Abstract: A single-transistor non-volatile memory cell MOS transistor with a floating gate and a control gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area wherein a tunneling of charge can take place between the drain and the floating gate by means of a system of applied voltages to the control gate and drain.

Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed to a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Abstract: A single transistor electrically programmable and erasable memory cell is disclosed. The single transistor has a source, a drain with a channel region therebetween, defined on a substrate. A first insulating layer is over the source, channel and drain regions. A floating gate is positioned on top of the first insulating layer over a portion of the channel region and over a portion of the drain region. A second insulating layer has a top wall which is over the floating gate, and a side wall which is adjacent thereto. A control gate has a first portion which is over the first insulating layer and immediately adjacent to the side wall of the second insulating layer. The control gate has a second portion which is over the top wall of the second insulating layer and is over the floating gate. Erasure of the cell is accomplished by the mechanism of Fowler-Nordheim tunneling from the floating gate through the second insulating layer to the control gate.

Abstract: A memory device for digital electronic signals includes at least one micro-mechanical memory element. The memory element includes a support having recess defined therein and a curved mechanical component bridging the recess and fixed to the support. The mechanical component has two stable positions, each of which being maintained by mechanical forces, one concave down towards the support and the other convex up away from the support. The mechanical component is adapted to be selectively changed from one stable position to the other stable position during a writing cycle and to have its stable position determined during a reading cycle so that the memory element can be used for storing binary logic information.

Abstract: A grooved separating region 112 having information electric charge storing capacitances C.sub.P formed on side surfaces thereof is formed to extend the region between the adjacent word line 107 in parallel with the word line 107. As a result, the grooved separating region 112 does not contact the channel region 111 of the gate transistors and does not intersect the word line 107.

Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Abstract: In a semiconductor memory device, a memory cell comprises a first MOS transistor (Q1) of a first channel type formed on a semiconductor substrate and having a gate electrode connected to a word line. A charge storage electrode is connected to the drain of the first transistor and forms a capacitor with the gate electrode. A semiconductor layer is formed over the charge storage electrode. A second MOS transistor (Q2) of a second channel type formed in the semiconductor layer. The charge storage electrode forms a gate electrode of the second transistor. The drain of the second transistor is connected to a power supply. The source of the second transistor is connected to a bit line, which is either the same as or separate from the first-mentioned bit line. For writing data, a first potential is applied to the word line to make conductive the first transistor for writing data, and the potential applied to the source of the first transistor is varied depending on whether the data to be written is "0" or "1".

Abstract: A one-transistor memory cell comprises a semiconductor body which has a thin insulating layer on a boundary surface and a conductive layer on the thin insulating layer, the conductive layer representing that electrode of a storage capacitor that is connected to a selection field effect transistor. The selection field effect transistor is realized in a layer applied as a polycrystalline semiconductor layer and is then recrystallized. The memory cell provides the smallest possible semiconductor surface. This is achieved in that the recrystallized semiconductor layer is disposed above the conductive layer 3 and is separated therefrom by an intermediate insulating layer, whereby it extends in the lateral direction, at most, up to the edge of the semiconductor layer 3.

Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Abstract: In a semiconductor memory device including memory and dummy cells connected to groups of data lines, word lines and dummy word lines for selecting the memory and dummy cells, respectively, and a signal detector for differentially amplifying the read signal from the memory cell selected by the signal of the word line and a reference signal from the dummy cell, the improvement wherein the memory cell capacitor consists of two capacitors, each having substantially the same structure as a dummy cell capacitor and connected in parallel with the other.

Abstract: A semiconductor memory device is provided with memory cells which each comprises an insulated gate type field effect transistor and a capacitor connected in series with one another and connected to bit lines. The capacitor is composed of a pair of electrodes and a dielectric film which includes a silicon nitride film existing between the pair of electrodes. One electrode of the capacitor is provided with a terminal to which a voltage is applied. The value of the applied voltage is chosen so that the voltage applied between the pair of electrodes is smaller in an absolute value than a voltage applied to the bit line.

Abstract: A semiconductor memory device of a one-transistor type is manufactured by using a so-called double-layer technology. The device comprises a buried-channel type transistor having normally-off characteristics and a capacitor having normally-on characteristics to provide high integrated density. An insulating layer between two conductive layers for forming the transistor and the capacitor is relatively thick to provide increased breakdown voltage and reduced parasitic capacitance.

Abstract: In a dynamic memory having a plurality of memory cells each of which consists of a MIS type field effect transistor and a charge storing capacitor connected thereto; a dynamic memory is disclosed wherein one electrode of the capacitor is made of a semiconductor layer which is formed on a semiconductor body through an insulating film and wherein a word line a part of which serves as a gate electrode of the MIS type field effect transistor is made of a conductor layer of multilayer structure which consists of a layer of semiconductor and a high-fusing metal layer containing the semiconductor.

Abstract: A memory cell comprises a double gate field effect transistor which exhibits source and drain regions located in a semiconductor body and two gate electrodes covering the semiconductor area between the source and drain regions, the gate electrodes being separated from the semiconductor body by a multilayer insulation. The first gate electrode is a memory gate, whereas inversion layers are produced with the second gate electrode given supply of a gate voltage, the inversion layers extending the source and drain regions in the direction towards the memory gate. The structure provides a surface-saving design of a selection element. The second gate electrode is employed for this purpose as the selection element and is connected to a selection line (word line). The invention finds application in very large scale integrated semiconductor memories.

Abstract: A dynamic memory is provided having a cell with an improved structure and made by an improved process which substantially reduces the capacitance of the bit/sense line connected to the cell. The cell has one field effect transistor and a storage node, and the cell structure includes a thick insulating segment located under a portion of a conductive layer or field shield and under a portion of the gate electrode of the transistor, while extending over the entire diffusion region of the bit/sense line and over substantially the entire depletion region surrounding the bit/sense line diffusion region.

Abstract: A dynamic RAM memory cell comprises an MOS read transistor whose conductivity state is determined by the state of charge on a first electrode overlying the read transistor channel region. The first electrode is connected through a buried contact opening to a diffused region in the substrate. This diffusion serves as a junction isolated storage node. This storage node can be charged or discharged through an MOS write transistor. The first electrode is capacitively coupled to a field plate held at a first potential. A control gate formed in a second electrode controls conduction through the write transistor and also allows selective reading in an array of read transistors. Nondestructive read can be achieved together with transistor amplification of the charge stored on the first electrode.

Abstract: An MNOS nonvolatile memory array employing single-element-per-bit storage and two-element-per-bit sensing utilizing a threshold referenced sense amplifier is organized such that the two legs of the sensing circuit are in substantial electrical balance during sensing.

Abstract: A high-density of semiconductor device is disclosed, which comprises a semiconductor substrate of a first conductivity type, first and second semiconductor regions of a second conductivity provided in the semiconductor substrate, the first and second semiconductor regions defining a channel region therebetween at the surface of the substrate, an insulator film disposed on the channel region, a conductive layer formed on the insulator film, means for producing depletion layers from the first and second semiconductor regions in such a manner that the depletion layers contact with each other to isolate the channel region from the substrate, means for selectively feeding majority carriers of the substrate to the channel region at a density higher than that of the substrate, and a means for detecting the existence of the accumulation of the majority carriers in the channel region.

Abstract: A semiconductor memory device of a surface-charge type comprises a p-type silicon substrate having a silicon dioxide film thereon and memory cells partly in the substrate and partly thereon in rows and columns. Each cell comprises an n.sup.+ -type region beneath the oxide film, a polysilicon layer on the oxide film, and an insulator film integral on the polysilicon layer with the oxide films at positions where the polysilicon layer is not present. The polysilicon layer comprises a p-type portion serving as a storage capacitor electrode and an n-type portion forming a p-n junction with the p-type portion. The n-type portion is common to cells of each column to serve as a transfer gate electrode and a word line. A metal film formed on the insulator film is connected to the n.sup.+ -type region of cells of each row to serve as a bit line.

Abstract: Disclosed is a memory system capable of being integrated into a semiconductor substrate and having an array of Hi-C memory cells. The Hi-C cells are selectively addressable by row and column lines. Each cell of the array is comprised of a transistor having a source coupled to a bit line, a gate coupled to a word line, and a drain coupled to a node N. Node N is coupled in parallel to a dielectric capacitor and to a depletion capacitor. The dielectric capacitor and the depletion capacitor are constructed to have substantially the same charge capacity.

Abstract: A one-transistor memory cell is provided in which the depletion-layer capacitance of an MOS capacitor is increased by locally enhancing the substrate dopant concentration. In preferred embodiments the substrate may also be doped adjacent to the substrate-insulator boundary with ions of appropriate conductivity type to form a diode junction in the substrate. The effective capacitance of the memory cell is therefore the capacitance of the insulator in parallel with the substantially increased depletion-layer or diode junction capacitance.

Abstract: A semiconductor memory has at least one V-MOS transistor which includes a trench and a storage capacitor. A semiconductor substrate is doped with concentration centers of a first conductivity type and has a buried layer which is doped with concentration centers of a second conductivity type opposite to the first conductivity type. At least two additional layers are divided by the trench and have alternately differing conductivity types, the two additional layers and the buried layer being produced by diffusion and/or implantation.

Abstract: A cell for a semiconductor memory of the static type employs only one conventional MOS transistor, along with a field implanted resistance and a vertical P-channel junction-type field effect transistor. These elements, along with a resistor element which may be another field implanted resistance or a polysilicon implanted resistance, provide a circuit which is stable with either a "1" or "0" stored. No clock or other refresh circuitry is needed.

Abstract: Semiconductor storage switching circuits and integrated circuit storage array devices that employ them are characterized by the fact that each individual cell of the storage array requires only a single active device, each such active device consisting of a three terminal, controlled-inversion device of metal, non-linear resistor, and semiconductor layers, the active device having controllable switching characteristics through the use of silicon dioxide, polycrystalline silicon, or nitrides of silicon in its non-linear resistive layer. Control circuits associated with the memory arrays make possible the unique selection of any one predetermined cell to write, erase, or read its content. Grounded base and grounded emitter forms of the storage devices are provided, as well as random access memory devices.

Abstract: An IGFET integrated circuit memory cell structure utilizing a capacitor with increased charge storage capability, and a method making the same. The capacitor includes a high impurity concentration region having the same conductivity type as the substrate. An island of opposite conductivity type is inset in the region and a conductive field plate overlies the island. The structure also includes a transfer transistor in which the source region is adjacent the capacitor and overlaps the island region therein. Activation of the transistor serves to transfer the charge stored in the capacitor to the drain region where it can be read by external circuitry. In the method, the high concentration region and island in the capacitor are formed by successive ion implantation steps.

Abstract: A memory circuit arrangement employing one-transistor-per-bit memory cells in which differential sense amplifiers are utilized for detecting the state of the stored bits. First and second digit lines are arranged substantially parallel to and adjacent to each other and first and second parallel word lines are arranged substantially at right angles to the digit lines. Memory cells are connected at each cross point between the digit lines and the word lines.

Abstract: A memory circuit including one-transistor-per-bit memory cells arranged in a matrix array of m and n columns, one capacitor, and n differential amplifiers associated with the n respective column. The memory array is divided into first and second row groups and each differential amplifier has a first input terminal connected to memory cells belonging to the first row group and associated with one of the n columns and a second input terminal connected to memory cells associated with the second row group and connected to the same column that is connected to the first terminal. The memory circuit also includes an output amplifier having two input terminals, a plurality of first and second switching means associated with respective columns and controlling means for controlling the first and second switching means. The first and second switching means, associated with the same column may be selected and controlled by the same controlling means.

Abstract: The present invention relates to a memory circuit including an array of inversion controlled switches arranged in an arbitrary number of rows and columns. Each inversion controlled switch is provided with emitter, base and collector terminals, and is characterized by first and second impedance states between its emitter and collector terminals.

Abstract: A memory is formed by a first insulating layer provided on a part of the surface of a semiconductor substrate of a first conductivity type, a first electrode provided on the first insulating layer and a surface region which serves as an electrode on the semiconductor substrate facing the first electrode. A semiconductor region of a second conductivity type is formed in the semiconductor substrate spaced from the surface electrode of the substrate, for providing a connection thereof to a digit line. A second electrode is provided between the second conductivity type semiconductor region and the surface region which serves as an electrode of the semiconductor substrate via a second insulating layer. The second electrode extends over a third insulating layer provided on the first electrode, and the extended portion of the second electrode is provided with an electrode secured thereto for providing a connection of the second electrode to an address selection line.