Abstract: A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.

Abstract: A static random access memory (SRAM) with cells in one portion having a higher beta ratio than the remaining cells of the array. In a first portion, cells have a low &bgr; ratio for high performance. A second portion of the array contains SRAM cells with a higher &bgr; ratio that are more stable than the cells in the first portion, but are somewhat slower.

Abstract: A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically OR'ing or AND'ing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).

Abstract: A semiconductor memory device capable of saving power supply voltage and power consumption without increasing the forming area of memory cell array by using MTCMOS technology. In writing data in a memory cell 50-21, a signal RE is turned “H” level, an NMOS 61-1 is turned off and a virtual ground line VGND1 is turned into floating state. When the signal RE is “H” level, the output level of an AND circuit 64-2 turns “L” level and NMOS 55a and 55b turn off. NMOS 53 and 54 turn on by “H” level of a word line WL2 and data in a bit line pair BL1 and BL/ is held on nodes N11 and N12. In reading out data, the signal RE is turned “L” level. When the NMOS 61-1 turns on and the VGND 1 becomes connected to GND, an acceleration circuit 55 accelerates the speed of readout operation.

Abstract: A method and apparatus for soft defect detection in a memory is disclosed. Bit lines are conditioned to predetermined voltages which ensure that, upon activation of the corresponding word line, all the storage transistors within the corresponding bit cells (at the intersection of the bit lines and the word line) are electrically conductive. A change in state of the bit cell in response to activation of the corresponding word line indicates the presence of a soft defect. An evaluator coupled to the memory may be used to identify defective memories by comparing the results of the testing to determine if any bit cells changed states. In one embodiment, the conditioning of the bit lines includes charging a bit line to a first predetermined voltage and its corresponding complementary bit line to a second predetermined voltage and then connecting the bit line and complementary bit line together to equalize the voltages.

Abstract: An ultra high-speed DDP-SRAM (Dual Dual-Port Static Random Access Memory) cache having a cache speed in approximately the GHz range. This is accomplished by (1) a specially designed dual-port SRAM whose size is slightly larger than that of a conventional single port SRAM, and (2) the use of a dual dual-port SRAM architecture which doubles its speed by interleaved read and write operations. A first embodiment provides a 6-T (transistor) all nMOS dual-port SRAM cell. A second embodiment provides a dual port 7T-SRAM cell which has only one port for write, and both ports for read.

Abstract: A power supply potential GNDP as a substrate potential of two N-channel MOS transistors constructing an SRAM transistor memory cell is enabled to be controlled independent of a ground potential GNDM as a source potential of the N-channel MOS transistors. In the case where a standby current failure occurs, by weakening the driving ability of the N-channel MOS transistors by a substrate effect, the failure can be found in a functional test. A defective memory cell as a cause of the standby current failure, in which a small leak occurs can be specified and is replaced by a redundant memory cell, thereby enabling the yield to be improved.

Abstract: A dynamic random access memory device includes a memory plane including at least one first matrix of memory cells, a read/write amplifier connected to the end of each column of the matrix, and at least one pair of input/output lines associated with the matrix. The dynamic random access memory device also includes at least one cache memory stage connected to each amplifier and is disposed in the immediate vicinity of this amplifier. The cache memory stage includes a static random access memory cell connected between the read/write amplifier and the pair of input/output lines.

Abstract: A method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line. A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line. A first state node transistor is also formed of the first transistor type.

Abstract: A four-transistors SRAM cell, which could be viewed as at least including two word line terminals, comprises following elements: first word line terminal, second word line terminal, first bit line terminal, second bit line terminal, first transistor, second transistor, third transistor, and fourth transistor. Whereby, gate of first transistor is coupled to first word line terminal and source of first transistor is coupled to the first bit line terminal, gate of second transistor is coupled to second word line terminal and source of second transistor is coupled to second bit line terminal, source of third transistor is coupled to drain of first transistor and gate of third transistor is coupled to drain of second transistor, source of fourth transistor is coupled to drain of second transistor and gate of fourth transistor is coupled to drain of first transistor.

Abstract: A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (Vf) of the tunnel diode (32) controls the Vgs transfer curve (56) of the load transistor. The tunnel diode (32) may be formed at a junction between a mono-crystalline silicon layer (88) at a region (98, 100) which also serves as a source or drain of a transistor (36, 54) and a poly-crystalline silicon layer (106). The poly-crystalline silicon layer (106) also serves as a non-metallic, conductive interconnection (55) to save space.

Abstract: A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, and a set of isolation transistors. The set of isolation transistors is coupled to the first set of cross-coupled transistors such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.

Abstract: The present invention relates to a ferromagnetic tunnel magnetoresistance effect element having a multilayered structure comprising a tunnel barrier layer and a first and a second ferromagnetic layer formed to sandwich the tunnel barrier layer therebetween, wherein the tunnel barrier layer is formed as an oxide film obtained by oxidizing a non-magnetic metal layer according to a radical oxidation method. Thus, there can be obtained a ferromagnetic tunnel magnetoresistance effect element which is excellent in productivity and quality stability and highly excellent in TMR effect.

Abstract: A static RAM which features an inclusion of a word line driving circuit shared by all the memory cells in the static RAM is disclosed. The static RAM is comprised of a plurality of four-transistor memory cells arranged in an array. Each of the memory cells includes first and second FETs respectively coupled to bit lines and controlled by word line potential. Further, each of the memory cells further comprises third and fourth cross-coupled FETs respectively coupled in series with the first and second FETs and forming a circuit having two stable states. The word line driving circuit reflects a stable state potential change of each of the plurality of memory cells, and controls an output voltage thereof which is applied to the plurality of memory cells in order to maintain the stable state potential in each of the plurality of memory cells.

Abstract: In some embodiments, the invention includes an integrated circuit including a bitline and a bitline#, wordlines, and memory cells. The memory cells each corresponding to one of the wordlines and each include first and second pass transistors coupled between first and second storage nodes, respectively, and the bitline and bitline#, respectively, the corresponding wordline being coupled to gates of the first and second pass transistors. The memory cells include first and second inverters cross-coupled between the first and second storage nodes, wherein the first and second pass transistors each have a lower threshold voltage than do transistors of the first and second inverters. Wordline voltage control circuitry coupled to the wordlines selectively controls wordline signals on the wordlines.

Abstract: A method of operating a memory cell includes detecting a first power supply anomaly or condition. When the first power supply condition occurs, memory cell access to bit lines is disabled, a series of shadow memory access FETs within the memory cells are enabled and data from the memory cells are coupled to memory FETs within the memory cells to store data corresponding to the data from the memory cells in the memory FETs. The memory FETs include nanocrystals of semiconductor material in gate dielectrics of the FETs. Electrons are stored in the nanocrystals of semiconductor material to represent the data stored in the memory cell. When a second power supply condition is detected, the data stored in the memory FETs are written back to the memory cells.

Abstract: A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (V.sub.f) of the tunnel diode (32) controls the V.sub.gs transfer curve (56) of the load transistor.

Abstract: A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process.

Abstract: An apparatus and method for constructing a capacitor loaded memory cell. This capacitor loaded memory cell operates as a static random access memory (SRAM) cell if a particular capacitor and transistor configuration is used. Normally, capacitors are not an obvious choice as a load device for a memory cell because the intrinsic nature of capacitors is one that blocks the flow of direct current, the invention takes into account the secondary effects such as leakage of a particular dielectric used in the construction of the capacitor to modify the current blocking nature of the capacitor.

Abstract: The SRAM cell configuration has at least six transistors in each memory cell. Four of the transistors form a flip-flop and they are arranged at the corners of a quadrilateral. The flip-flop is driven by two of the transistors, which are disposed so as to adjoin diagonally opposite corners of the quadrilateral and outside the quadrilateral. Adjacent memory cells along a word line can be arranged in such a way that a first bit line and a second bit line of the adjacent memory cells coincide. The transistors are preferably vertical and are arranged at semiconductor structures (St1, St2, St3, St4, St5, St6) produced from a layer sequence. Two of the transistors having n-doped channel regions are preferably formed in each case on two semiconductor structures.

Abstract: A non-volatile memory cell includes a well region formed in a semiconductor substrate. First and second avalanche injection elements reside in the well region. A bifurcated floating-gate electrode includes a first segment overlying the first avalanche injection element and a second segment overlying the second avalanche injection element. A first contact region resides in the well region adjacent to the first segment of the floating-gate electrode, and a second contact region resides in the well region adjacent to the second segment of the floating-gate electrode. Upon the application of programming or erasing voltage, electrical charge is independently transferred to each of the first and second segments of the floating-gate electrode from the first and second avalanche injection elements, respectively.

Abstract: A zero-power non-volatile memory cell includes a control element, an avalanche injection element, and a CMOS inverter. A floating-gate electrode is capacitively coupled to the control element, the avalanche injection element, and to the CMOS inverter. The avalanche injection element is arranged, so as to transfer electrical charge onto the floating-gate electrode. The presence of stored data within the memory cell is indicated by reading a supply voltage V.sub.DD at an output terminal of the inverter. Accordingly, data can be read from the non-volatile memory cell without applying electrical power to the cell.

Abstract: A memory cell includes a static inverter having an input connected to a storage node. An impedance connects the storage node to a voltage supply. A first transistor, having an input connected to an output of the static inverter, connects the storage node to a write line. Lastly, a second transistor, responsive to a wordline access signal, connects the storage node to a single data bitline. The memory cell further includes a single ended four transistor CMOS SRAM cell. Additionally, a memory array is disclosed which includes a plurality of memory cells arranged to form a matrix of rows and columns, each memory cell including a single ended four transistor CMOS SRAM cell.

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: The low power data line and method may comprise a line (30, 102) connecting a plurality of devices (60, 104) to an output (32, 104). The devices (60, 104) may be independently accessed to provide data to the output (32) along the line (30, 102). A switch (40, 120) may be disposed in the line (30, 102) to selectively disconnect a segment (52, 132) of the line (30, 102) connected to at least one of the devices (60, 104) from the output (32).

Abstract: In a method for operating an SRAM MOS transistor memory cell, the memory cell comprises a 6-transistor memory cell composed of two inverters with feedback, each of which is connected to a bit line via a selection transistor which is driven by a word line. Both selection transistors are switched on when writing information to the memory cell. Only the first selection transistor is switched on, the other selection transistor remaining switched off, when reading the contents of the cell. In this way, the charge on only one bit line is changed when reading.

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: A semiconductor memory device includes cells arranged in a matrix formation. Each of the cells includes a driver transistor, a read transistor which is controlled by a read word line and outputs read data read from the cell to a read bit line, a write transistor which is controlled by a write word line and supplies write data supplied from a write bit line to a cell capacitor connected to a gate of the driver transistor, and a column write select transistor which is controlled by a column write select signal line and is connected to the write transistor in series. The write data is supplied to the cell capacitor via both the column write select transistor and the write transistor.

Abstract: An SRAM memory cell is provided in which a pair of cross-coupled n-type MOS pull-down transistors are coupled to respective parasitically formed bipolar pull-up transistors. The memory cell is formed within a semiconductor layer which extends over a buried layer. The bipolar transistors are formed parasitically from the buried layer and the semiconductor layer used to form the pull-down transistors. The bases of the bipolar transistors may also be dynamically controlled. An SRAM memory array having a plurality of such memory cells and a computer system incorporating the SRAM memory array are also provided.

Abstract: A memory cell for storing data having at least three logic states includes a pair of storage devices and third-level storage and refresh circuitry coupled to a pair of storage nodes. The storage devices maintain multi-level signals representative of first and second logic states at the pair of storage nodes. To store a third logic state, the third-level storage and refresh circuitry maintain the multi-level signals at both storage nodes at substantially equal intermediate levels.

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: A semiconductor memory device of a three-transistor cell type dynamic random-access memory with improved performances includes a circuit arranged between a write bit line and a read bit line. During a read operation, the circuit generates a voltage difference responsive to information that is stored in the memory cell during a read operation. A latch-type sense amplifier amplifies and latches the voltage difference between the write bit line and the read bit line. When information is read from a memory cell, the information in the memory cell amplified by the latch-type sense amplifier is read through the read bit line while being written to the memory cell via the write bit line to refresh the information in the memory cell.

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: A memory cell having programming voltage margin verification is provided. The memory cell includes a voltage comparator having a differential input with first and second inputs and bias circuitry for generating a differential input voltage. A voltage offset is applied to the second input of the comparator to provide an input offset voltage. A programming voltage is received for programming the memory cell and the memory cell provides an output signal. To verify an unprogrammed state voltage margin of the memory cell, a margin detection circuitry receives a verification check signal and the output is monitored to determine whether the unprogrammed state voltage margin is proper. To verify a proper programmed state voltage margin of the memory cell, current is sensed through the programming input and a determination of a proper programmed state voltage margin is determined as a function of the sensed current.

Abstract: A static random access memory cell having a plurality of active regions defined on a semiconductor substrate, includes a plurality of first bulk transistors having a first common gate electrode and first impurity-doped regions, the first common gate electrode and first impurity-doped regions being formed on a portion of the active regions; a plurality of second bulk transistors spaced from the first bulk transistors, the second bulk transistors including a second common gate electrode and second impurity-doped regions, the second common gate electrode and second impurity-doped regions being formed on a portion of the active regions; and a plurality of thin film transistors formed on the second bulk transistors and including the second common gate electrode and a conductive layer formed above the second common gate electrode, wherein the conductive layer overlaps and is substantially coextensive with the second common gate electrode.

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: An analog memory circuit of the present invention includes: a recording circuit for recording and holding an input analog signal as a charge and for reading out the analog signal after deterioration of the analog signal caused by leakage of the charge in a holding operation is eliminated; a selecting circuit for controlling an operation of the recording circuit; and a driving circuit for supplying a predetermined constant voltage to the recording circuit, wherein the recording circuit includes: an input/output terminal for inputting and outputting the analog signal; a first capacitor having a first electrode and a second electrode, for recording and holding the analog signal as the charge; and a second capacitor connected between the second electrode of the first capacitor and a reference potential, for holding a charge leaked from the first capacitor, and wherein an amount of charge corresponding to an amount of leaked charge held in the second capacitor is restored to the first capacitor with predetermined

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: SRAM cells are manufactured with balanced, high-resistance load resistances by having substantially all of dielectric layer directly over the polysilicon load resistor covered by a metal layer. The metal layer protects the polysilicon during subsequent processing which can adversely alter its characteristics.

Abstract: A static RAM memory is arranged into groups of four cells sharing a single active region with a contact to one of the bit lines. The shared active region forms the sources of four access transistors. The group of four cells requires only one pair of bit lines instead of the usual two pairs of bit lines. Thus a pair of bit lines occurs for every two cells rather than for every cell. This increases the bit-line pitch and facilitates design and layout of the sense amps. Since only one of the four cells can drive the bit lines at any time, four word lines are used instead of only two. Each cell has two word lines crossing over it, and the cells in a row alternately connect to one or the other word line. Since word-line drivers and decoders are simpler and easier to lay out than the sense amps, the tighter word-line pitch is acceptable. An unused metal line occurs for every two columns of cells. The bit lines are shielded from this unused metal line by power and ground lines.

Abstract: A dynamic random access memory circuit for storing an information signal using both a data input line and a data output line for a two-transistor dynamic ram cell memory circuit is disclosed. The circuit is incorporated into an integrated circuit array of similar cells. Because of the nature of the circuitry, the data input and output lines of each cell in the array are laid out in parallel, and the data-out line of one random access memory cell becomes the data-in line of the adjacent random access memory cell. Thus, while the addition of a separate line for data-in and data-out adds structure to a single cell, it reduces the overall structure of an array of such cells, and results in a more compact construction of a memory array.

Abstract: A three dimensional latch and bulk silicon pass transistor for high density field reconfigurable architectures is provided utilizing bulk silicon with a layer of polysilicon or silicon on insulator (SOI) thereover. The pass transistor, which must have very low resistance to provide a good short circuit path between the metal runs and fast switching speed, is fabricated in the bulk silicon wherein the resistivity can be made very low relative to polysilicon and because only the pass transistor is disposed in the bulk silicon, thereby permitting the dimensions thereof to be increased to provide even lower resistance. Since only the latch is fabricated in the layer of polysilicon or SOI and is disposed over the pass transistor, the amount of chip area utilized can be the same or less than required in the prior art wherein all circuitry was in the bulk silicon.

Abstract: Adjacent memory cells has a two-layer structure formed of first layer and second layer. The first layer is provided with driver transistors of the memory cell, access transistors of the memory cell, and driver transistors formed of the memory cell. The second layer is provided with load transistors of the memory cell, load transistors and of the memory cell, and access transistors of the memory cell. The transistors formed in the first layer are of an NMOS type, and the transistors formed in the second layer are of a PMOS type.

Abstract: A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

Abstract: A semiconductor memory device comprises a layout of a plurality of memory cells each including a pair of device regions, a pair of driver transistors respectively formed on the respective device regions of the pair and having gates and drains thereof cross-connected to each other, a pair of transfer transistors respectively formed on the respective device regions of the pair and controlled by a word line, a pair of load devices respectively disposed in the respective driver transistors of the pair, the pair of transfer transistors having a gate layer formed on the pair of device regions; and the word line being formed so as to cross the pair of driver transistors thereabove and being in contact with the gate layer of the pair of transfer transistors. No region is necessary for mask alignment between the word lines and the gate layer, and an area of a memory cell can be reduced.

Abstract: The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a static random access memory cell (110) having a vertical n-channel field-effect transistor (116) and a vertical p-channel field-effect transistor (115) and methods of forming them. In one embodiment, a six-transistor static random access memory cell (110) has two pass transistors (111 and 114), which are planar n-channel field-effect transistors, two latch transistors (113 and 116), which are vertical n-channel field-effect transistors with drain regions having graded diffusion junctions (31), and two load transistors (112 and 115), which are vertical p-channel thin-film field-effect transistors having laterally recessed channel regions (92).

Abstract: A semiconductor memory circuit includes a plurality of memory cells arranged in an array form, a plurality of data lines for reading and writing data, a plurality of address lines each for transferring an address signal that specifies a corresponding specific memory cell, a control unit for controlling reading and writing of the data, a plurality of data input and data output terminals for inputting and outputting the data, a write enable signal input terminal to which a write enable signal for permitting writing of the data is applied, and at least one control signal input terminal to which either a cell clear signal for clearing the data stored or a cell initialization signal for performing the initialization of the data is applied. Data reading, data writing and data clearing or data initializing are performed through the plurality of data lines and the plurality of address lines.