Abstract: A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read transistor. A sense amplifier senses and amplifies a difference in voltage between a bit line and a sense node that is developed when the read transistor permits or does not permit current to flow between ground an a bit line. Associated semiconductor device structures and fabrication techniques are also disclosed.

Abstract: A device is provided for static random access memories (SRAM's), including an apparatus capable of executing more than one kind of logical operation for each memory cell, with a relatively small number of elements, and the same configuration for different types of operations. These operations include (1) the normal read-out/write-in operations; (2) inverting the contents of one sequence of memory cells and storing either the result or the result shifted one bit to the right in a second sequence of memory cells; (3) storing the result of an OR operation between two sequences of memory cells in a third sequence of memory cells; and (4) initializing each memory cell. The left or right node potential of each memory cell may also be individually accessed. Each operation between memory cells is simultaneous with the direct writing of the result into other memory cells, so no temporary holding cells are required and the operation is accomplished at high speed.

Abstract: A single poly EE cell and an array using said cell, with the array being provided electrical connections such that the select gate for the read select transistor and the select gate for the write select transistor may be separately controlled. In the array, first level metal is utilized for connection to the gates of the read and write select transistors and second level metal is utilized for connection to the product term connections of the cell.

Abstract: A memory cell constructed in accordance with the present invention includes a node operable to present an electrical level representing a first state or a second state. Further included is a first switching device having a first terminal connected to the node such that if the first switching device were to close, the electrical level at the node would be connected to a second terminal of the first switching device. Additionally, second and third switching devices are provided both having first and second terminals and both operable to switch as a function of the state at the node. Finally, a single control switching device is provided in association with the second and third switching devices wherein a control signal switches the control switching device such that the state at the node may be determined by connecting to the first terminals of the second and third switching devices.

Abstract: Disclosed is a TFT for a semiconductor memory device and the fabricating method thereof, comprising a first conductive layer formed on a first insulating layer of a semiconductor substrate and doped with a first conductive type impurity, a second insulating layer formed on the first conductive layer, a contact hole formed in the second insulating layer above the first conductive layer, a semiconductor layer formed on a predetermined portion of the first conductive layer exposed in the contact hole, the inner walls of the contact hole and the second insulating layer, a thin-film gate insulating layer covering the semiconductor layer, a second conductive layer formed on a gate insulating layer to overlap the contact hole and its periphery, a first impurity region formed while upwardly dispersing the impurity of the first conductive layer into the semiconductor layer in contact with the first conductive layer of the contact hole, a second impurity region placed in the semiconductor layer of the second insulating

Abstract: A dynamic memory cell includes a first MOS transistor for data transfer connected at one end to a read/write node and having a gate connected to a transfer gate control line, a second MOS transistor having a gate connected to a first storage node on the other end side of the first MOS transistor and a gate capacitor used as a data storage capacitor, a third MOS transistor for refresh current supply connected at one end to the first storage node, and a resistor element or switching element connected between the gate of the third MOS transistor and the other end of the second MOS transistor. The cell itself has the refresh current supplying capability and it is not necessary to effect the refresh operation on the read/write node side by turning on the charge transfer transistor.

Abstract: In a static memory, a memory cell is constituted by only the same-channel MOSFETs. With the MOSFETs of the same channel, no well isolation region is required, and a cell size can be decreased. Moreover, the high potential side power source of a flip-flop can be used as a read word line. Thus the read word line can be driven by an ECL logic circuit.

Abstract: A compact cell design for a static random access memory cell is achieved. The cell has two transistors with gates substantially parallel to each other. One interconnect connects the gate of one transistor to an electrode of the other transistor. Another interconnect connects the gate of the other transistor to an electrode of the first transistor. The two gates and the two interconnects form substantially a rectangle. A power supply circiut line is disposed outside the rectangle. This line and the two interconnects are formed from one conductive layer.

Abstract: A stacked static random access memory SRAM having a plurality of memory cells is disclosed. Individual memory cell has a portion formed in an upper active element layer in the device structure and a portion formed in a lower active element layer in the device structure separated from the upper layer by an intermediate insulating layer. A word line, a bit line and access transistors are formed in the same upper active element layer, eliminating the need for interconnecting them through the insulating layer. The elimination of the inter-layer connections helps to reduce the number of through-holes required to be made in the insulating layer. This in turn reduces the area to be occupied by the memory cell and leads to a simplified manufacturing process of the SRAM.

Abstract: A semiconductor associative memory device comprises a content addressable memory cell connected to a word line, a bit line, an inversion bit line and a match line. The memory cell comprises first and second n channel MOS transistors constituting a capacitance element. When the word line is activated, a value on the bit line is stored in the first n channel MOS transistor, and the value on the inversion bit line is stored in the second n channel MOS transistor. When the first n channel MOS transistor and the bit line are in the active state, or when the second n channel MOS transistor and the inversion bit line are in the active state, a control terminal is activated. N channel MOS transistors are connected between the control terminal and the first and second n channel MOS transistors, and the first and second n channel MOS transistors are refreshed during matching and reading by means of these transistors.

Abstract: A static storage cell is formed of two cross-coupled inverters each containing a field effect transistor and a resistor element connected in series therewith. Each circuit node is thus connected via an additional logic element to a bit line allocated thereto. A storage cell is provided which is on as small as possible a semiconductor area and has a short access time. This is achieved by designing the additional logic elements as hot electron transistors which are respectively combined with one of the field effect transistors to form a common component which only requires the area of a field effect transistor. The cell is useful in VLSI semiconductor memories.

Abstract: A CMOS static memory cell comprising a bistable circuit is described. A grounded p-type region separates the p-channel transistors of the circuit from the n-channel transistors. This p-type region reduces latch up problems and permits polysilicon lines to be routed over the region. The resultant memory cell is of higher density than prior art cells.

Abstract: A logic circuit comprises a first and second circuit. The first circuit consists of at least one first conductivity-type MOSFET having a gate connected to an input terminal, and having a first current path connected at one end to an output terminal. The second circuit consists of at least one second conductivity-type MOSFET having a gate is connected to the input terminal, and having a second current path connected at one end to the output terminal. The logical circuit further comprises a depletion-type MOSFET of the second conductivity type and a depletion-type MOSFET of the first conductivity type. The depletion-type MOSFET of the second conductivity type has a threshold voltage the absolute value of which is larger than that of the first conductivity-type MOSFET, has a current path connected between the other end of the first current path and a first power source, and has a gate connected to the output terminal.

Abstract: A controllable impedance means is connected in series with the conduction path of transistors forming a complementary inverter for selectively "skewing" the inverter in a direction to center its toggle point with respect to the signals applied to the inverter input. The "skewed" inverter is thereby compensated for offsets or asymmetry in its input signals. Also disclosed is the use of skewed inverters to form memory cells which can be easily written to both binary conditions. Also disclosed is the use of the controllable impedances as "cross-unders" to enable the fabrication of very compact "skewable" inverters and memory cells.

Abstract: A unique topography of I.sup.2 L bipolar semiconductor elements provides Read-Write Random Access Memory (RAM) with very high packing density, low cost, and good power and speed characteristics and with a very simple metallization pattern.

Abstract: An improved READ/WRITE circuit for a memory array of cells arranged in rows and columns, where each cell is coupled to a bit line via the conduction path of a single gating transistor which conducts in the source follower mode for one binary condition. The circuit includes a voltage multiplying circuit having an output at which is selectively produced either a read voltage, or a write voltage of significantly greater amplitude than the read voltage. The output of the voltage multiplying circuit is coupled via a level shifting decoder circuit, which passes either the read or the write voltage, to the control electrodes of selected gating transistors. The read voltage applied to the control electrode of a gating transistor turns it on just enough to enable the non-destructive-readout (NDRO) of the contents of its associated memory cell.

Abstract: An integrated semiconductor memory device of the static type uses a memory cell circuit having an MOS transistor of the conventional type as the access transistor, along with a resistance element buried under field oxide and an inverted field-effect transistor formed by a polycrystalline layer over a gate region. The MOS transistor connects a storage node to the access line, and the inverted field-effect transistor connects the storage node to reference potential. The storage node is connected to a second node through the resistance element, and a resistor connects the second node to a voltage supply; the magnitude of the resistance element varies according to the voltage on the storage node. The impedance of the inverted field-effect is determined by the voltage on the second node which is a moat region forming the gate.

Abstract: A bipolar memory cell of reduced size requires only four I.sup.2 L operated transistors and three access lines. Two current injection transistors supply operating current to two inversely operated flip-flop transistors and also function as load devices as well as coupling devices. The three access lines conduct power to the cells as well as the signals for the write and read operations. A write operation is performed by ratioing the currents supplied to a memory cell array such that only a selected cell is written.

Abstract: An active storage or memory cell includes first and second high input impedance inverters cross coupled to form a flip-flop. The output impedance of the second inverter is significantly lower than the output impedance of the first inverter. Input signals are applied at, and information is read out from, a single input-output point common to the output of the second inverter and the input of the first inverter via a gating means connected between said input-output point and an input-output line which is turned on more slowly than it is turned off.