Multiplexing Patents (Class 365/189.02)
  • Patent number: 11031075
    Abstract: A high bandwidth register file circuit that significantly reduces the shared local read bitline RC delay to enable ultra-high performance PRFs with high port counts. In one example, the register file circuit includes read stack nfets in a multiplexer circuit instead of the memory cell causing the local read bitline RC to be independent of the number of read and write ports of the memory cell.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: June 8, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Hoan Huu Nguyen, Francois Ibrahim Atallah, Keith Alan Bowman, Jihoon Jeong
  • Patent number: 11016885
    Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Robert Walker, Chandrasekhar Nagarajan
  • Patent number: 11017128
    Abstract: Apparatus and method for transferring data between a processing circuit and a memory. In some embodiments, a data storage device has a main non-volatile memory (NVM) configured to store user data from a host device. A controller circuit is configured to direct transfers of the user data between the NVM and the host device. The controller circuit has a programmable processor and a secure data transfer circuit. The secure data transfer circuit executes memory access operations to transfer user data and control values between the processor and a local memory. A memory access operation includes receiving bits of a multi-bit control value on a multi-line bus from the processor, and activating a programmable switching circuit to randomly interconnect different ones of the multi-line bus to transpose the bits in the control value.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: May 25, 2021
    Assignee: Seagate Technology LLC
    Inventor: Timothy J. Courtney
  • Patent number: 11016670
    Abstract: A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: May 25, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Takuya Futatsuyama
  • Patent number: 11004502
    Abstract: A storage unit and a static random access memory (SRAM), where storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first metal-oxide-semiconductor (MOS) transistor. A gate of the first MOS transistor is coupled to the first storage bit, a source of the first MOS transistor is coupled to a first read line, and a drain of the first MOS transistor is coupled to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line, or in a second state, the second read line is a read word line, and the first read line is a read bit line. The storage unit according to embodiments of the present invention can implement an exchange between a read word line and a read bit line.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: May 11, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Sijie Chi, Bingwu Ji, Tanfu Zhao, Yunming Zhou
  • Patent number: 10998015
    Abstract: A semiconductor storage device includes a memory array at which writing and reading of plural data are carried out, one pair of write registers that temporarily store write data that is to be written into the memory array, and one pair of read registers that temporarily store read data that is read-out from the memory array.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: May 4, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Toshio Inada, Katsuaki Matsui
  • Patent number: 10964364
    Abstract: A semiconductor device includes a plurality of stacked dies electrically connected with each other. Each of the stacked dies includes a data path, a strobe path, a stack information generation circuit, and a delay control circuit. The data path transmits a data signal. The strobe path transmits a data strobe signal. The stack information generation circuit generates stack information representing a number of the dies. The delay control circuit controls a delay time of at least one of the data path and the strobe path based on the stack information.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Kwan Su Shon, Yo Han Jeong
  • Patent number: 10908838
    Abstract: Apparatuses, systems, and methods are presented for column replacement. An input register, which includes a set of input divisions, may receive write data for a memory array. An output register, which includes a set of normal output divisions and a set of replacement output divisions, may output write data to an array. A column replacement circuit may selectively couple input divisions to output divisions. A column replacement circuit may couple normal output divisions for functional columns of an array to corresponding input divisions. A column replacement circuit may couple replacement output divisions for functional columns of an array to input divisions selected by the column replacement circuit, which may be corresponding input divisions or other input divisions.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: February 2, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Dike Zhou, Yen-Lung Li
  • Patent number: 10902904
    Abstract: Apparatuses and methods for providing multiphase clocks are disclosed. An example apparatus includes a plurality of clock circuits, each configured to provide one of the multiphase clocks responsive to a respective input clock. The apparatus further includes first and second control circuits. The first control circuit receives a first one of the multiphase clocks and a reset signal provided to the plurality of clock circuits, and provides a first control signal to reset a clock circuit of the plurality of clock circuits that is based on the first one of the multiphase clocks and the reset signal. The second control circuit receives the control clock and a second one of the multiphase clocks and provides a second control signal to clock the clock circuit of the plurality of clock circuits that is based on the control clock and the second one of the multiphase clocks.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shingo Mitsubori, Kenji Mae
  • Patent number: 10896130
    Abstract: Methods and systems for pre-fetching operations include executing event callbacks in an event loop using a processor until execution stops on a polling request. A path walk is performed on future events in the event loop until the polling request returns to pre-fetch information for the future events into a processor cache associated with the processor. Execution of the event callbacks in the event loop is resumed after the polling request returns.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: January 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Michael H. Dawson, Gireesh Punathil
  • Patent number: 10877731
    Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: December 29, 2020
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Bob Haig, Chao-Hung Chang
  • Patent number: 10867665
    Abstract: An SRAM bit-cell with independent write and read ports and an architecture utilizing a feedback loop from the read port to the write port of half-selected bit-cells. This guarantees absolute data retention of all SRAM bit-cells not fully selected for write operation across a wide range of supply voltage spanning from the nominal voltage of a process to a sub-threshold range.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: December 15, 2020
    Assignee: Synopsys, Inc.
    Inventors: Prashant Dubey, Jamil Kawa, Kritika Aditya
  • Patent number: 10838808
    Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 17, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Indu Prathapan, Prashanth Saraf, Desmond Pravin Martin Fernandes, Saket Jalan
  • Patent number: 10832788
    Abstract: A semiconductor device has a memory circuit and a logic circuit coupled with a memory circuit. the memory circuit included a memory array in which memory cells are arranged in a matrix, an input/output circuit for writing data to the memory cells and reading data from the memory cells, and a control circuit for generating a control signal for controlling the input/output circuit. In a test operation for testing the logic circuit, the input/output circuit receives a test data. The control circuit raises and lowers the control signal based on a rising and a falling of an external clock signal, thereby the test data is output to the logic circuit via the input/output circuit.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: November 10, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuichiro Ishii
  • Patent number: 10832771
    Abstract: A semiconductor memory device includes a first transistor connected between a high voltage line connected to a first end of a memory element and a first power supply terminal, and a second transistor connected between the high voltage line and a second power supply terminal, a third transistor connected between a low voltage line connected to a second end of the memory element and a third power supply terminal, and a fourth transistor connected between the low voltage line and a fourth power supply terminal. The second and fourth transistors satisfy the condition: |Vth|<|VG?VB|+VF, where Vth is a threshold voltage thereof, VG is a voltage difference between a gate and a source or drain thereof, VB is a bias voltage applied to a body thereof, and VF is a minimum voltage at which a parasitic diode current flows.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takayuki Miyazaki
  • Patent number: 10818359
    Abstract: Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Aaron P. Boehm, Fa-Long Luo
  • Patent number: 10817199
    Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dongsik Cho
  • Patent number: 10817008
    Abstract: A semiconductor device includes a circuit-to-be-adjusted in which an output characteristic thereof can be adjusted by a fuse that is controlled based on a fuse signal. The semiconductor device includes a control circuit using, as a power source, an internal power source that has a converted voltage obtained by converting a voltage of an external power source, the control circuit being configured to generate control signals A, B based on an inputted test signal, the control signals being able to adjust the circuit-to-be-adjusted in place of the fuse signal. The semiconductor device includes a selector circuit that selects the fuse signal before the internal power source reaches a stable state after the external power source is turned on, and selects the control signal CS after the internal power source has reached a stable state.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 27, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Takuya Matsumoto
  • Patent number: 10811083
    Abstract: Some embodiments include an integrated assembly having a first memory array which includes a first column of first memory cells. A first digit line extends along the first column and is utilized to address the first memory cells of the first column. A second memory array is proximate to the first memory array and includes a second column of second memory cells. A second digit line extends along the second column and is utilized to address the second memory cells of the second column. A primary-sense-amplifier comparatively couples the first digit line with the second digit line. A first secondary-sense-amplifier is along the first digit line, and a second secondary-sense-amplifier is along the second digit line.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 10802909
    Abstract: Methods, systems, and devices for operating memory cell(s) using an enhanced bit flipping scheme are described. An enhanced bit flipping scheme may include methods, systems, and devices for performing error correction of data bits in a codeword concurrently with the generation of a flip bit that indicates whether data bits in a corresponding codeword are to be flipped; for refraining from performing error correction of inversion bit(s) in the codeword; and for generating a high-reliability flip bit using multiple inversion bits. For instance, a flip bit that is even more reliable may be generated by determining whether a number of, a majority of, or all of the inversion bits indicate that the data bits are in an inverted state.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Richard E. Fackenthal
  • Patent number: 10803924
    Abstract: Systems and methods include capture circuitry configured to capture a write signal from a host device using a data strobe signal from the host device and to output one or more indications of capture of the write signal. Calculation circuitry is configured to receive the data strobe signal, receive the one or more indications of capture, and determine a delay between a first edge of the data strobe signal and receipt of the one or more indications of capture. The systems and methods also include transmission and control circuitry configured to launch subsequent write signals at a time based at least in part on the delay.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ming-Bo Liu, Daniel B. Penney
  • Patent number: 10783968
    Abstract: A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Thanh K. Mai, Gary L. Howe
  • Patent number: 10783935
    Abstract: A sense amplifier driving device is disclosed. The device includes a cell array, a bias current generation unit connected to the cell array via a bit line, a sense amplifier connected to the cell array via the bit line to detect and amplify a bit line voltage of the bit line, and a latch unit that outputs the detected bit line voltage as an output signal in a read operation of the cell array. The sense amplifier includes a precharge transistor that precharges the bit line based on a first voltage during a programming operation of the cell array, a read voltage convey unit connected to the bit line and operates during a read operation of the cell array, and a sensing unit that outputs an output voltage based on the bit line voltage.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: September 22, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Duk Ju Jeong
  • Patent number: 10768831
    Abstract: Apparatuses and methods related to implementing a non-persistent unlock state for secure memory. Implementing the non-persistent unlock state can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated following the placement of the protected region in a non-persistent unlocked mode. If the row of the memory array corresponding to the access command is activated, then the protected region can be placed on a locked mode.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Naveh Malihi
  • Patent number: 10755766
    Abstract: An example apparatus comprises an array of memory cells coupled to sensing circuitry including a first sense amplifier, a second sense amplifier, and a logical operation component. The sensing circuitry may be controlled to sense, via first sense amplifier, a data value stored in a first memory cell of the array, sense, via a second sense amplifier, a data value stored in a second memory cell of the array, and operate the logical operation component to output a logical operation result based on the data value stored in the first sense amplifier and the data value stored in the second sense amplifier.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 10754812
    Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes first-in first-out (FIFO) cells included in an asynchronous FIFO unit and first and second circuits included in the asynchronous FIFO unit. The first circuit provides first information based on a value of a first bit from each of the FIFO cells in order to select one of the FIFO cells to be a selected FIFO cell for storing data information in the selected FIFO cell. The second circuit provides information based on a value of a second bit from each of the FIFO cells in order to select one of the FIFO cells to be a selected FIFO cell for reading data information from the selected FIFO cell.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: August 25, 2020
    Assignee: Intel IP Corporation
    Inventor: Vinod Pagare
  • Patent number: 10714151
    Abstract: The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 14, 2020
    Assignee: ULTRAMEMORY INC.
    Inventors: Yasutoshi Yamada, Kouji Uemura, Takao Adachi
  • Patent number: 10714166
    Abstract: Memories having block select circuitry having an output that is selectively connected to a plurality of driver circuitries, each driver circuitry connected to a respective block of memory cells, as well as methods of operating such memories.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Aaron S. Yip
  • Patent number: 10705934
    Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Donald G. Mikan, Jr., Hao-I Yang, Kao-Cheng Lin, Ming-Chien Tsai, Saman M. I. Adham, Tsung-Yung Chang, Uppu Sharath Chandra
  • Patent number: 10686080
    Abstract: A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Nakagawa, Yoshiyuki Kurokawa, Munehiro Kozuma
  • Patent number: 10663514
    Abstract: An internal net of a digital circuit is virtually probed while performing a dynamic functional stimulation that includes changing vectors asserted to a dynamic functional interface. A JTAG SAMPLE command is triggered through a JTAG interface at a timing during the dynamic functional stimulation by controlling the timing of a JTAG TCK rising clock edge. Captured JTAG SAMPLE data is shifted out to the JTAG interface. The JTAG SAMPLE data, which includes the logic states of internal nets at a chosen timing during the dynamic functional stimulation, are stored. A sequence database is built by repeating the test with incrementally different JTAG rising clock edge timings.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Artisan Electronics, Inc.
    Inventors: Greg Gossett, Thomas Barclay, Carrol Wade Poff
  • Patent number: 10665279
    Abstract: A memory device includes a memory bank; a first latch circuit positioned at the one side of the memory bank, for latching a first column address in synchronization with a first strobe signal; a second latch circuit positioned at the other side of the memory bank, for latching a second column address in synchronization with a second strobe signal; a first column decoder positioned at the one side of the memory bank, for generating first column select signals in synchronization with the first strobe signal and the first column address; and a second column decoder positioned at the other side of the memory bank, for generating second column select signals in synchronization with the second strobe signal and the second column address.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventor: Tae-Kyun Kim
  • Patent number: 10665270
    Abstract: An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 26, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Patent number: 10658062
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Patent number: 10651114
    Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yu Lin, Kao-Cheng Lin, Li-Wen Wang, Yen-Huei Chen
  • Patent number: 10622083
    Abstract: In connection with data pin timing calibration with a strobe signal, examples provide for determination of pass/fail status of a pin from multiple pass/fail results in a single operation. Determination of pass/fail results for multiple pins based on multiple applied trim offsets can be made in parallel. Accordingly, a time to determine pass/fail results from multiple trim values for a pin can be reduced, which can enable faster power-up of NAND flash devices.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Varsha Regulapati, Heonwook Kim, Aliasgar S. Madraswala, Naga Kiranmayee Upadhyayula, Purval S. Sule, Jong Tai Park, Sriram Balasubrahmanyam, Manjiri M. Katmore
  • Patent number: 10613918
    Abstract: Aspects of the present disclosure are directed to assessing characteristics of stored data, as may be implemented for verification thereof. As may be implemented in connection with one or more apparatus or method-based embodiments, a first data signature is generated, which corresponds to a logical derivation of configuration data sent over a data bus. Outputs that correspond to data read out from each of a plurality of configuration registers, which receive the configuration data over the data bus, are logically combined into a second data signature. The first data signature and the second data signature are processed and compared for ascertaining that stored data, as stored in each of the plurality of configuration registers, accurately corresponds to the configuration data sent over the data bus for writing into each of the plurality of configuration registers.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: April 7, 2020
    Assignee: NXP B.V.
    Inventors: Peter van de Haar, Lucas Pieter Lodewijk van Dijk
  • Patent number: 10607666
    Abstract: A data transfer device may include: a global input/output (GIO) driver configured for driving input data and outputting the driven data to a first GIO line, and configured for using a second supply voltage lower than a first supply voltage as a source voltage to drive the input data; and a repeater configured for amplifying data applied to the first GIO line, outputting the amplified data to a second GIO line, and shifting the data applied to the first GIO line to a level of the first supply voltage. The repeater may drive the data applied to the first GIO line to a first node, drive an output of the first node to the second GIO line, and reset the first node to the level of the first supply voltage based on a reset signal before a read operation.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventor: Yun Seok Hong
  • Patent number: 10607692
    Abstract: A data output device includes: a plurality of storage devices coupled in parallel to store input data, and having a storage region with a predetermined depth; and a selector suitable for selecting an output of any one storage device among the plurality of storage devices.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventors: Jae-Hyeong Kim, Amal Akbar
  • Patent number: 10586606
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Patent number: 10579760
    Abstract: Forming a logic circuit design from a behavioral description language that includes N force and M release statements applied to a net disposed in the design, includes, in part, forming N multiplexers and a controller controlling the select terminals of the N multiplexers. Each multiplexer receives a force signal at its first input terminal. The output signal of the ith multiplexer is supplied to a second input terminal of (i+1)th multiplexer. A driver signal driving the net in the absence of the force statements is applied to a second input terminal of a first multiplexer. The controller asserts the select signal of the ith multiplexer if the ith force condition is active, and unasserts the select signal of the ith multiplexer if any one of a number of predefined conditions is satisfied.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 3, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Ionut Silviu Cirjan, Boris Gommershtadt, Dmitry Korchemny, Naphtali Yehoshua Sprei
  • Patent number: 10566044
    Abstract: Method and Apparatuses for transmitting and receiving commands for a semiconductor device are described. An example apparatus includes: a memory device including a plurality of banks, each bank including a plurality of memory cells; and a memory controller that transmits a first command and a plurality of address signals indicative of a memory cell in a first bank of the plurality of banks at a first time. The first command is indicative of performing a first memory operation, and a second memory operation different from the first memory operation. The memory device receives the first command and the plurality of address signals and further performs the second memory operation to the first bank responsive, at least a part, to the plurality of address signals and the first command.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: February 18, 2020
    Assignee: Micron Technology LLP
    Inventor: Michael Richter
  • Patent number: 10566036
    Abstract: Apparatuses and methods for reducing sense amplifier leakage current during an active power-down are disclosed. An example apparatus includes a memory that includes a memory cell and a first digit line and a second digit line. The memory cell is coupled to the first digit line in response to activation of a wordline coupled the memory cell. The example apparatus further includes a sense amplifier comprising of a first transistor coupled between the first digit line and a first gut node of the sense amplifier and a second transistor coupled between the second digit line and a second gut node of the sense amplifier. While the wordline is activated, in response to entering a power-down mode, the first transistor is disabled to decouple the first digit line from the first gut node and the second transistor is disabled to decouple the second digit line from the second gut node.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Christopher Kawamura
  • Patent number: 10510401
    Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semicondutor Manufacturing Company Limited
    Inventors: Chien-Yuan Chen, Che-Ju Yeh, Hau-Tai Shieh, Cheng-Hung Lee, Hung-Jen Liao, Sahil Preet Singh, Manish Arora, Hemant Patel, Li-Wen Wang
  • Patent number: 10498215
    Abstract: A voltage regulator includes a first feedback loop and a second feedback loop. The first feedback loop includes a charge pump outputting a first output voltage, a first transistor ladder and a control circuit. The first transistor ladder divides the first output voltage to generate a first feedback voltage. The control circuit receives the first feedback voltage and controls a level of the first output voltage according to the first feedback voltage and a reference voltage. The second feedback loop includes a power transistor, a second transistor ladder and an operational amplifier. The power transistor receives the first output voltage to output a second output voltage. The second transistor ladder divides the second output voltage to generate a second feedback voltage. The operational amplifier outputs a control signal to the power transistor by receiving the second feedback voltage and a reference voltage selected from one of a plurality of levels.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: December 3, 2019
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan Tang, Jen-Tai Hsu
  • Patent number: 10489061
    Abstract: A first rank includes a plurality of first semiconductor memory devices, and a second rank includes a plurality of second semiconductor memory devices. The command/address signal lines are shared by a controller, the first rank, and the second rank, and the data lines are shared by the controller, the first rank, and the second rank. When performing a data movement operation of moving data between the first rank and the second rank, the controller applies a shift read command to one of the first rank and the second rank through the command/address signal lines and applies a normal write command or a shift write command to another of the first rank and the second rank through the command/address signal lines after a time corresponding to a value obtained by subtracting the value of the write latency from the value of the read latency.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: November 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong Jin Lee, Ji Hyun Choi
  • Patent number: 10482972
    Abstract: Memories include a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Frankie F. Roohparvar
  • Patent number: 10460781
    Abstract: A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a memory array of addressable memory cells and a pipeline configured to process read and write operations addressed to the memory bank. Further, the memory device comprises an x decoder circuit coupled to the memory array for decoding an x portion of a memory address for the memory array and a y multiplexer circuit coupled to the memory array and operable to simultaneously multiplex across the memory array based on two y portions of memory addresses and, based thereon with the x portion, for simultaneously writing a value and reading a value associated with two separate memory cells of the memory array, wherein the x decoder and the y multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to the memory array.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 29, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele, Daniel Hillman
  • Patent number: 10452588
    Abstract: A semiconductor device includes first input/output circuits for a first channel, first input/output pads corresponding to the first input/output circuits, respectively, wherein the first input/output pads are aligned along and extends in a first direction, second input/output circuits for the first channel, second input/output pads corresponding to the second input/output circuits, respectively, wherein the second input/output pads are aligned along and extends in a second direction, and an input circuit between the first input/output pads and the second input/output pads, and connected to a memory to which the input circuit inputs data from the first input/output circuits and the second input/output circuits. The input circuit is positioned such that a first line extending perpendicular to the first direction from one of the first input/output pads and a second line extending perpendicular to the second direction from one of the second input/output pads intersect a portion of the input circuit.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 22, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mikihiko Ito, Masaru Koyanagi
  • Patent number: 10438952
    Abstract: A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: October 8, 2019
    Assignee: TC Lab, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng