Abstract: The present disclosure includes apparatuses and methods for data transfer between subarrays in memory. An example may include a first subarray of memory cells and a second subarray of memory cells, wherein a first portion of memory cells of the first subarray and a first portion of memory cells of the second subarray are coupled to a first sensing circuitry stripe. A third subarray of memory cells can include a first portion of memory cells coupled to a second sensing circuitry stripe. A second portion of memory cells of the second subarray and a second portion of memory cells of the third subarray can be coupled to a third sensing circuitry stripe. A particular row of the second array can include memory cells from the first portion of memory cells in the second array coupled to memory cells from the second portion of memory cells in the second array.

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might include an array of memory cells. An example apparatus might also include a plurality of sensing components coupled to the array and comprising a first group of sensing components coupled to a controller via a first number of control lines and a second group of sensing components coupled to the controller via a second number of control lines wherein the controller is configured to activate at least one of the first number of control lines and the second number of control lines.

Abstract: A dual-domain dynamic multiplexer and a method of transitioning between asynchronous voltage and frequency domains. One embodiment of the dual-domain dynamic multiplexer includes: (1) a first domain having a first voltage and a first clock, and a second domain having a second voltage and a second clock, (2) a plurality of data and data select input pairs wherein a data input of an input pair is in the first domain and a data select input of an input pair is in the second domain, and (3) a pre-charge stage in the second domain that is energized upon an edge of the second clock, whereby one data and data input pair is enabled and data latched in the second domain upon another edge of the second clock.

Abstract: Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.

Abstract: Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. The scan cell may include an output phase having multiple latches arranged to receive the scan input signal, the first address signal, or the second address signal from the input phase and provide the scan input signal, the first address signal, or the second address signal as a scan output signal based on a second clock signal and a third clock signal.

Abstract: A multiple instruction, multiple data memory device includes a memory array with several sections, one or more multiplexers between the sections and a decoder. Each section has memory cells arranged in rows and columns. The cells in a row are connected by a read enabled word line and by a write enabled word line. The decoder includes a decoder memory array which generally simultaneously activates a plurality of read enabled word lines in several sections, a plurality of write enabled word lines in several sections and one or more multiplexers. The decoder memory array includes several bit lines oriented perpendicularly to and connected to the rows of the memory array. A method of activating in-memory computation using several bit lines of a decoder memory array, connected to rows of the memory array to simultaneously activate several read enabled word lines, several write enabled word lines and one or more multiplexers.

Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.

Abstract: A semiconductor device that has a normal mode of operation and a test mode of operation and can include: a first circuit that generates at least one assist signal having an assist enable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device as compared to read or write operations when the assist signal has an assist disable logic level; and the first circuit generates the at least one assist signal having the assist disable logic level in the test mode of operation.

Abstract: Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to both drive latched data and conduct read and write operations. For example, a memory device may contain two or more memory arrays independently coupled to two drivers via two data lines. One data line may be driven strongly to shield a corresponding memory array from effects associated with data line capacitive coupling. An opposing data line may be driven with data pertaining to an access operation of the memory array to which it is coupled. The opposing data line may be driven concurrently or within a small time difference of the other data line.

Abstract: A circuit includes a memory cell array which includes: a plurality of memory cells; a plurality of word lines coupled to the memory cells, respectively, and a plurality of bit lines coupled to the memory cells, an address control circuit which includes: a first latch circuit into which a first address signal is input and from which a first output signal is output; a selection circuit into which a second address signal and the first output signal are input and which selects the first output signal or the second address signal for outputting the first output signal or the second address signal as a second output signal; a second latch circuit into which the second output signal is input and from which a third output signal is output; a decode circuit which decodes the third output signal and outputs a fourth output signal; and a word line drive circuit.

Abstract: A memory array includes a first column of memory cells, a second column of memory cells, a first pre-charge circuit, a second pre-charge circuit and a set of input output circuits. The first column of memory cells includes a first bit line, a first word line and a first bit line bar. The second column of memory cells includes the first bit line bar, a second word line and a second bit line. The first pre-charge circuit is coupled to the first bit line. The second pre-charge circuit is coupled to the first bit line bar. The first column of memory cells and the second column of memory cells are configured to share the first bit line bar. The first bit line and the first bit line bar are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane.

Abstract: Systems and methods of testing integrated circuits are disclosed. A system may include a data compression component to compress data received from an integrated circuit under test at a first clock frequency, to generate compressed data. The system may also include a data output component, operatively coupled to the data compression component, to convey the compressed data to automated testing equipment at a second clock frequency.

Abstract: A method of operating a semiconductor device can include determining in which of a plurality of voltage windows the first power supply potential is located; changing at least one voltage window signal when the first power supply potential moves from one voltage window into another of the voltage windows; detecting a change in the at least one voltage window signal; and generating at least one read assist signal in response to the at least one voltage window signal; wherein the at least one read assist signal alters a read operation to a static random access memory (SRAM) cell, as compared to the read operation without the at least one read assist signal.

Abstract: A semiconductor device includes a latch signal generation circuit latching an external signal in synchronization with an internal clock signal to generate a latch signal, a test pulse generation circuit buffering the internal clock signal according to the latch signal to generate a test pulse signal, and a test period signal generation circuit generating a test period signal which is enabled, in response to a pulse of the test pulse signal, to execute a predetermined function.

Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.

Abstract: Various embodiments include apparatus and methods having a data receiver with a real time clock decoding decision feedback equalizer. In various embodiments, a digital decision feedback loop can be implemented in a data receiver circuit, while all analog signals involved are static relative to the input signal data rate. The implemented data receiver circuit can include a number of data latches with different, but static, analog unbalances and a decision-based clock decoder. In an example, the analog unbalances may be different reference voltages. The decision-based clock decoder can be structured to activate only one data latch, the one with the desired analog unbalance. The outputs of the latches attached to the same clock decoder can be combined such that only the active latch drives the final output. Additional apparatus, systems, and methods are disclosed.

Abstract: An SRAM facility adapted to power an address path using a first developed supply voltage and to power a data path using a second developed supply voltage, the first and second developed power supplies being separate, distinct, and different. The SRAM facility includes a power supply facility or a voltage supply facility adapted to develop the first and second supply voltages.

Abstract: A dynamic NOR circuit includes a pre-charge transistor coupled between a first voltage supply node and a dynamic node to pre-charge the dynamic node. The dynamic NOR circuit includes a first keeper circuit having a first keeper transistor and a second keeper transistor serially coupled between the first voltage supply node and the dynamic node. The dynamic NOR circuit includes a first pull down circuit coupled between the dynamic node and ground. A first input signal is coupled to a gate of a first pull-down transistor in the first pull-down circuit and is also coupled to a gate of the first keeper transistor. A first keeper enable signal is coupled to a gate of the second keeper transistor. Additional keeper circuits and pull down circuits coupled to the dynamic node allow the dynamic NOR structure to handle a plurality of input signals.

Abstract: A memory device may include a plurality of memory cells; a refresh counter suitable for generating a refresh address; an address storage circuit suitable for storing an additional refresh address; an error detection unit suitable for detecting an error of selected memory cells of the plurality of memory cells in response to a refresh command in a detection period; and a refresh control unit suitable for refreshing memory cells corresponding to the refresh address or the additional refresh address among the memory cells in response to the refresh command, and controlling the refreshing of the memory cells to be delayed in the detection period.

Abstract: Disclosed is a content addressable memory (CAM). The content addressable memory array includes a memory array and a data match module. The memory array includes multiple memory rows. Each memory row is configured to store a first data word and a second data word. The data match module includes a first match circuitry configured to compare a first match word to the first data word of a memory row, and to generate a first match output based on the comparison between the first match word and the first data word of the memory row. The data match module further includes a second match circuitry configured to compare a second match word to the second data word of the memory row, and to generate a second match output based on the comparison between the second match word and the second data word of the memory row.

Abstract: Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.

Abstract: A semiconductor device includes an input/output control circuit configured to generate a first driving signal and a second driving signal by shifting a latency signal in synchronization with a clock, and generating a strobe signal which toggles according to logic levels of the first driving signal and the second driving signal; and a data input/output circuit configured to latch input data in synchronization with the strobe signal, and outputting the latched input data as output data.

Abstract: A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions. The data pattern providing unit is configured to provide a predefined data pattern. The write circuit is configured to, when a first write command and an address signal are received from an external device, write the predefined data pattern provided from the data pattern providing unit to a memory region corresponding to the address signal.

Abstract: Method and system for predicting an oil temperature of a transformer for a desired load and/or predicting a load that a transformer can support for a desired time. A machine learning algorithm is developed using historical data of a transformer. After the algorithm is developed, historical data corresponding to the transformer are input into the algorithm to develop a profile of the transformer describing how the temperature of oil within the transformer is expected to change as a function of a desired load. Using the profile, the of temperature of the transformer is predicted for a desired load. In this way, a prediction is made as to whether and/or for how long a transformer may support a desired load before the oil temperature reaches a specified threshold and/or before the transformer fails due to the load.

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.

Abstract: Techniques and mechanisms for a SIP to control access to a non-volatile memory of another packaged device. In an embodiment, the SIP includes interface a processor, a local memory and a memory controller that provides the processor with access to the local memory. The SIP further includes interface hardware to couple the SIP to the packaged device, wherein the processor of the SIP accesses a non-volatile memory of the packaged device via the memory controller of the SIP. In another embodiment, the interface hardware of the SIP includes a first plurality of contacts to couple to the packaged device, as well as a second plurality of contacts. An interface standard describe an arrangement of interface contacts, wherein, of a first arrangement of the first contacts and the second arrangement of the second contacts, only the second arrangement conforms to the described arrangement of interface contacts.

Abstract: A memory array includes a first column of memory cells, a second column of memory cells and a set of switching elements. The first column of memory cells includes a first bit line, a first word line and a second bit line. The second column of memory cells includes the second bit line, a second word line and a third bit line. The first and second column of memory cells are configured to share the second bit line. The first and second bit lines are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane. An amount of bit line switching elements in the set of bit line switching elements is equal to N*2, where N is an amount of columns of memory cells in the memory array.

Abstract: Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.

Abstract: A method can of operating a semiconductor device can include generating a read or write assist signal having an enable logic level in response to a power supply potential being in a first voltage window and a disable logic level in response to the power supply potential being in a second voltage window. Access operations to a static random access memory (SRAM) cell can be altered in response to the assist signal having the assist enable logic level. The second voltage window can be larger than the first voltage window.

Abstract: A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.

Abstract: In some embodiments, extemporaneous control of remote objects can be made more natural using the invention, enabling a participant to pivot, tip and aim a head-mounted display apparatus to control a remote-controlled toy or full-sized vehicle, for example, hands-free. If the vehicle is outfitted with a camera, then the participant may see the remote location from first-person proprioceptive perspective.

Abstract: A multiport memory includes an address control circuit, a memory array, a data input-output circuit and a control circuit and first and second address signals and a clock signal are input through two ports. The address control circuit includes first and second latch circuits, a selection circuit, a decode circuit and a word line drive circuit. The first address signal input through one port is input into the first latch circuit and the second address signal input through the other port is input into the selection circuit. The selection circuit selects one of the first and second address signals, the second latch circuit latches and outputs the selected address signal to the decode circuit. The word line drive circuit drives a word line on the basis of an output signal from the decode circuit.

Abstract: In one aspect, a method includes receiving an I/O, incrementing a first counter in an active data structure in a backlog at a splitter after receiving the I/O, storing I/O metadata of the I/O in the active data structure, incrementing a second counter in the active data structure or a passive data structure in the backlog if the I/O was written to a storage array and received by the data protection appliance and incrementing a third counter in the active data structure or the passive data structure if either the I/O was not written to a storage array or not received by the data protection appliance.

Abstract: A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.

Abstract: Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

Abstract: A memory circuit includes a memory cell, a first bit line, a first bit line bar, a sense amplifier, a first switch and a second switch. The memory cell is coupled with a first bit line having a first bit line portion and a second bit line portion. The first bit line bar has a first bit line bar portion and a second bit line bar portion. The sense amplifier includes a read/write circuit configured to couple the second bit line portion to a global bit line. The first switch is coupled between the first bit line bar portion and the second bit line bar portion. The second switch is coupled between the first bit line portion and the second bit line portion.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to process data to form codewords and to send the codewords to the memory to be stored at locations of the memory that are restricted based on a non-adjacency pattern.

Abstract: A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register have a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.

Abstract: A group of low-level FIFOs may be logically bound together to form a super-FIFO. The super-FIFO may treat each low-level FIFO as a storage location. The super-FIFO may enable a push to (or a pop from) every low-level FIFO, simultaneously. The super-FIFO may enable a virtual channel (VC) to use the super-FIFO, bypassing a VC FIFO for the VC, removing several cycles of latency otherwise needed for enqueuing and dequeuing messages in the VC FIFO. In addition, the super-FIFO may enable bypassing of an arbiter, further reducing latency by avoiding a penalty of the arbiter.

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Abstract: A memory circuit using dynamic random access memory (DRAM) arrays. The DRAM arrays can be configured as CAMs or RAMs on the same die, with the control circuitry for performing comparisons located outside of the DRAM arrays. In addition, DRAM arrays can be configured for secure authentication where, after the first authentication performed with a non-volatile secure element, subsequent authentications can be performed by the DRAM array. Input patterns can be loaded into a DRAM array by loading logic state ones (“1”) into each of the plurality of input data bit lines in each of the columns in the DRAM array and shunting one or more of the plurality of input data bit lines in the DRAM array corresponding to logic state zeroes (“0”) in the input pattern.

Abstract: A system includes a first application and a storage layer running on a cloud computing device, where the first application includes a service layer to interface over a network with a browser application running on a client computing device to provide the browser application access to the first application and a tagging module to interface over a communication connector with a second application running on a remote computing device having a database. The service layer receives requests for data from the first application and provides the requested data from the database. The tagging module is configured to tag a record of the data in response to tag requests from the first application, where the record of the data is tagged by generating an item reference to the record to enable a customized view of the data. The storage layer is configured to store the item references.

Abstract: An apparatus and method are described for reducing power when reading and writing graphics data. For example, one embodiment of an apparatus comprises: a graphics processor unit (GPU) to process graphics data including floating point data; a set of registers, at least one of the registers of the set partitioned to store the floating point data; and encode/decode logic to reduce a number of binary 1 values being read from the at least one register by causing a specified set of bit positions within the floating point data to be read out as 0s rather than 1s.

Abstract: A method for reducing current consumption of a memory is disclosed, wherein the memory includes a controller and a plurality of banks, and each bank of the plurality of banks includes a plurality of segments. The method includes the controller enabling an activating command corresponding to a first row address and an address of a first bank of the plurality of banks; a word line switch of a segment of the first bank corresponding to the first row address being turned on according to the activating command; the controller enabling an access command corresponding to an address of the segment; a plurality of bit switches corresponding to the segment being turned on according to the access command; and the controller enabling a pre-charge command corresponding to an address of a following segment and the address of the first bank after the access command is disabled.

Abstract: A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC.

Abstract: A memory 2 includes a regular array of storage elements 4. A regular array of write multiplexers 8 is provided outside of the regular array of storage elements 4. The storage element pitch is matched to the write multiplexer pitch. The write multiplexers 10 support a plurality of write ports. When forming a memory design 2, a given instance of an array of write multiplexers 8 may be selected in dependence upon the desired number of write ports to support and this combined with a common form of storage element array 4.

Abstract: An input circuit of a memory device includes an input receiver to receive an input signal, a clock receiver to receive a clock signal, a data latch, an input signal delay path coupled to the input receiver and configured to provide a delayed internal input signal to the data latch, a first clock signal delay path coupled to the clock receiver and configured to provide a first delayed internal clock signal, a second clock signal delay path coupled to the input receiver and configured to provide a second delayed internal clock signal, and a multiplexer coupled to receive and select one of the first delayed internal clock signal and the second delayed internal clock signal in response to a test mode control signal, and to provide the selected signal to the data latch.

Abstract: Disclosed is a content addressable memory (CAM). The content addressable memory array includes a memory array and a data match module. The memory array includes multiple memory rows. Each memory row is configured to store a first data word and a second data word. The data match module includes a first match circuitry configured to compare a first match word to the first data word of a memory row, and to generate a first match output based on the comparison between the first match word and the first data word of the memory row. The data match module further includes a second match circuitry configured to compare a second match word to the second data word of the memory row, and to generate a second match output based on the comparison between the second match word and the second data word of the memory row.