Abstract: A semiconductor memory device includes a first transistor connected between a high voltage line connected to a first end of a memory element and a first power supply terminal, and a second transistor connected between the high voltage line and a second power supply terminal, a third transistor connected between a low voltage line connected to a second end of the memory element and a third power supply terminal, and a fourth transistor connected between the low voltage line and a fourth power supply terminal. The second and fourth transistors satisfy the condition: |Vth|<|VG?VB|+VF, where Vth is a threshold voltage thereof, VG is a voltage difference between a gate and a source or drain thereof, VB is a bias voltage applied to a body thereof, and VF is a minimum voltage at which a parasitic diode current flows.

Abstract: A semiconductor device has a memory circuit and a logic circuit coupled with a memory circuit. the memory circuit included a memory array in which memory cells are arranged in a matrix, an input/output circuit for writing data to the memory cells and reading data from the memory cells, and a control circuit for generating a control signal for controlling the input/output circuit. In a test operation for testing the logic circuit, the input/output circuit receives a test data. The control circuit raises and lowers the control signal based on a rising and a falling of an external clock signal, thereby the test data is output to the logic circuit via the input/output circuit.

Abstract: A semiconductor device includes a circuit-to-be-adjusted in which an output characteristic thereof can be adjusted by a fuse that is controlled based on a fuse signal. The semiconductor device includes a control circuit using, as a power source, an internal power source that has a converted voltage obtained by converting a voltage of an external power source, the control circuit being configured to generate control signals A, B based on an inputted test signal, the control signals being able to adjust the circuit-to-be-adjusted in place of the fuse signal. The semiconductor device includes a selector circuit that selects the fuse signal before the internal power source reaches a stable state after the external power source is turned on, and selects the control signal CS after the internal power source has reached a stable state.

Abstract: Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.

Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

Abstract: Some embodiments include an integrated assembly having a first memory array which includes a first column of first memory cells. A first digit line extends along the first column and is utilized to address the first memory cells of the first column. A second memory array is proximate to the first memory array and includes a second column of second memory cells. A second digit line extends along the second column and is utilized to address the second memory cells of the second column. A primary-sense-amplifier comparatively couples the first digit line with the second digit line. A first secondary-sense-amplifier is along the first digit line, and a second secondary-sense-amplifier is along the second digit line.

Abstract: Systems and methods include capture circuitry configured to capture a write signal from a host device using a data strobe signal from the host device and to output one or more indications of capture of the write signal. Calculation circuitry is configured to receive the data strobe signal, receive the one or more indications of capture, and determine a delay between a first edge of the data strobe signal and receipt of the one or more indications of capture. The systems and methods also include transmission and control circuitry configured to launch subsequent write signals at a time based at least in part on the delay.

Abstract: Methods, systems, and devices for operating memory cell(s) using an enhanced bit flipping scheme are described. An enhanced bit flipping scheme may include methods, systems, and devices for performing error correction of data bits in a codeword concurrently with the generation of a flip bit that indicates whether data bits in a corresponding codeword are to be flipped; for refraining from performing error correction of inversion bit(s) in the codeword; and for generating a high-reliability flip bit using multiple inversion bits. For instance, a flip bit that is even more reliable may be generated by determining whether a number of, a majority of, or all of the inversion bits indicate that the data bits are in an inverted state.

Abstract: A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.

Abstract: A sense amplifier driving device is disclosed. The device includes a cell array, a bias current generation unit connected to the cell array via a bit line, a sense amplifier connected to the cell array via the bit line to detect and amplify a bit line voltage of the bit line, and a latch unit that outputs the detected bit line voltage as an output signal in a read operation of the cell array. The sense amplifier includes a precharge transistor that precharges the bit line based on a first voltage during a programming operation of the cell array, a read voltage convey unit connected to the bit line and operates during a read operation of the cell array, and a sensing unit that outputs an output voltage based on the bit line voltage.

Abstract: Apparatuses and methods related to implementing a non-persistent unlock state for secure memory. Implementing the non-persistent unlock state can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated following the placement of the protected region in a non-persistent unlocked mode. If the row of the memory array corresponding to the access command is activated, then the protected region can be placed on a locked mode.

Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes first-in first-out (FIFO) cells included in an asynchronous FIFO unit and first and second circuits included in the asynchronous FIFO unit. The first circuit provides first information based on a value of a first bit from each of the FIFO cells in order to select one of the FIFO cells to be a selected FIFO cell for storing data information in the selected FIFO cell. The second circuit provides information based on a value of a second bit from each of the FIFO cells in order to select one of the FIFO cells to be a selected FIFO cell for reading data information from the selected FIFO cell.

Abstract: An example apparatus comprises an array of memory cells coupled to sensing circuitry including a first sense amplifier, a second sense amplifier, and a logical operation component. The sensing circuitry may be controlled to sense, via first sense amplifier, a data value stored in a first memory cell of the array, sense, via a second sense amplifier, a data value stored in a second memory cell of the array, and operate the logical operation component to output a logical operation result based on the data value stored in the first sense amplifier and the data value stored in the second sense amplifier.

Abstract: The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units.

Abstract: Memories having block select circuitry having an output that is selectively connected to a plurality of driver circuitries, each driver circuitry connected to a respective block of memory cells, as well as methods of operating such memories.

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.

Abstract: A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.

Abstract: An internal net of a digital circuit is virtually probed while performing a dynamic functional stimulation that includes changing vectors asserted to a dynamic functional interface. A JTAG SAMPLE command is triggered through a JTAG interface at a timing during the dynamic functional stimulation by controlling the timing of a JTAG TCK rising clock edge. Captured JTAG SAMPLE data is shifted out to the JTAG interface. The JTAG SAMPLE data, which includes the logic states of internal nets at a chosen timing during the dynamic functional stimulation, are stored. A sequence database is built by repeating the test with incrementally different JTAG rising clock edge timings.

Abstract: A memory device includes a memory bank; a first latch circuit positioned at the one side of the memory bank, for latching a first column address in synchronization with a first strobe signal; a second latch circuit positioned at the other side of the memory bank, for latching a second column address in synchronization with a second strobe signal; a first column decoder positioned at the one side of the memory bank, for generating first column select signals in synchronization with the first strobe signal and the first column address; and a second column decoder positioned at the other side of the memory bank, for generating second column select signals in synchronization with the second strobe signal and the second column address.

Abstract: An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

Abstract: In connection with data pin timing calibration with a strobe signal, examples provide for determination of pass/fail status of a pin from multiple pass/fail results in a single operation. Determination of pass/fail results for multiple pins based on multiple applied trim offsets can be made in parallel. Accordingly, a time to determine pass/fail results from multiple trim values for a pin can be reduced, which can enable faster power-up of NAND flash devices.

Abstract: Aspects of the present disclosure are directed to assessing characteristics of stored data, as may be implemented for verification thereof. As may be implemented in connection with one or more apparatus or method-based embodiments, a first data signature is generated, which corresponds to a logical derivation of configuration data sent over a data bus. Outputs that correspond to data read out from each of a plurality of configuration registers, which receive the configuration data over the data bus, are logically combined into a second data signature. The first data signature and the second data signature are processed and compared for ascertaining that stored data, as stored in each of the plurality of configuration registers, accurately corresponds to the configuration data sent over the data bus for writing into each of the plurality of configuration registers.

Abstract: A data transfer device may include: a global input/output (GIO) driver configured for driving input data and outputting the driven data to a first GIO line, and configured for using a second supply voltage lower than a first supply voltage as a source voltage to drive the input data; and a repeater configured for amplifying data applied to the first GIO line, outputting the amplified data to a second GIO line, and shifting the data applied to the first GIO line to a level of the first supply voltage. The repeater may drive the data applied to the first GIO line to a first node, drive an output of the first node to the second GIO line, and reset the first node to the level of the first supply voltage based on a reset signal before a read operation.

Abstract: A data output device includes: a plurality of storage devices coupled in parallel to store input data, and having a storage region with a predetermined depth; and a selector suitable for selecting an output of any one storage device among the plurality of storage devices.

Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.

Abstract: Forming a logic circuit design from a behavioral description language that includes N force and M release statements applied to a net disposed in the design, includes, in part, forming N multiplexers and a controller controlling the select terminals of the N multiplexers. Each multiplexer receives a force signal at its first input terminal. The output signal of the ith multiplexer is supplied to a second input terminal of (i+1)th multiplexer. A driver signal driving the net in the absence of the force statements is applied to a second input terminal of a first multiplexer. The controller asserts the select signal of the ith multiplexer if the ith force condition is active, and unasserts the select signal of the ith multiplexer if any one of a number of predefined conditions is satisfied.

Abstract: Method and Apparatuses for transmitting and receiving commands for a semiconductor device are described. An example apparatus includes: a memory device including a plurality of banks, each bank including a plurality of memory cells; and a memory controller that transmits a first command and a plurality of address signals indicative of a memory cell in a first bank of the plurality of banks at a first time. The first command is indicative of performing a first memory operation, and a second memory operation different from the first memory operation. The memory device receives the first command and the plurality of address signals and further performs the second memory operation to the first bank responsive, at least a part, to the plurality of address signals and the first command.

Abstract: Apparatuses and methods for reducing sense amplifier leakage current during an active power-down are disclosed. An example apparatus includes a memory that includes a memory cell and a first digit line and a second digit line. The memory cell is coupled to the first digit line in response to activation of a wordline coupled the memory cell. The example apparatus further includes a sense amplifier comprising of a first transistor coupled between the first digit line and a first gut node of the sense amplifier and a second transistor coupled between the second digit line and a second gut node of the sense amplifier. While the wordline is activated, in response to entering a power-down mode, the first transistor is disabled to decouple the first digit line from the first gut node and the second transistor is disabled to decouple the second digit line from the second gut node.

Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.

Abstract: A voltage regulator includes a first feedback loop and a second feedback loop. The first feedback loop includes a charge pump outputting a first output voltage, a first transistor ladder and a control circuit. The first transistor ladder divides the first output voltage to generate a first feedback voltage. The control circuit receives the first feedback voltage and controls a level of the first output voltage according to the first feedback voltage and a reference voltage. The second feedback loop includes a power transistor, a second transistor ladder and an operational amplifier. The power transistor receives the first output voltage to output a second output voltage. The second transistor ladder divides the second output voltage to generate a second feedback voltage. The operational amplifier outputs a control signal to the power transistor by receiving the second feedback voltage and a reference voltage selected from one of a plurality of levels.

Abstract: A first rank includes a plurality of first semiconductor memory devices, and a second rank includes a plurality of second semiconductor memory devices. The command/address signal lines are shared by a controller, the first rank, and the second rank, and the data lines are shared by the controller, the first rank, and the second rank. When performing a data movement operation of moving data between the first rank and the second rank, the controller applies a shift read command to one of the first rank and the second rank through the command/address signal lines and applies a normal write command or a shift write command to another of the first rank and the second rank through the command/address signal lines after a time corresponding to a value obtained by subtracting the value of the write latency from the value of the read latency.

Abstract: Memories include a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells.

Abstract: A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a memory array of addressable memory cells and a pipeline configured to process read and write operations addressed to the memory bank. Further, the memory device comprises an x decoder circuit coupled to the memory array for decoding an x portion of a memory address for the memory array and a y multiplexer circuit coupled to the memory array and operable to simultaneously multiplex across the memory array based on two y portions of memory addresses and, based thereon with the x portion, for simultaneously writing a value and reading a value associated with two separate memory cells of the memory array, wherein the x decoder and the y multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to the memory array.

Abstract: A semiconductor device includes first input/output circuits for a first channel, first input/output pads corresponding to the first input/output circuits, respectively, wherein the first input/output pads are aligned along and extends in a first direction, second input/output circuits for the first channel, second input/output pads corresponding to the second input/output circuits, respectively, wherein the second input/output pads are aligned along and extends in a second direction, and an input circuit between the first input/output pads and the second input/output pads, and connected to a memory to which the input circuit inputs data from the first input/output circuits and the second input/output circuits. The input circuit is positioned such that a first line extending perpendicular to the first direction from one of the first input/output pads and a second line extending perpendicular to the second direction from one of the second input/output pads intersect a portion of the input circuit.

Abstract: A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.

Abstract: An example read address generation circuit for a static random access memory (SRAM) cell includes an operational amplifier having a non-inverting input coupled to a reference voltage, a memory emulation circuit having an output coupled to an inverting input of the operational amplifier and a control input coupled to an output of the operational amplifier, and a multiplexer having a first input coupled to receive a constant read voltage, a second input coupled to the output of the operational amplifier, and an output coupled to supply a read address voltage to the SRAM cell.

Abstract: Various implementations described herein are directed to an integrated circuit having multiple access wires including a first access wire coupled to a first access port of the integrated circuit and a second access wire coupled to a second access port of the integrated circuit. The integrated circuit may include inverter circuitry having a first plurality of inverters coupled to the first access wire and a second plurality of inverters coupled to the second access wire. The first plurality of inverters may be positioned adjacent to the second plurality of inverters in an alternating manner.

Abstract: Memories including a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells, as well as methods of operating similar memories.

Abstract: Methods and apparatuses have been disclosed for a high speed, low power, isolated buffer having architecture and operation that control current flow to minimize coupling and power consumption. Buffer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit and a buffer disabling circuit operated to disable the buffer when the input circuit is disabled by the selection circuit. Any one or more of these features may be implemented to improve isolation performance. The selection circuit, input disabling circuit and buffer disabling circuit may be operated by the same control signal.

Abstract: One embodiment relates to an integrated circuit with an array of modular physical layer (PHY) slice circuits that are configured into multiple synchronous groups. Each synchronous group receives a delayed synchronous pulse signal provided by a chain of synchronous delay circuits. Another embodiment relates to an array of modular PHY slice circuits, each of which includes a manager circuit that manages the modular PHY slice circuit, a remap circuit that remaps interconnect redundancy, and an input-output module that provides outbound control and data streams and receives inbound control and data streams.

Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

Abstract: A peripheral controller, and method of operation, for half duplex communication between a system and a peripheral, in which a system clock and a peripheral clock are asynchronous, are described. A FIFO includes a FIFO controller and a FIFO memory and has a plurality of inputs. A multiplexer circuit is connected to the plurality of inputs, and is operable by a selection signal to supply either a first group of system and peripheral signals or a second group of system and peripheral signals to the FIFO to operate the FIFO to transmit data from the system to the peripheral or to receive data at the system from the peripheral.

Abstract: A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of mats connected to a word line. The column decoder includes a first repair circuit in which a first repair column address is stored, and a second repair circuit in which a second repair column address is stored. When the first repair column address coincides with a column address received in a read command or a write command, the column decoder selects other bit lines instead of bit lines corresponding to the received column address in one mat from among the plurality of mats. When the second repair column address coincides with the received column address, the column decoder selects other bit lines instead of the bit lines corresponding to the received column address in the plurality of mats.

Abstract: Memory devices including an array of memory cells, a plurality of access lines selectively coupled to respective pluralities of memory cells of the array of memory cells, a plurality of first registers, a second register, a first multiplexer, a second multiplexer, and a decoder configured to selectively connect a corresponding access line to a selected voltage source of a plurality of voltage sources in response to the output of the second multiplexer, wherein the second multiplexer is configured to pass a selected one of the output of the second register and the output of the first multiplexer to its output, and wherein the first multiplexer is configured to pass a selected one of the outputs of the plurality of first registers to its output.

Abstract: A memory apparatus including a memory cell array, a register unit and a command generator is provided. The memory cell array includes a plurality of memory cells. The register unit is configured to record a plurality of user-defined information. The command generator receives a user-defined command and operates at least two memory operations on the memory cell array according to the received user-defined command and the user-defined information. The user-defined information is generated according to the at least two memory operations. Furthermore, an operating method of a memory apparatus is also provided.

Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

Abstract: Embodiments generally relate to a command protocol and/or related circuits and apparatus for communication between a memory device and a memory controller. In one embodiment, the memory controller includes an interface for transmitting commands to the memory device, wherein the memory device includes bitline multiplexers, and accessing of memory cells within the memory device is carried out by a command protocol sequence that includes a wordline selection, followed by bitline selections by the bitline multiplexers. In another embodiment, a memory device includes bitline multiplexers and further includes an interface for receiving a command protocol sequence that specifies a wordline selection followed by bitline selections by the bitline multiplexers.