Abstract: A semiconductor package with clock sharing, which is suitable for an electronic system having low power consumption characteristics, is provided. The semiconductor package includes a lower package including a lower package substrate and a memory controller mounted on the lower package substrate, an upper package stacked on the lower package and including an upper package substrate and a memory device mounted on the upper package substrate, and a plurality of vertical interconnections electrically connecting the lower package to the upper package. The semiconductor package is configured to cause the memory controller to output a first data clock signal used for a channel that is an independent data interface between the memory controller and the memory device, branch the first data clock signal, and provide the branched first data clock signal to the memory device.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for fuse latch and match circuits. A memory may include a number of fuse registers, each of which is associated with a line of redundant memory cells. An address may be stored in fuse latches of the fuse register. A dynamic logic circuit may activate one of the fuse registers and a match logic circuit may compare the address stored in the activated fuse register to an address received as part of an access operation to determine if the redundant memory cells should be accessed. The fuse latches may be floated during a power up operation. The dynamic logic circuit may control a timing of the activation and comparison operation.

Abstract: A memory system includes a memory device with a termination circuit providing a termination impedance for a data signal in the memory device. The device also includes a calibration circuit configured to set the termination impedance to a predetermined value. The device further includes an impedance adjustment circuit configured to adjust the termination impedance based on a feedback signal indicating a change in the termination impedance due to at least one of a change in a temperature of the memory device or a change in voltage of a voltage bus in the memory device.

Abstract: The provided is a method of controlling a dynamic random-access memory (DRAM) device comprising: storing a plurality of pieces of data consisting of a plurality of bits in a memory in a transposed manner; setting at least one refresh period for each of a plurality of rows constituting the memory; and performing a refresh operation of the memory on the basis of the set refresh period.

Abstract: According to an aspect of a present invention, there is provided a semiconductor device including a first power monitoring device and a second power monitoring device. The first power monitoring device outputs first operating power that is to be supplied to a second control section. The second power monitoring device outputs second operating power that is to be supplied to a first control section. Based on a first setting given from the first control section, a first power monitoring circuit autonomously verifies whether the second operating power is normal, and periodically transmits the result of verification to the second control section as first error information. Based on a second setting given from the second control section, a second power monitoring circuit autonomously verifies whether the first operating power is normal, and periodically transmits the result of verification to the first control section as second error information.

Abstract: A memory is provided with a logic gate that processes a first version and a second version of a memory clock signal to assert a clock signal for the clocking of latches in a second array of columns for the memory. The first version clocks the latches in a first array of columns for the memory. But the second version does not clock any latches in the first array of columns.

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

Abstract: Storage capacity optimization of non-volatile memory is shown. Through a controller, communication between a host and a non-volatile memory is in units of a first data length. The controller manages a bad column table for the non-volatile memory in units of a second data length. The second data length is shorter than the first data length. Taking byte communication as an example, one nibble of storage units is marked as bad when it has any damaged storage units.

Abstract: Devices and methods include distributing biases for input buffers of a memory device. The devices include multiple input buffers configured to buffer data for storage in the multiple memory banks. The devices also include biasing generation and distribution circuitry configured to generate and distribute biases to the multiple input buffers. The biasing generation and distribution circuitry includes bias voltage generation circuitry and multiple remote resistor stacks each located at a corresponding input buffer of the input buffers and remote from the bias voltage generation circuitry.

Abstract: An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level of the command signal. A gate circuit of the apparatus may provide a shift clock signal responsive, at least in part, to the clock enable signal. The apparatus may also include a shifter that captures and shifts the delay command signal responsive, at least in part, to the shift clock signal.

Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to bypass one or more memory cells in a bypass mode of operation. The various exemplary memory storage devices can adjust, for example, pull-up or pull-down, the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. In some situations, the various exemplary memory storage devices may introduce an unwanted bias into the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. The various exemplary memory storage devices can pull-down the electronic data and/or pull-up the electronic data as the electronic data is passing through these exemplary memory storage devices in the bypass mode of operation to compensate for this unwanted bias.

Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.

Abstract: Disclosed herein is an apparatus that includes a clock generator configured to generate first, second, third, and fourth clock signals different in phase from one another, and first, second, third, and fourth clock drivers each configured to drive the first, second, third, and fourth clock signals, respectively. The first and second clock drivers are arranged symmetrically with respect to a first line extending in a first direction. The first and third clock drivers a arranged symmetrically with respect to a second line extending in a second direction. The first and fourth clock drivers are arranged symmetrically with respect to a point crossing the first and second lines.

Abstract: A memory device controls a page buffer to ensure the reliability of data. The memory device includes: a memory cell array including a plurality of memory cells configured for storing data; first and second page buffers respectively including main latches and cache latches, which are coupled to a bus, the first and second page buffers being connected to the memory cell array respectively through bit lines coupled to the main latches; and control logic including a bus precharge controller for differently setting a voltage level of the bus, based on a distance between a reference position and the first page buffer and a distance between the reference position and the second page buffer, for precharging of the bus for transmitting data of a cache latch included in each of the first and second page buffers to a corresponding main latch.

Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.

Abstract: One embodiment provides a method, including: identifying, using a processor, a connection of a device to an information handling device; receiving, at the information handling device, an indication of a user selection action on the device; and performing, responsive to receiving the indication, an action on the information handling device. Other aspects are described and claimed.

Abstract: Convenience in a decoding process on a receiver side for when a predetermined number of high-quality-format image data is transmitted together with basic-format image data is achieved. A base stream including, as an access unit, encoded image data for each picture of basic-format image data, and a predetermined number of enhanced streams, each including, as an access unit, encoded image data for each picture of high-quality-format image data are generated. Here, a predictive coding process is performed on image data in high-quality format by referring to the image data in basic format or image data in another high-quality format, by which an enhanced stream is generated. Then, information indicating decoding order is added to each access unit of the enhanced streams. A container in a predetermined format that includes the base stream and the predetermined number of enhanced streams is transmitted.

Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.

Abstract: A semiconductor memory device includes a memory cell array including first memory cells and second memory cell, and a peripheral circuit. When a first command, a first address, and first input data are received, the peripheral circuit reads first data from the first memory cells based on the first address in response to the first command, performs a first operation by using the first data and the first input data, and reads second data from the second memory cells by using a result of the first operation.

Abstract: A semiconductor device includes an information signal generation circuit configured to store the register information depending on an input control signal generated based on the mode register read command, and output the stored register information depending on an output control signal generated based on the mode register read command.

Abstract: In one aspect of the present description, safe data commit scan operations of individual data storage systems of a distributed data storage system may be synchronized to reduce the occurrence of reductions in input/output (I/O) response times. In one embodiment, a set of safe data commit scan operations of the individual data storage systems of a distributed data storage system are synchronously timed to substantially overlap in time within a single synchronized safe data commit scan set interval to reduce or eliminate the occurrences of reductions in input/output response times outside the synchronized safe data commit scan set interval. Other features and aspects may be realized, depending upon the particular application.

Abstract: Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.

Abstract: The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

Abstract: A memory subsystem includes a command address bus capable to be operated at double data rate. A memory circuit includes N command signal lines that operate at a data rate of 2R to receive command information from a memory controller. The memory circuit includes 2N command signal lines that operate at a data rate of R to transfer the commands to one or more memory devices. While ratios of 1:2 are specified, similar techniques can be used to send command signals at higher data rates over fewer signal lines from a host to a logic circuit, which then transfers the command signals at lower data rates over more signal lines.

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

Abstract: An off-chip driver including a first driving circuit is provided. The first driving circuit is used to adjust a slew rate of the off-chip driver. The first driving circuit includes a first pre-driver, a switch string, and a first output stage. The first pre-driver receives a read signal and a first pre-driver control signal. The switch string is configured to perform a voltage division operation in cooperation with the first pre-driver on a power supply voltage according to the read signal, so as to generate a first output stage control signal. The first output stage generates a data signal according to the first output stage control signal.

Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.

Abstract: A memory system includes a nonvolatile memory including a word line and a plurality of memory cells connected to the word line, and a controller configured to transmit to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line.

Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices.

Abstract: Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

Abstract: Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.

Abstract: A computer-implemented method according to one embodiment includes receiving log data from a component of a network, processing the log data to create processed log data, creating a component object, utilizing the processed log data, receiving an identification of a device connected to the network, determining a path within the network that is associated with the device, utilizing the component object, and returning the path.

Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

Abstract: In one aspect of the present description, a primary-secondary role swap operation which swaps roles of primary and secondary data storage systems in a distributed data storage system, is synchronized with safe data commit scan operations of individual data storage systems. The safe data commit scan operations of the individual data storage systems are also synchronized to ensure completion of the safe data commit scans and to reduce the occurrence of reductions in input/output (I/O) response times prior to initiation of a primary-secondary role swap operation. Other features and aspects may be realized, depending upon the particular application.

Abstract: Apparatuses and methods are provided for write address tracking. An example apparatus can include an array of memory cells and a cache coupled to the array. The example apparatus can include tracking circuitry coupled to the cache. The tracking circuitry can be configured to track write addresses of data written to the cache.

Abstract: In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.

Abstract: Apparatuses for receiving an input data signal are described. An example apparatus includes: a plurality of data input circuits and an internal data strobe generator. Each data input circuit of the plurality of data input circuits includes: an amplifier that receives data from a data terminal, and latches the data in an enable state and refrains from latching data in a disable state; and a voltage control circuit coupled to a tail node of the amplifier and provides a first voltage to the tail node during the enable state, and further provides a second voltage different from the first voltage to the tail node in a first mode and to sets the tail node in a floating state in a second mode during the disable state. The internal data strobe signal generator provides a plurality of internal data strobe signals to the plurality of corresponding data input circuits respectively.

Abstract: The present invention provides a decision feedback equalizer including a first path and a second path. The first path includes a first sampling circuit and a first latch circuit, wherein the first sampling circuit generates a first set signal and a first reset signal according to an input signal, a second set signal and a second reset signal, and the first latch circuit generates a first digital signal according to the first set signal and the first reset signal. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit generates the second set signal and the second reset signal according to the input signal, the first set signal and the first reset signal, and the second latch circuit generates a second digital signal according to the second set signal and the second reset signal.

Abstract: Methods and apparatus for implementing a circuit design are provided. A physical description is generated corresponding to a predefined physical layout of a programmable integrated circuit. The circuit design includes a memory block. A timing analysis is executed to determine a first timing profile of the physical description. The physical description is optimized (or at least altered), and a physical implementation is generated based on the optimized physical description. Optimizing the physical description includes: selectively moving from or into the memory block of the physical description a register in response to an attribute of the memory block; executing a timing analysis to determine a second timing profile of the physical description with the register moved from or into the memory block of the physical description; comparing the first and second timing profiles; and selectively accepting or reversing the moving based on the comparison of the first and second timing profiles.

Abstract: Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to both drive latched data and conduct read and write operations. For example, a memory device may contain two or more memory arrays independently coupled to two drivers via two data lines. One data line may be driven strongly to shield a corresponding memory array from effects associated with data line capacitive coupling. An opposing data line may be driven with data pertaining to an access operation of the memory array to which it is coupled. The opposing data line may be driven concurrently or within a small time difference of the other data line.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for plate coupled sense amplifiers. An example embodiment may include a sense amplifier which may sense a voltage from a memory cell. The sense amplifier may also monitor a change in the voltage, and determine a logical value of the memory cell based on the time when the voltage reaches a trigger voltage. The memory cell may be coupled to a plate with a plate voltage, wherein a change in the plate voltage determines the change of the voltage from the memory cell.

Abstract: Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.

Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.

Abstract: According to an embodiment, a word line driver includes: a first inverter that is driven by a first power supply voltage and inverts and outputs a decode signal; a second inverter that is driven by a second power supply voltage and inverts and outputs the decode signal; a first PMOS transistor that is controlled to be turned on or off on the basis of an output signal of the second inverter; a first NMOS transistor that is controlled to be turned on or off on the basis of an output signal of the first inverter; and a second PMOS transistor that is provided between a power supply voltage terminal to which the second power supply voltage is supplied and the gate of the first PMOS transistor and is temporarily turned on in synchronization with falling of the decode signal.

Abstract: A memory device includes a plurality of bit lines; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein a number of stages of the page buffer circuit is less than a number of stages of the cache circuit.

Abstract: A timing calibration system is applicable to a memory read system which includes a memory, a delay unit and a data read circuit. The memory outputs a data signal and a data latch signal. The delay unit delays the data latch signal by a delay value, to generate a read signal. The data read circuit reads the data signal according to the read signal. In the timing calibration system, a logic computation unit generates first and second charging signals according to the data signal and the read signal, and a capacitor-resistor charging unit performs charging operations according to the first and second charging signals, so as to generate first and second capacitor voltages, and a comparing unit can compare the first and second capacitor voltages, to generate a comparison result, thereby adjusting the delay value of the delay unit according to the comparison result.

Abstract: A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.

Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.

Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.