Including Specified Plural Element Logic Arrangement Patents (Class 365/189.08)
  • Patent number: 10437685
    Abstract: Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 8, 2019
    Assignee: Rambus Inc.
    Inventors: Steven Woo, David A. Secker, Ravindranath Kollipara
  • Patent number: 10332586
    Abstract: Systems, apparatuses, and methods related to subrow addressing for electronic memory and/or storage are described. Independent subrow addressing may enable energy consumed by performance of an operation on a particular subset of data values stored by a row to more closely correspond to the size of the particular subset of data values relative to energy consumed by addressing and activating the complete row. For instance, one such apparatus includes a plurality of subrows within a row of memory cells and a controller configured to selectably address and manage an activation state of each subrow of the plurality of subrows. The apparatus further includes subrow driver circuitry coupled to the controller. The subrow driver circuitry is configured to maintain one or more subrows of the plurality in the activation state based at least in part on signaling from the controller.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Richard C. Murphy
  • Patent number: 10304518
    Abstract: Some embodiments include an apparatus which has a wordline coupled with a transistor gate, and which has a compensator line extending along the wordline and spaced from the wordline by a dielectric region. A driver is coupled with the wordline, and a controller is coupled with the compensator line. The wordline is coupled with access transistors, and is operated at a first voltage while the access transistors are in an OFF state. The compensator line is operated at a second voltage while the wordline is at the first voltage; with the second voltage being greater than the first voltage. The wordline is operated at a third voltage while the access transistors are in an ON state, and the compensator line is operated at a fourth voltage while the wordline is at the third voltage. The third voltage may or may not be greater than the fourth voltage.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Chandra Mouli, Haitao Liu
  • Patent number: 10217493
    Abstract: Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: February 26, 2019
    Assignee: INTEL CORPORATION
    Inventors: Wei Wu, Shigeki Tomishima, Shih-Lien L. Lu
  • Patent number: 10153038
    Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
  • Patent number: 10061378
    Abstract: A system and method is disclosed for an electronic device, such as a non-volatile memory associated with a host, to determine a current sourcing capability of the host and to adjust performance characteristics of the electronic device based on the determined current sourcing capability. The system may include an input current source testing circuit, device function circuitry and a controller configured to determine a current sourcing capability of a host with the input current source testing circuit, select a device performance parameter associated with the determined current sourcing capability and operate the device function circuitry according to the device performance parameter until detecting a power-off event. The method may include the electronic device reducing a resistance presented to the host to a plurality of predetermined resistance levels to determine the current sourcing capability of the host and utilizing the results of the determination to select associated device performance parameters.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: August 28, 2018
    Assignee: SanDisk Technologies LLC
    Inventor: Ankur Agrawal
  • Patent number: 10021450
    Abstract: Various arrangements are presented for reducing channel change times. A first tuner of a television receiver may tune to a decryption key transponder stream. The decryption key transponder stream may include a plurality of decryption keys for a plurality of television channels that are transmitted to the television receiver via a plurality of transponder streams. A second tuner of the television receiver may be tuned to a media transponder stream to receive a television channel. Data obtained from the decryption key transponder stream may be used for decoding the television channel.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: July 10, 2018
    Assignee: DISH Technologies L.L.C.
    Inventors: David Innes, William Michael Beals, David Kummer
  • Patent number: 10014035
    Abstract: A control device includes: a dummy memory cell group; a transistor having a first terminal, a grounded second terminal and a control terminal; an adjustor providing a resistance between the dummy memory cell group and the first terminal of the transistor; an inverter generating, based on a voltage at the first terminal of the transistor, a sense start signal that is associated with switching of a sense amplifier circuit of a semiconductor memory device from a disabled state to an enabled state; and a controller generating, based on the sense start signal, a control signal for controlling the transistor such that switching of the transistor from conduction into non-conduction is associated with the sense start signal.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 3, 2018
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventors: Yu-Fen Lin, Nan-Chun Lien
  • Patent number: 9947393
    Abstract: A semiconductor integrated circuit device includes a control unit which causes a column selection circuit to separate bit line pairs from a common bit line pair and causes a sense amplifier circuit to amplify a potential difference between the common bit line pair precharged by a precharge circuit, in response to a unique ID generation instruction.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Yabuuchi, Hidehiro Fujiwara
  • Patent number: 9934827
    Abstract: Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: April 3, 2018
    Assignee: INTEL CORPORATION
    Inventors: Wei Wu, Shigeki Tomishima, Shih-Lien L. Lu
  • Patent number: 9934844
    Abstract: Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Hieu T. Ngo, Daniel J. Cummings
  • Patent number: 9870810
    Abstract: A method and system for suppressing power signature in a memory device during read operations. A memory array stores data in an even number of cells per bit, such as 2 cells per bit, where complementary data states are stored in each pair of cells. Differential read out of the memory array via the bitlines suppresses power signature because the same power consumption occurs regardless of the data being accessed from the memory array. Data output buffers that provide complementary data to a downstream circuit system are reset to the same logic state prior to every read operation such that only one output buffer (in the complementary output buffer pair) is ever driven to the opposite logic state in each read cycle. Hence the power consumption remains the same regardless of the data states being read out from the memory array and provided by the output buffers.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: January 16, 2018
    Assignee: Sidense Corp.
    Inventors: Wlodek Kurjanowicz, Betina Hold
  • Patent number: 9837129
    Abstract: Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: December 5, 2017
    Assignee: CrossFire Technologies, Inc.
    Inventors: Kevin Atkinson, Clifford H. Boler
  • Patent number: 9830957
    Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip having a memory controller. The memory controller includes a memory interface circuit configured to interface the IC chip with a memory chip having a memory array, and a first control circuit. The memory chip has a configuration circuit for adjusting one or more configurations of the memory chip. The first control circuit is configured to control the memory interface circuit and to communicate with the configuration circuit in the memory chip via the memory interface circuit to adjust the one or more configurations of the memory chip.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: November 28, 2017
    Assignee: Marvell International Ltd.
    Inventors: Jun Zhu, Akanksha Mehta, Akshay Chandra, Ting Qu, Saswat Mishra
  • Patent number: 9830977
    Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: November 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Yabuuchi, Hidehiro Fujiwara
  • Patent number: 9824767
    Abstract: A disclosed example to reduce a threshold voltage drift of a selector device of a memory cell includes providing an applied voltage to the selector device of the memory cell, the applied voltage being less than a threshold voltage of the selector device, and reducing the threshold voltage drift of the memory cell by maintaining the applied voltage at the selector device for a thresholding duration to activate the selector device.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Davide Mantegazza, Feng Pan, Prashant S. Damle, Hanmant Pramod Belgal, Kiran Pangal
  • Patent number: 9824776
    Abstract: A semiconductor memory device includes: a plurality of memory blocks; a plurality of bit-line sense amplifiers shared by neighboring memory blocks among the plurality of the memory blocks, and suitable for sensing and amplifying data read from memory cells coupled to activated word lines through bit lines, and outputting the amplified data through a plurality of segment data lines; a word line driver suitable for activating word lines of memory blocks that do not share the bit-line sense amplifiers during a test mode; and a weak cell detection circuit suitable for compressing the amplified data transferred through the plurality of the segment data lines for generating compressed data and detecting a weak cell based on the compressed data during the test mode.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: November 21, 2017
    Assignee: SK Hynix Inc.
    Inventor: Youk-Hee Kim
  • Patent number: 9779784
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry can include a sense amplifier coupled to a pair of complementary sense lines and a compute component coupled to the sense amplifier via pass gates coupled to logical operation selection logic. The logical operation selection logic can be configured to control pass gates based on a selected logical operation.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: October 3, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 9740407
    Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: August 22, 2017
    Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
    Inventors: Peter B. Gillingham, Graham Allan
  • Patent number: 9496042
    Abstract: According to one embodiment, a semiconductor device includes: a first semiconductor chip including a first via and a second via; and a second semiconductor chip including a third via and a fourth via and being located above the first semiconductor chip. The first semiconductor chip includes: a first detector capable of coupling to the third via through the second and fourth vias; and a first current source configured to control an output current in accordance with a voltage of the third via detected by the first detector.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: November 15, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naofumi Abiko, Masahiro Yoshihara, Yoshihiko Kamata
  • Patent number: 9460810
    Abstract: A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip, determining a distribution of bit failure rates from the measured bit failure rates; determining a maximum allowed bit failure rate from a given chip failure rate limit, determining a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate and determining, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: October 4, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Georg Tempel
  • Patent number: 9395422
    Abstract: The present invention relates to a magnetism detection device. First and second switch units switch a direction of a current flown from a bias generating unit across two opposite terminals of four terminals of a hall sensor, and switch a direction of a voltage to be available in remaining two opposite terminals in the direction orthogonal to the direction of the current, respectively, so that in a first period, a polarity of a hall electromotive force is a first polarity and a polarity of the hall offset voltage alternates four times, and in a second period, the polarity of the hall electromotive force is a second polarity opposite to the first polarity and the polarity of the hall offset voltage alternates four times.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: July 19, 2016
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Takeo Yamamoto
  • Patent number: 9390770
    Abstract: Apparatuses and methods for accessing memory are described. An example method includes accessing memory cells of a memory section, and sharing a source of an inactive sense amplifier section with an active sense amplifier section coupled to the memory cells of the memory section during a memory access operation to the memory section coupled to the active sense amplifier section. An example apparatus includes a memory section and a first sense amplifier section associated with the memory section. The first sense amplifier section includes a sense amplifier and includes a read/write circuit coupled to a first source associated with the first sense amplifier section. The source associated with the first sense amplifier section is coupled to a source associated with a second sense amplifier section. The second sense amplifier section is configured to be inactive during a memory access operation to the memory section.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: July 12, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Harish Venkata
  • Patent number: 9360880
    Abstract: An integrated circuit includes a node setting block connected to a reference node and suitable for setting a voltage level of the reference node to a reference voltage level, a plurality of control voltage generation units connected in series to a reference node and suitable for generating a plurality of control voltages of which voltage level is variable and a current sensing circuit suitable for sensing a variation of a current flowing through a signal transmission line by using the plurality of control voltages, the signal transmission line connected to an internal circuit and a voltage level of the signal transmission line being fixed.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: June 7, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jae-Kwan Kwon
  • Patent number: 9349419
    Abstract: A control circuit, a memory device and a voltage control method thereof are provided. The memory device includes a memory cell, a voltage regulator circuit and the control circuit. The control circuit receives a clock signal, and determines a clock frequency of the clock signal so as to generate a control signal. An operation voltage is converted into an internal supply voltage for supplying the control circuit by the voltage regulator circuit according to the control signal.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 24, 2016
    Assignee: Winbond Electronics Corp.
    Inventor: Ying-Te Tu
  • Patent number: 9343139
    Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: May 17, 2016
    Assignee: Apple Inc.
    Inventors: Brian J. Campbell, Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam
  • Patent number: 9325314
    Abstract: Provided is an integrated circuit including circuits driven in different voltage domains. The integrated circuit includes a logic circuit configured to be driven by a first power supply voltage having a first power supply voltage level, and a memory circuit configured to be driven by a second power supply voltage having a second power supply voltage level different from the first power supply voltage level. The memory circuit includes a circuit configured to interface with the logic circuit, configured to be supplied with power at the second power supply voltage level in response to an output signal, and configured to shift a level of a signal having the first power supply voltage level received from the logic circuit to the second power supply voltage level. The first power supply voltage corresponds to a first voltage domain, and the second power supply voltage corresponds to a second voltage domain.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: April 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ken Keon Shin
  • Patent number: 9263110
    Abstract: A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included in a memory bank that is selected based on the bank selective signal, activates any one of the circuit areas based on the address signal, and deactivates at least one of rest of the circuit areas. According to the present invention, the power consumption can be reduced in an active state by a dynamic power control in response to an address signal, not by entire power control by an external command.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 16, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Makoto Kitayama
  • Patent number: 9164520
    Abstract: According to one embodiment, a synchronous rectification type power circuit includes a first power terminal to which a voltage on a high potential side is supplied, a second power terminal to which a voltage on a low potential side is supplied, an output terminal that outputs an output voltage to a load having an inductance and a capacitor, a first switch unit connected between the first power terminal and the output terminal, a second switch unit connected between the second power terminal and the output terminal, a control signal generating circuit which controls ON/OFF of the first and second switch units, and a control circuit that compares the output voltage with a predetermined reference voltage for a predetermined period when the second switch unit is turned OFF. A timing for turning OFF the second switch unit is adjusted based on a result of the comparison.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: October 20, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takayuki Miyazaki
  • Patent number: 9165923
    Abstract: Disclosed herein is a device that includes: a plurality of first standard cells arranged on a semiconductor substrate in a first direction, each of the first standard cells including at least one field-effect transistor; and a first power supply wiring extending in the first direction along one end of the first standard cells in a second direction. The field-effect transistor including a gate electrode formed on a gate wiring layer. The first power supply wiring being formed on the gate wiring layer.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: October 20, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Satoru Sugimoto, Takanari Shimizu
  • Patent number: 9112495
    Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 18, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, David A. Kidd, Augustine Kuo
  • Patent number: 9041430
    Abstract: An integrated circuit (IC) with a novel configurable routing fabric is provided. The configurable routing fabric has signal paths that propagate signals between user registers on user clock cycles. Each signal path includes a set of configurable storage elements and a set of configurable logic elements. Each configurable storage element in the path is reconfigurable on every sub-cycle of the user clock cycle to either store an incoming signal or to pass the incoming signal transparently.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: May 26, 2015
    Assignee: TABULA, INC.
    Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
  • Patent number: 9036447
    Abstract: A decoder circuit with reduced leakage configured to decode an address and drive one of a number of word lines may be implemented with two-high logic gates in a pre-decode stage, a decode stage, and a word line driver stage. Such decoder circuits may include, in the word line driver stage, a number of two-high NOR gates configured to drive one of a number of word lines. In some embodiments, the two-high logic gates that share common inputs are implemented with multi-output static logic.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 19, 2015
    Assignee: Oracle International Corporation
    Inventors: Robert P. Masleid, Johan Bastiaens
  • Patent number: 9025404
    Abstract: A semiconductor device with reduced leakage current and a method of manufacturing these reduced leakage current semiconductor devices are disclosed. The reduced leakage current semiconductor devices may be used for both static circuits and dynamic circuits. The reduced leakage current semiconductor devices reduce leakage current in the device when the node is not transitioning which occurs more than 95% of the time.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: May 5, 2015
    Assignee: Cold Brick Semiconductor, Inc.
    Inventor: Gajendra Prasad Signh
  • Patent number: 9025356
    Abstract: The propagation delay of a signal through multiple load devices coupled sequentially along a conductor is improved by separating a subset of the load devices that is more distant from the signal source, and coupling the more distant subset to the signal through a fly-over conductor that bypasses the subset that is nearer to the signal source. The technique is applicable to subsets of bit cells in a random access memory (SRAM) coupled to a given word line, or to word line decoder gates coupled sequentially to a strobe signal, as well as other circuits wherein load devices selectable as a group can be divided into subsets by proximity to the signal source. In an SRAM layout with multiple levels, different metal deposition layers carry the conductor legs between the load devices versus the fly-over conductor bypassing the nearer subset.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Wen Lu, Wei-Jer Hsieh, Chiting Cheng, Chung-Cheng Chou, Jonathan Tsung-Yung Chang
  • Patent number: 9019782
    Abstract: A memory macro comprises a plurality of memory cells, a plurality of first amplifying circuits, a first driver circuit, and a first level shifter. The plurality of memory cells is arranged in groups of a first direction and groups of a second direction. Each amplifying circuit is coupled to a plurality of first memory cells arranged in a first group of the first direction via a first data line. The first driver circuit is configured to drive the plurality of first amplifying circuits. The first level shifter is configured to level shift an input signal operating in a first power domain to an output signal operating in a second power domain. The output signal of the first level shifter is for use by the first driver circuit. The first driver circuit and a sense amplifier of an amplifying circuit operate in the second power domain.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: April 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Atul Katoch
  • Patent number: 9013926
    Abstract: According to one embodiment, a non-volatile semiconductor storage device includes a memory cell array, a row decoder, a potential generating circuit, first plural potential selection circuits, a second potential selection circuit, a first discharge circuit, and a second discharge circuit. The first plural potential selection circuits select one of output potentials of the potential generating circuit by receiving a first control signal and apply the selected output potential to a first signal line. The second potential selection circuit applies a potential of the first signal line to a second signal line connected to the row decoder by receiving a second control signal. The first discharge circuit is arranged in the first potential selection circuit. The second discharge circuit is arranged in the second potential selection circuit.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoya Tokiwa
  • Patent number: 9007093
    Abstract: A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a PLD that is easily capable of dynamic reconfiguration and has a short startup time is provided. A programmable logic device including a memory element, a selector, and an output portion is provided. The memory element includes a transistor in which a channel is formed in an oxide semiconductor film, and a storage capacitor and an inverter which are connected to one of a source and a drain of the transistor. The inverter is connected to the selector. The selector is connected to the output portion.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda
  • Patent number: 9007850
    Abstract: A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating node, the dynamic latch comprising a storage capacitor, a write transistor configured to write the data of the floating node to the storage capacitor, and a read transistor configured to read the data of the storage capacitor, and the write transistor and the read transistor sharing the floating node.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hyun Joo, Il-Han Park, Ki-Hwan Song
  • Patent number: 8995174
    Abstract: A semiconductor device includes NAND gates and switches to form a circuit to hold data, and a capacitor electrically connected to the circuit via a transistor to store the data held in the circuit. The transistor has a channel formation region including an oxide semiconductor.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 8988929
    Abstract: A method is for driving a nonvolatile memory device, where the nonvolatile memory device includes a memory cell array composed of resistance memory cells. The method includes electrically connecting a clamping circuit, a line resistor and a selected one of the resistance memory cells in series between a sensing node and a ground. The method further includes adjusting at least one of a clamping voltage of the clamping circuit and a resistance of the line resistor according to a relative location of the selected one of the resistance memory cells within the memory cell array, and applying a read current to the sense node and sensing a voltage of the sense node to read a data stored in the selected one of the resistance memory cells.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Kook Park, Young-Don Choi
  • Patent number: 8982646
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data bus, a transfer controller, column blocks, and a column selector. The data bus is divided into stages. The transfer controller serially transfers data such that the data are respectively allocated to the stages. The column blocks temporarily stores the data. The column selector selects a column block for each of the stages from the column blocks, and transfers the data parallel between the stages and the column blocks selected for the stages. The data bus extends from one end to the other in a direction in which the column blocks are arranged, and returns from the other end to the one end.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Ito
  • Patent number: 8971139
    Abstract: A semiconductor device comprises transmission lines, inverting circuits, first, second and third switches, global sense amplifiers, and a control circuit. The first switch switches between the transmission line and the input of the inverting circuit, the second switch switches between the transmission line and the output of the transmission line, and the third switch switches between the adjacent transmission lines. The control circuit turns off the first and second switches so that the transmission lines are brought into a floating state in a state where signals of the transmission lines are held in the inverting circuits by the global sense amplifiers. After charge sharing of the transmission lines occurs by turning on the third switches within a predetermined period, the control circuit turns off the second switches so that the transmission lines are inverted and driven via the inverting circuits and the second switches.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: March 3, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 8958255
    Abstract: A semiconductor storage apparatus according to the present invention includes a plurality of memory cells, a plurality of word lines, a plurality of pairs of bit lines, a plurality of sense amplifiers, a pair of common data lines, a data-to-be-written output circuit configured to, in writing data, set voltages of the common data lines forming the pair, a column selection signal output unit configured to output a plurality of column selection signals, and a plurality of column selection gates, in which in writing the data, the column selection signal output unit selectively turns on one of the column selection gates by setting each of voltages of the column selection signals to one of a level of a higher-potential power supply voltage and a level of a lower-potential power supply voltage, before activating the sense amplifiers.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: February 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Takahashi, Masahiro Yoshida
  • Patent number: 8958232
    Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: February 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chung-Cheng Chou, Hung-Jen Liao, Bin-Hau Lo
  • Patent number: 8947949
    Abstract: A circuit includes a memory cell having a ground reference node, a switch coupled to the ground reference node, and a mode changing circuit having an output coupled to the switch. The mode changing circuit is configured to change a logic state of the output between a first output logic state and a second output logic state in response to a change in an operational voltage and/or temperature, thereby set the memory cell in a first mode in which the ground reference node is at first reference level or in a second mode in which the ground reference node is at a second reference level different from the first reference level.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bing Wang, Kuoyuan (Peter) Hsu
  • Patent number: 8942050
    Abstract: A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: January 27, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hiroshi Tomotani, Kazuhiko Shimakawa, Ryotaro Azuma, Yoshikazu Katoh, Yuichiro Ikeda
  • Patent number: 8929157
    Abstract: Circuitry to provide a supply voltage. A voltage regulator is coupled to receive a target reference signal. The voltage regulator generates a supply voltage (Vtt) and is coupled to receive the supply voltage as an input signal. An upper limit comparator receives an upper limit voltage signal that is higher than the target reference voltage signal and the supply voltage to generate a “too high” signal when the supply voltage exceeds an upper threshold. A lower limit comparator receives a lower limit voltage signal that is lower than the target reference voltage signal and the supply voltage to generate a “too low” signal when the supply voltage is below a lower threshold. A pull up current source is coupled to pull the supply voltage up in response to the too low signal. A pull down current source is coupled to pull the supply voltage down in response to the too high signal.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: January 6, 2015
    Assignee: Intel Corporation
    Inventors: Christopher P. Mozak, Navindra Navaratnam, Mahmoud Elassal
  • Patent number: 8923076
    Abstract: A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit. The input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch. An output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit. An input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor. The other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: RE46916
    Abstract: A system and method are provided for managing mobile user access to enterprise network resources from a wireless mobile device, such as a smart phone or mobile computer, with improved security and access control. Access rules determining accessible resources and associated permitted operations are determined based on membership of an authenticated user to each of one or more groups, each group being associated with a set of permitted accessible resources and operations. For each user, based on membership of a group, or a Boolean evaluation of memberships of two or more groups, a list of accessible resources and permitted operations is generated, and the list is made available for subsequent processes, e.g. presentation to the user on an interface of the mobile device. Access rules may also be defined dependent on other information received from the system, or from the mobile device, such as time or location.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: June 26, 2018
    Inventor: Thomas William Hickie