Abstract: This invention discloses a write-sensing circuit for a semiconductor memory having at least one memory block with a continuous word-line being coupled to all the memory cells in a column of the memory block and a continuous bit-line being coupled to all the memory cells in a row of the memory block, the write-sensing circuit comprising a first and a second sense amplifier belonging to the same memory block, a first switching device coupled between the first sense amplifier and a first power supply, the first switching device being controlled by a first signal, and a second switching device coupled between the second sense amplifier and the first power supply, the second switching device being controlled by a second signal different from the first signal, wherein when the first sense amplifier is activated, the second sense amplifier can remain de-activated.

Abstract: A method and signal timing adjustment circuit for implementing variation tolerant memory array signal timing, and a design structure on which the subject circuit resides are provided. A logic circuit generates a first delay signal based upon logic devices forming the logic circuit. A memory cell circuit receives the first delay signal and generates control signals responsive to the first delay signal and based upon memory cell devices forming the memory cell circuit. A programmable logic delay circuit receives the control signals and generates a timing adjustment signal.

Abstract: A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory array. The dedicated read output paths bypass the width decoding logic and provide data from the memory array directly to a data bus, thereby providing improved memory performance when width decoding is not needed. The memory unit can be incorporated in programmable devices and a programmable device configuration can select either the read bypass paths or the width decoding logic. Hardware applications that require width decoding and improved memory access speed can utilize additional programmable device resources outside the memory unit to register the full width data from the memory unit and convert it to a different data width.

Abstract: An output driver of a semiconductor memory apparatus comprises a voltage dividing block configured to generate divide voltages by dividing an internal voltage, a threshold voltage detecting block configured to generate a detecting voltage corresponding to a change in a threshold voltage of a transistor, a drive capability control signal generating block 300 configured to generate a compare signal by comparing the levels of the detecting voltage with the divide voltage and generate a control signal in response to an input signal when the compare signal is enabled, and a drive capability controlling block comprising a driver configured to perform a driving operation in response to the input signal, and a control driver configured to perform a driving operation in response to the control signal.

Abstract: A non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.

Abstract: Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power.

Abstract: A circuit and method for testing address uniqueness of a memory array are disclosed. The circuit includes a plurality of current sinks associated with rows and columns of the memory array. A plurality of word lines of the memory array are coupled to the plurality of current sinks. A current mirror circuit is coupled to the plurality of current sinks and a circuit output node is coupled to the current mirror circuit. The circuit output node is configured to compare a total current from tested word lines of the memory array with a predetermined reference current, and to output a test pass or test fail indication in response to the comparison.

Abstract: A method for testing a memory includes the following steps. First, data is read from the memory and stored to a first temporary memory. Meanwhile, expected data corresponding to the data from the memory is written into a second temporary memory from a tester. Thereafter, the data in the first temporary memory and the expected data in the second temporary memory are compared with each other to judge whether the memory has an enough operation window.

Abstract: A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, and a Y-switch circuit that is arranged for each of the bit line pairs and is configured to select each of the bit line pairs. The semiconductor memory device further includes a mode switching unit that switches the normal mode and the test mode in accordance with a mode selection signal that is externally supplied, a plurality of individual control units that control operation of each of the precharge circuits in accordance with operation of each of the Y-switch circuits in the normal mode, and a block control unit that collectively turns off all of the precharge circuits in the test mode.

Abstract: The present invention relates to a magnetic memory cell, which controls the magnetization direction of the free magnetic layer of a Magnetic Tunnel Junction (MTJ) device using a spin torque transfer, and enables the implementation of a magnetic logic circuit, in which memory and logic circuit functions are integrated. The magnetic memory cell includes an MTJ device (10) including a top electrode (11) and a bottom electrode (13), which are provided to allow current to flow therethrough, and a fixed layer (15) and a free layer (17), which are magnetic layers respectively deposited on a top and a bottom of an insulating layer (19), required to insulate the top and bottom electrodes from each other. A current control circuit (50) controls a flow of current flowing between the top and bottom electrodes, and changes a magnetization direction of the free layer according to an input logic level.

Abstract: A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

Abstract: A semiconductor memory device includes a first memory block, a second memory block, and a signal controller. The first memory block is configured to generate a first blocking signal, a second blocking signal, and a first enable signal in response to a row address, and to block and enable wordlines of the memory block in response to the first blocking signal and the first enable signal, respectively. The second memory block is configured to generate a third blocking signal, a fourth blocking signal, and a second enable signal in response to the row address, and to block and enable wordlines of the second memory block in response to the third blocking signal and the second enable signal, respectively. The signal controller is connected between the first memory block and the second memory block and is configured to enable the third blocking signal when the second blocking signal is enabled, and to enable the first blocking signal when the fourth blocking signal is enabled.

Abstract: A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.

Abstract: A data line layout structure comprises a plurality of first data lines, second data lines, a third data line, a first data line driver, and a second data line driver. The plurality of first data lines are connected to sub mats in a memory mat so that a predetermined number of first data lines are connected to each sub mat. The second data lines are disposed in a smaller quantity than the number of the first data lines so as to form a hierarchy with respect to the first data lines. The third data line is disposed to form a hierarchy with respect to the second data lines, and transfers data provided through the second data lines to a data latch. The first data line driver is connected between the first data lines and the second data lines, and performs a logical ORing operation for output of the first data lines so as to drive a corresponding second data line.

Abstract: An interface between memories having different write times is described. The interface includes a latch for capturing address and data information during a memory access by a processor of a first memory device. The interface also includes an index counter for providing frame management. The interface also includes a variable identity array logic for determining what data is to be written into a second memory device and address generation logic to determine where the data is to be stored in the second memory device. Additionally, the interface includes data validity logic to ensure that the data being written into the second memory device is valid. As a result, the processor can operate in substantially real time and can restore itself after detecting an event upset using the data stored in the second memory device.

Abstract: A first input buffer receives sequentially inputted first data. A first data selector selectively transfers the first data from the first input buffer in accordance with a data input mode. A first data alignment circuit aligns and outputs the data from the first data selector. A second input buffer receives sequentially inputted second data in accordance with the data input mode. A second data selector selectively transfers the data of the first input buffer or of the second input buffer, in accordance with the data input mode. A first data alignment circuit aligns and outputs the data from the second data selector.

Abstract: A semiconductor device includes plural memory cell blocks, each having a memory array of plural memory cells. Plural control circuits are provided in correspondence with each of the memory cell blocks, for writing information to the memory cell blocks and for reading information written in the memory cell blocks. Plural input/output terminals are for inputting the information to be written and for outputting the information to be read. Plural multiplexers are provided in correspondence with each of the input/output terminals, for conveying the information to be written from the input/output terminals and for conveying the information to be read to the input/.output terminals. A bidirectional transfer type buffer is connected to each connection line between the control circuits and the multiplexers, for selectively conveying information from the control circuits to each of the multiplexers and for selectively conveying information from the multiplexers to each of the control circuits.

Abstract: The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using input/output (I/O) circuitry, and outputting the status through the I/O circuitry.

Abstract: According to the present invention, an intra-macro match determining circuit 111 internally determines whether or not n test outputs from each macro all have the same level. The result of the determination is combined with some of the test outputs, and the resultant signal is output to a tester. Thus, the determination result for a match is combined with the test outputs instead of a particular value. Consequently, the same expected value can also be used for individual macro testing, and output bits are assigned to each of the macros. Therefore, in internally performing a comparison with the expected value, the tester can easily detect defective macros.

Abstract: A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair of bit lines to a pair of data lines. The write driver is coupled to the pair of data lines. The voltage detector provides an initiate boost signal when a voltage of a first data line of the pair of data lines drops below a first level during the writing of the pair of data lines by the write driver. The bootstrap circuit reduces the voltage of the first data line in response to the boost enable signal. This is particularly beneficial when the number of memory cells on a bit line can vary significantly as in a compiler.

Abstract: Disclosed is an accumulation memory circuit for providing a fast read, modify, and write operation in a single clock cycle time. The memory circuit is configured to read data stored in the memory device at an address. The memory circuit includes a reconfigurable adder unit generating read, accumulate and write output in a single clock cycle. The memory circuit is further configured to minimize data overflow. A high speed accumulation method comprises resetting a memory circuit; reading from an address of the memory circuit; performing internal addition within the memory circuit and rewriting into the address of the memory circuit in a single clock cycle.

Abstract: A semiconductor memory device is capable of measuring internal voltages via a shared pad to reduce a chip size. The semiconductor memory device includes a selector and a monitoring pad. The selector is configured to select one of a plurality of internal signals in response to a test signal and output the selected internal signal. The monitoring pad is configured to output an output signal of the selector to an outside of the semiconductor memory device.

Abstract: Dividing memory used for storing histogram data into multiple banks is disclosed to allow for phased RMW cycles. Although the same address lines are provided to each bank, address control logic ensures that each successive RMW cycle is handled by a different bank, so that another RMW cycle can be started in one bank while the previous RMW cycle is still being performed in another bank. By staggering or phasing the starts of the RMW cycles in a wraparound fashion, each histogram bin is spread out over multiple banks, but testing can proceed faster than if only a single bank was used. After the histogram data has been captured, the areas of memory in each bank associated with a particular bin can be added together to compute the total count for that bin.

Abstract: A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write data conversion circuit generates write data from bit data input from the same data input/output terminal in a set of a plurality of data of j bits input at different timings.

Abstract: A semiconductor device receives a first data mask signal and a second data mask signal. A data mask control unit outputs a data mask control signal by combining a test mode signal with the first data mask signal. A data clock output unit receives a delay locked loop (DLL) clock and outputs a data clock in response to the data mask control signal. A column address enable (YAE) control signal generating unit generates a column address enable control signal to control the enablement of a column address enable signal. The column address enable control signal generating unit generates the column address enable control signal by combining the test mode signal with the second data mask signal.

Abstract: An intergrated circuit having a drive circuit is disclosed. One embodiment provides an intergrated memory circuit arrangement with a drive circuit for an EEPROM. In one embodiment, the drive circuit contains tunnel field effect transistors and can be produced in particular on a small chip area.

Abstract: A semiconductor memory device includes a plurality of word lines, a plurality of pairs of bit lines and complementary bit lines that cross the word lines, and a plurality of memory cells, each memory cell being disposed at a region where a respective word line and a pair of a bit line and a complementary bit line cross each other. A voltage control unit includes a plurality of elements connected in series between a power voltage source and the memory cells and are switched on/off in response to a control signal that controls an operation of the plurality of memory cells. The voltage control unit controls the voltage of the power voltage source to a predetermined level, thereby obtaining a controlled voltage to be supplied to the memory cells.

Abstract: A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.

Abstract: A voltage regulation circuit in a nonvolatile memory card accepts an input voltage from a host at two or more different voltage levels and provides an output voltage at a single level to components including a memory die. The voltage regulation circuit can provide an output voltage that is higher or lower than the input voltage.

Abstract: A design structure embodied in a machine readable medium to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The design structure includes a write circuit for an SRAM cell or an SRAM array. The write circuit includes a gate to switch the write circuit on and off. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage.

Abstract: A hybrid circuit for a memory includes: a skewed static logic gate circuit; a dynamic pre-discharge device coupled with the skewed static logic gate circuit for operating the static logic gate circuit as a dynamic circuit.

Abstract: A memory device includes a refresh generator and a refresh command generation circuit. The refresh generator generates a refresh signal for a refresh operation enable. The refresh command generation circuit logically combines the refresh signal and a reset signal to produce a refresh command. The refresh command generation circuit produces the refresh command only when either the refresh signal or the reset signal is enabled.

Abstract: A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and a LSB verification circuit. The MSB latch is configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, and output an inverted upper sensing data, or store an input data and output an inverted input data. The LSB latch is configured to sense a voltage of the sensing node in response to the control signal, and store and output a lower sensing data, or store and output an input data received through the MSB latch. The data I/O circuit is connected to the MSB latch and a data I/O line, and is configured to perform the input and output of a sensing data or the input and output of a program data.

Abstract: A microprocessor includes re-writeable non-volatile state (RNS) addressable by an instruction executed by the microprocessor that instructs the microprocessor to write a new value to the RNS. A plurality of fuses are each readable to determine whether the fuse is blown or unblown, in response to the microprocessor decoding the instruction. A Boolean logic unit performs Boolean operations on the values read from the plurality of fuses to determine a current RNS value. A fuse blowing device blows at least one unblown fuse to change the current RNS value to the new value when the new value is different than the current value. The microprocessor can read the plurality of fuses, perform the Boolean operations, and blow at least one unblown fuse to change the current value of the RNS to a new value multiple times in response to a program running on the microprocessor executing the instruction multiple times.

Abstract: A tree-style AND-type match circuit device applied to the content addressable memory (CAM) is provided. In this tree-style AND-type match circuit device, a plurality of AND-type match circuit groups branchingly connect with each other by a first AND logic gate. The tree-style AND-type match circuit increases the parallelism of the evaluation of the entire match circuit so that it can efficiently reduce the searching period and the switching activity. Thus, the switching caused by the transformation activity is also shortened. As a result, the match circuit device will not increase the loading of the clock signal so the power consumption is reduced significantly.

Abstract: A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data and command signals, and has an output. A command circuit receives the output of the input buffer and stores the command signals therefrom. An address circuit receives the output of the input buffer and stores the address signals therefrom. A data buffer circuit receives the output of the input buffer and stores the data signals therefrom. An array of non-volatile memory cells stores data from and provides data to the data buffer in response to address signals from the address decoder. A state machine is connected to the command circuit and controls the array of non-volatile memory cells.

Abstract: A circuit measures current passing through a memory cell in a NAND flash memory. The circuit includes a decoder and an analog mixer. The decoder is configured to select at least one data line coupled to page buffers and column decoders in accordance with a controlling signal. The analog mixer is configured to output current passing through the selected data line, or to couple all of the data lines to a means for measuring current in accordance with a total current measurement controlling signal.

Abstract: A voltage regulation circuit in a nonvolatile memory card accepts an input voltage from a host at two or more different voltage levels and provides an output voltage at a single level to components including a memory die. The voltage regulation circuit can provide an output voltage that is higher or lower than the input voltage.

Abstract: Methods for inputting a data-value pattern into a nanowire crossbar, for inputting a data-value pattern into a nanowire crossbar that support computer instructions stored in a computer-readable medium, and for distributing a received data value to each of a set of nanowires that support control logic implemented in logic circuits are provided. First and second nanoscale shift registers are employed, the first having output signal lines that form or interconnect with a first parallel set of nanowire-crossbar nanowires and the second having output signal lines that form or interconnect with a second parallel set of nanowire-crossbar nanowires. A first pattern of values is stored in the first shift register and a second pattern of values is stored in the second shift register using voltage signals below the WRITE voltage for junctions of the crossbar. Voltage signals greater than or equal to the WRITE threshold are applied for junctions of the crossbar to write the pattern of data values into the crossbar.

Abstract: A novel methodology for the construction and operation of logical circuits and gates that makes use of and contact to a fourth (4th) terminal (substrates/bodies) of MOSFET devices is implemented by the present invention to realize a novel decode personalization. The novel construction and operation of the decode personalization provides for maintaining body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a transistor moves inversely to its body potential, the body of each device is tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate, decode personalization and logical family operation.

Abstract: A memory device includes a delay circuit and a delay selection unit. The delay circuit delays a pulse signal to generate a delayed pulse signal. The pulse signal is used to generate a write enable signal and a read enable signal. The delay selection unit selects one of the delayed pulse signal output from the delay circuit in a test mode and the pulse signal in a normal mode.

Abstract: A memory cell array has a plurality of memory cells arrayed in row and column directions. A plurality of sense amplifier units includes a plurality of sense amplifiers detecting write completion of each of the memory cells selected for each row. A plurality of detection units is arranged correspondingly to the sense amplifier units, and forms a transfer path for transferring potential in accordance with a detection output signal of each sense amplifier unit. The detection units detect a sense amplifier unit corresponding to a portion where the transfer path breaks off, as a sense amplifier unit including write incompletion bit.

Abstract: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory.

Abstract: An internal voltage generator stably supplies an internal voltage in a semiconductor device. The internal voltage generator includes: a first internal voltage generating means for supplying a first internal voltage which has a level corresponding to a first reference voltage using an external voltage; a second internal voltage generating means for supplying a second internal voltage which has a level corresponding to a second reference voltage using the external voltage; and a third internal voltage generating means for supplying a third internal voltage which has a level corresponding to a third reference voltage generated based on the first internal voltage, using the second internal voltage as a power source.

Abstract: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.

Abstract: A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues.

Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.

Abstract: A semiconductor device includes a first sense amplifier coupled to an input for generating a first output; a second sense amplifier couple to the input for generating a second output; and a third sense amplifier coupled to the input for generating a third output, wherein a fourth output amplifying the input is generated based on combinations of logic states of the first, second and third outputs.

Abstract: A test circuit is connected to a memory core integrated unit of SRAM. When the memory core integrated unit is to be tested, a test start signal is set to a high level so that one of a bit line and an inverted bit line is used for data write and the test circuit sets data to this selected bit line. The other bit line is used for data read, and the written data is set to this bit line in the normal operation. Whether each memory core is not defective is judged by EOR which confirms data set to the bit line and data set to the inverted bit line are mutually inverted each other. A test method is realized which can test a defect of each memory core of a semiconductor memory such as SRAM in a short time.

Abstract: A dual function serial and parallel data register with integrated program verify functionality. The master and slave latching circuits of the dual function data register can concurrently store two different words of data. In a program verify operation, the master latch stores program data and the slave latch will receive and store read data. Comparison logic in each register stage will compare the data of both latches, and integrate the comparison result to that of the previous register stage. The final single bit result will indicate the presence of at least one bit that has not been programmed. Automatic program inhibit logic in each stage will prevent successfully programmed bits from being re-programmed in each subsequent reprogram cycle. Either data word can be serially clocked out by selectively starting the shift operations on either the low or high active logic level of a clock signal.