Abstract: A non-volatile memory device includes a memory cell array including memory cells, each memory cell being defined at an intersection of a word line and a bit line. A page buffer is coupled to the memory cell array via a sensing line. The page buffer comprises a first latch unit including a first latch circuit and coupled to the sensing line, the first latch unit being configured to be activated during a copy-back program operation to read data stored in a first memory cell and reprogram the data to a second memory cell that is different from the first memory cell.

Abstract: The present invention provides a semiconductor memory device for reducing a power consumption and securing an enough valid data window. A semiconductor memory device includes an align control signal generation unit for generating a plurality of align control signals sequentially activated by dividing a data strobe signal only when a data input/output is performed; and a data align unit for outputting a plurality of data which are sequentially inputted as a plurality of align data at the same time in response to the plurality of align control signals.

Abstract: A receiver multi-protocol interface includes a wide bandwidth amplifier, a data sampling module, and a clocking module. The wide bandwidth amplifier amplifies a first formatted input signal or a second formatted input signal to produce an amplified input signal. The data sampling module converts the amplified input signal into a first data stream in accordance with at least one first sampling clock signal when the interface is configured in the first mode and to converts the amplified input signal into a second data stream in accordance with at least a second sampling clock signal when the interface is in a second mode. The clocking module generates the first sampling clock signals from a reference clock when the multi-protocol interface is in a first operational mode and generates the second sampling clock signals based on the reference clock when the interface is in the second operational mode.

Abstract: A memory circuit includes a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of column sense logic units are also provided, corresponding to the bit line structures. Each of the column sense logic units includes a first logic gate and a second logic gate. The first logic gate has a first input connected with a first one of the bit lines and a second input connected with a second one of the bit lines. The second logic gate has a first input interconnected with a third one of the bit lines, and a second input interconnected with the second one of the bit lines.

Abstract: Disclosed is an input data distribution device for a memory device, the input data distribution device comprising: a decoding section for receiving a starting column address applied when a write command is activated; and N number of switching sections each of which receives N bits of data applied sequentially through one data pin after the write command is activated, wherein each of the switching sections exclusively outputs one bit from among the N bits of data by using an output signal of the decoding section and a signal for determining a burst type.

Abstract: An inexpensive, re-configurable storage circuit for programmable logic devices and application specific integrated circuits is disclosed. The storage circuit comprises: at least one output; and at least two inputs; and at least a one input and a two input response sequence, wherein the inputs change the output in a well defined response sequence; and a configuration circuit comprising one or more memory elements, wherein the memory bits are programmed to select one of said response sequences.

Abstract: An internal voltage generator for generating a back bias voltage includes a back bias voltage pumping block for comparing a reference voltage with a feedback back bias voltage to generate a back bias enable signal and the back bias voltage in response to an activated self refresh signal and a back bias voltage discharge controlling unit for discharging the back bias voltage into a ground voltage in response to the activated self refresh signal and the back bias enable signal.

Abstract: There is provided a semiconductor storage device capable of executing a high-speed read operation without increasing a chip area thereof. The semiconductor storage device includes per-bit sensing circuits 103 each connected to a pair of bit lines (BLT, BLN) and a data output circuit 104 connected to the bit lines BLT from the per-bit sensing circuits, for outputting read data. Each of the per-bit sensing circuits 103 includes a pre-charge circuit for setting the bit line pair to a supply voltage VDD when a bit line pair selection signal YS is inactive, a latch circuit for setting the bit line pair to complementary levels (VDD and GND) according to a read signal when the bit line pair selection signal YS and a sensing circuit activation signal SE are active, and a data write circuit connected to a pair of write data lines (WDT, WDN), for setting one of the bit line pair to a second level (GND) according to write data when the bit line pair selection signal is active.

Abstract: An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage and a level of a reference voltage to thereby output a first active driving signal, a first active driver for providing the internal voltage in response to the first active driving signal, a driving time controller for generating a time driving signal activated for a predetermined time, an active driving controller for activating a second active driving signal while the time driving signal is activated and for outputting the first active driving signal as the second active driving signal while the time driving signal is inactivated, and a second active driver for providing the internal voltage in response to the second active driving signal.

Abstract: Dual port memory blocks that have a reduced layout area are provided. The write drivers and sense amplifiers are shared between the dual ports to reduce the number of write drivers and sense amplifiers to save layout area. The write drivers for the two ports are used to write into all of the first port's bitlines. The sense amplifiers for the two ports are used to read from all of the second port's bitlines. A memory block can to support true dual port (TDP) and simple dual port (SDP) operation using substantially less write drivers and sense amplifiers.

Abstract: Precise estimation of latency is attained based on identifying that a receive clock is configured to operate only at prescribed available frequencies. A receive buffer circuit includes buffer control logic configured for reading a selected number of the buffer entries based on a detected number of receive clock edges within one local clock cycle. Valid data is identified based on the number of clock edges exceeding a selected threshold. A selected pointer offset is obtained from a lookahead table, specifying multiple pointer offsets for accommodating latency encountered at respective prescribed available frequencies, based on matching the determined frequency to one of the prescribed available frequencies. The selected pointer offset is added to a read pointer to offset the latency encountered from edge detection.

Abstract: A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mode in which the signal lines are not precharged.

Abstract: In a SRAM structure, space and power saving is achieved by providing row and column select lines to select a specific bit cell, and reducing the number of bit lines in the structure used for writing to and reading from the bit cells. The number of bit lines is reduced by sharing bit lines of adjacent bit cells. Furthermore, in order to achieve power saving, the load on the row select lines is reduced by sharing the pass gates between adjacent bit cells that are used to control precharging, reading from and writing to the bit cells.

Abstract: A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data signals to generate corresponding timed read data signals. These timed data signals and termination signals from the timing circuit are applied to pull-up and pull-down circuitry, which drive respective pull-up and pull-down transistors coupled to the data bus terminals. The transistors drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected. Additionally, the pull-up and pull-down transistors bias the data bus terminals to respective voltages corresponding to the selected operating mode.

Abstract: A semiconductor device includes a memory cell array and first and second replica bit lines. A plurality of memory cells are arranged in an array form on the memory cell array. The first replica bit line is configured by wirings having the same wiring width and wiring intervals as bit lines configuring the memory cell array and is operated to generate a read timing signal. The second replica bit line is configured by wirings having the same wiring width and wiring intervals as the bit lines configuring the memory cell array and is operated to generate a write timing signal.

Abstract: A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or gate the wordline signal until an enable signal has arrived at the logic circuit. The access device improves stability and eliminates early read problems.

Abstract: A multiple-clock controlled logic signal generating circuit is proposed, which is designed for use to generate a logic signal during specified periods with reference to multiple clock signals; and which is characterized by the use of a set of switching modules to switch between two different input signals and two different clock signals and the use of an S-R flip-flop unit to output either the first input signal or the second input signal during different specified periods. This feature allows the architecture of the proposed multiple-clock controlled logic signal generating circuit to be more simplified than prior art and thus easier to implement.

Abstract: A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a logic block for decoding a plurality of chip select signals. A first high density memory module is also provided that includes the modified memory devices and a serial presence detect device. The first high density memory module is included within an electronic system. Also, an additional method of forming a stacked memory module is provided, the method requiring modification of an address buffer to include a logic block for decoding a plurality of chip select signals. A second high density memory module is also provided that includes the modified address buffer and a serial presence detect device. The second high density memory module is included within an electronic system.

Abstract: A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state output bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state output bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals. The memory produces an output signal dependent upon the enable signal generation logic output, and thus upon a logic level of the tri-state output bit line.

Abstract: A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory cells. A row decoder selects the word lines in response to a row address. Further, the row address decoder selects the redundant word line when a replacement signal is received. A column decoder selects the bit lines in response to a column address. A row address redundancy circuit stores a redundant row address. The row address redundancy circuit provides the replacement signal when the redundant row address corresponds to the received address. The mode setting circuit receives a mode signal having a normal mode and a test mode. The mode setting circuit outputs the replacement signal to the row decoder when the mode signal is in the normal mode, and prohibits an output of the replacement signal.

Abstract: A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

Abstract: A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a second MOS transistor PS1 for charging a sub-bit line SBL1—1. The source electrode of the second MOS transistor PS1 is connected to a power source voltage, and the source electrode of the first MOS transistor PD1 is connected via a fourth MOS transistor PD2 to the power source voltage. Since there is not a resistance between the main bit line MBL1 and the sub-bit line SBL1—1, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.

Abstract: A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.

Abstract: A circuit for generating a write data mask signal in a synchronous semiconductor memory device includes an output unit and a reset control unit. The output unit controls a write data mask operation of the synchronous semiconductor memory device, latches a write data mask signal, and outputs an internal write data mask signal, in response to an internal clock signal. The reset control unit generates a reset signal for resetting the internal write data mask signal, in response to a write column disable signal indicating an activation end point of a column selection line signal generated when a write operation including the write data mask operation is performed. While the synchronous semiconductor memory device performs a gapless write data mask operation included in a gapless write operation, the reset signal is deactivated so that the write data mask signal is not reset.

Abstract: Techniques for reducing power when reading a full-swing memory array are disclosed. The full-swing memory array includes a plurality of local bit lines and a global bit line. In order to reduce power consumption, a method of driving the global bit line includes the step of coupling the plurality of local bit lines to the global bit line through a plurality of tri-state devices. The method further includes the steps of generating a global select signal to enable one of the plurality of tri-state devices and selecting a corresponding local bit line to drive the output of the enabled tri-state device. In this way, the global bit line is statically driven so that consecutive reads of bits having the same value read over the global bit line do not result in transitioning the state of the global bit line.

Abstract: In a semiconductor device particularly including a phase change material, the reliability of the read-out operation is improved. In a read-out operation of a phase change memory, a bit line to be read out is precharged in advance with a sufficiently low voltage that can prevent the destructive read operation. In this state, after a word line is activated and a period in which the voltage is sufficiently discharged via a storage element which is in a low resistance state elapses (first read out), charge sharing is performed between the bit line and a read bit line of a sense amplifier which is precharged to a high voltage, and a read-out operation is performed again (second read out). Consequently, the read-out signal amount can be increased while suppressing the read current.

Abstract: A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, but is not within a throat region between two arrays. The location of the row logic allows the throat region to include more bidirectional IO circuitry and signal lines servicing two arrays, which increases the performance of the SDRAM. In addition, separate power bussing is employed for the memory arrays and IO circuitry. This prevents noise from the arrays from affecting the IO circuitry and signal lines of the throat region and vice versa.

Abstract: A nonvolatile semiconductor memory device includes write/verify circuits, a switching elements which divides the bit lines into plural portions, and a control circuit. The control circuit is configured to control the write/verify circuits and switching elements. The control circuit performs a control operation to perform the write and verify operations with the switching elements set in an OFF state when a memory cell of an address to be written lies on the write/verify circuit side in the memory cell array, write and save data into a memory cell lying on the write/verify circuit side with the switching elements set in the OFF state when the memory cell lies farther apart from the write/verify circuit than the switching elements, and then turn ON the switching elements while the write/verify circuit is not being operated and write the saved data into a memory cell of an address to be written.

Abstract: A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals such that the first and second enable signals are not in an active state simultaneously.

Abstract: An integrated circuit memory device may include a memory cell array, a plurality of data input/output pins, and a plurality of input/output circuits coupled to respective data input/output pins. The input/output circuits may be configured to accept respective data bits being written to the memory cell array from the respective data input/output pins during a write operation, and the input/output circuits may be configured to provide respective data bits being read from the memory cell array to the respective data input/output pins during a read operation. In addition, the input/output circuits may be configured to modify operational characteristics thereof responsive to respective control bits received through the respective data input/output pins during a mode set operation. Related methods and systems are also discussed.

Abstract: A multi-time programmable semiconductor memory device includes a unit array, a unit decoder and a cell distribution circuit. The unit array includes a plurality of programmable units, each of which has a plurality of one-time programmable cells. The unit decoder generates a unit select signal for selecting a programmable unit of the unit array based on an address signal. The cell distribution circuit generates an odd-numbered cell programming signal for programming one of odd-numbered one-time programmable cells of the plurality of the one-time programming cells of the programmable unit that is selected by the unit select signal, and an even-numbered cell programming signal for programming one of even-numbered one-time programmable cells of the plurality of the one-time programming cells, based on previous data state of the selected programmable unit received from the unit array, and present data state to be programmed to the selected programmable unit.

Abstract: We describe a semiconductor memory device including a memory cell array and a storage device to store access data. The memory cell array is accessed responsive to the access data. The memory cell array access is determined by the access data stored in the storage device. The memory cell array is accessed according to access data only if necessary, drastically reducing power dissipation.

Abstract: An arithmetic circuit is provided having a compact and high-speed logic-in-memory wherein various operations are performed. The arithmetic circuit includes a memory element having a variable resistance element R in which the state of resistance changes reversibly between the state of high resistance and the state of low resistance by applying voltages with different polarities between one electrode and the other electrode, and at least one transistor of MRD, MRS, MW1 and MW2 connected respectively to both ends of the memory element; wherein data is stored in the memory element, the operation for the external data X, W, Y1 and Y2 input through any of the transistors is performed by applying potential to each of the ends of the memory element through the transistors MRD, MRS, MW1, and MW2, and a result of the operation is output from the memory element.

Abstract: Methods and apparatus for the protection of memory within an integrated circuit (IC) are provided for various phases of operation of the IC. Various portions of sensitive data may be contained within battery backed random access memory (RAM) (310), which may then be protected using either a passive, or an active, zeroization sequence depending upon the phase of operation of the IC. In an idle state, detection circuit (324) senses a drop in battery power (VBATT) to launch active destruction of RAM (310) memory using active zeroization circuits (312 and 314). In a configuration state, detection circuit (402) or (504) senses a drop in battery power (VBATT) to launch active destruction of RAM (310) memory using active zeroization circuits (312 and 314). In an operational state, various methods may be employed to detect and counteract the unauthorized access to RAM (310).

Abstract: The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.

Abstract: Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data and the parity data are exchanged with each other by a switch circuit, so that the regular data can be written to the parity cell array and the parity data can be written to the regular cell array. This enables the write of desired data to the parity cell array. A test of the parity data can be easily conducted. In particular, a leakage test or the like between memory cells can be easily conducted.

Abstract: A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.

Abstract: An upside-down MRAM comprises a sense transistor and a plurality of sense lines. A first end of the sense transistor is electrically connected to a low voltage. The sense lines are electrically connected in parallel between a high voltage and a second end of the sense transistor. Each of the sense lines has a control logic and at least one memory bit, and the memory bit is connected in series between the high voltage and the control logic.

Abstract: A semiconductor memory having at least one memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal. The invention also relates to a tri-state driver device for driving the control signal. Further, there is a method for operating a memory, in which the memory has a memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal.

Abstract: A memory driver architecture and associated methods are generally described.

Abstract: A bit line over driving control signal generator generates an over driving control signal in response to an over driving signal. The over driving signal is generated in response to an active command. The bit line over driving control signal generator for use in a semiconductor memory device includes a delaying unit for delaying an over driving signal generated in response to an active command to thereby output a delayed over driving signal, a controlling unit for determining whether the delayed over driving signal is outputted without any modification or outputted with being disabled in response to the over driving signal, a read command, and a precharge command, and a pulse width adding unit for adding a predetermined pulse width of the delayed over driving signal to the over driving signal to thereby output a bit line over driving control signal.

Abstract: In one embodiment of the invention, a block of configuration memory has rows of memory cells, at least one row having a set of one or more dual-port memory cells adapted to selectively store either configuration data or local data. The configuration address line for that row is segmented such that the address line is connected to the configuration address ports of the dual-port memory cells via access control circuitry that can be programmably configured to prevent access to those memory cells via the configuration address line. The access control circuitry enables local data to be efficiently and accurately stored in the dual-port memory cells without interference from configuration readback operations during normal operation or from partial reconfiguration of the configuration memory.

Abstract: A programmable priority encoder is disclosed for use with the device such as a Content Addressable Memory (CAM) device having a plurality of array objects to be encoded in binary and arranged in row and columns. Match lines are adapted to be connected to a plurality of arrayed objects associated with respective rows. A plurality of encoder cells, each having a memory element and forming an encoder block are arranged in rows. Precharged bus lines are operative with the encoder cells and match lines. The precharged bus lines are discharged indicating a match and priority is assigned to rows based on logic values stored within the memory elements of the encoder cell.

Abstract: A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of columns of memory cells are contained in each of the four banks. The bank in which an item of data are stored is determined by either the memory device, a memory controller or a processor based on one or more of several factors. For example, the bank in which the data are stored may be determined by the nature of the data or the length of data bursts written to or read from the memory device. Alternatively, the bank in which the data are stored may be determined based on the source of data written to the memory device or destination for data read from the memory device.

Abstract: A dual-port memory includes a plurality of memory cells coupled to a row decoder and column logic. Each memory cell includes two storage nodes, where each storage node is coupled to a bit line via an access transistor. Each memory cell also includes a logic gate for logically combining a word line signal with a column address signal and providing the resulting output signal to the gates of the access transistors. In one embodiment, the logic gate is a NOR logic gate and in another embodiment, the logic gate is a transmission gate. This prevents a potential read disturb problem with unselected memory cells of a row. This also reduces power consumption in the memory.

Abstract: A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or gate the wordline signal until an enable signal has arrived at the logic circuit. The access device improves stability and eliminates early read problems.

Abstract: An RRAM flip-flop rcell memory of the type having a write address decoder, a read address decoder, a set of n flip flops, one AND gate associated with each flip flop in the set, a set of w OR gates where each of the w OR gates in the set has n inputs, the improvement comprising only one write address decoder, and replacing the read address decoder and the set of AND gates and the set of OR gates with no more than one multiplexor, thereby providing a reduction in a path length from an rcell memory input to an rcell memory output and thereby improving timing of the rcell memory, while reducing fanout size of the rcell. In a preferred embodiment, the multiplexor includes fewer than w OR gates, and fewer than n AND gates, and two decoders, which are commonly connected to outputs of the n flip flops.

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

Abstract: Provided is a decoding circuit for a memory device which is improved in an operation of chip so as to enable the operation to be predictable by making a decoded result corresponding to an undefined code get a specific value. The decoding circuit for a memory device generates address signals by control signals set with a mode, and comprises a first logical circuit for decoding and outputting a result value defined by logically-combining the address signals corresponding to a first group and a second logical circuit for performing a decoding operation to have address signals with a specific value included in the defined result value by logically-combining address signals corresponding to a second group, by dividing the address signals into the first group corresponding to at least one defined result value and the second group corresponding to an undefined result value.

Abstract: Apparatus and methods for increasing a number of selectable options for an operating mode. A number of selectable options for an operating mode is increased by programming a first register with data selecting one option of a set of options for the operating mode. A second register is programmed with data selecting one of a plurality of sets of options for the operating mode. The data programmed in the first register selects one of the options of the set of options selected by the data programmed in the second register.