Abstract: A semiconductor system includes a controller configured to apply code signals for setting levels of a reference voltage and data, and to receive output data. The semiconductor system also includes a semiconductor device configured to receive the data for the respective levels of the reference voltage set according to the code signals, to compare the reference voltages with the data to generate new data, to store the new data as internal data, and to process the stored internal data to output as the output data.

Abstract: The nonvolatile storage device includes a variable resistance element (106) and a write circuit (101) which writes data into the variable resistance element, wherein the variable resistance element has a property of changing from a first resistance state (LR state or HR state) to a second resistance state (HR state or LR state) when a pulse of a first voltage (Vh or Vl) is applied to the variable resistance element, and changing from the second resistance state to the first resistance state when a pulse of a second voltage (Vl or Vh) is applied to the variable resistance element, and the write circuit applies, to the variable resistance element, at least the pulse of the first voltage, a pulse of a third voltage (VlLow or VhLow), and the pulse of the first voltage in this order, when the variable resistance element is caused to change from the first resistance state to the second resistance state.

Abstract: In a semiconductor memory device, the output of a regulator is coupled to the inputs of first and second switches, the output of the first switch is coupled to a path for supplying the drain voltage of a memory cell in the first mode, and the output of the second switch is coupled to a path for supplying the gate voltage of the memory cell in the second mode. A fourth switch is placed in parallel with the second switch: the output of the fourth switch is coupled to the output of the second switch, to supply the gate voltage of the memory cell in the first mode. Thus, one regulator is used as both the regulator for the drain voltage of the memory cell and the regulator for the gate voltage of the memory cell.

Abstract: According to one embodiment, a voltage generation circuit includes a first boost circuit, a first output circuit, a rectifying circuit, a second output circuit, and a detection circuit. The first boost circuit outputs a first voltage in first and second operation modes. The first output circuit is connected to the first boost circuit, and outputs the first voltage as a second voltage in the first operation mode. The rectifying circuit is connected to the first boost circuit, and outputs a third voltage which is lower than the first voltage in the first operation mode. The second output circuit short-circuits the rectifying circuit in the second operation mode, and outputs the first voltage as a fourth voltage. The detection circuit detects the second and fourth voltages which are supplied from the first and second output circuits.

Abstract: A data retention method that includes sampling a plurality of nonvolatile memory devices included in a data storage device to detect retention information for each of the nonvolatile memory devices in response to a request of a host and outputting, from the data storage device to the host, sampling data based on a result of the sampling, determining, at the host, whether to perform a retention operation on each of the nonvolatile memory devices based on the sampling data, and performing the retention operation on each of the nonvolatile memory devices based on a result of the determination.

Abstract: A driver for a semiconductor memory includes: a selection controller configured to output a target charge current select signal and a bucket charge current select signal in response to an inputted memory cell address and a target charge current value and a bucket charge current value, which are to be applied to a memory cell of the memory cell address; a current supply unit configured to supply a target charge current to the memory cell of the memory cell address in response to the target charge current select signal; and a bucket charge current supply unit configured to supply a bucket charge current to the memory cell of the memory cell address, in order to pre-charge the memory cell of the memory cell address in response to the bucket charge current select signal.

Abstract: A semiconductor device comprises a first transistor connected between a bit line and a sense node, and a second transistor amplifying a signal of the sense node. A first potential applied to a gate of the first transistor, a second potential supplied to the sense node, and a third potential supplied to the bit line are controlled so that the first potential applied to a gate of the first transistor is between the second and third potentials, the second potential is set larger than the third potential, and a predetermined potential obtained by subtracting a threshold voltage of the first transistor from the first potential is smaller than the third potential and higher than a low potential supplied to the second transistor. A potential of the bit line transitions from the third potential toward the low potential in accordance with data of a current change memory cell.

Abstract: Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. Examples of leakage measurement systems described herein may be included in memory devices.

Abstract: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump.

Abstract: A semiconductor device is provided with first and second main word lines, and a control circuit. The control circuit, in response to a command signal received from outside of the semiconductor device, activates the first main word line at a first timing, and activates the second main word line at a second timing different from the first timing, the first main word line maintaining an activation state at said second timing.

Abstract: A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.

Abstract: A memory includes a data pin, an address pin, and a reference voltage generation circuit. The reference voltage generation circuit includes a first reference voltage generation circuit and a second reference voltage generation circuit. The first reference voltage generation circuit is electronically connected to the data pin, and supplies a reliable first reference voltage to the data pin. The second reference voltage generation circuit is electronically connected to the address pin, and supplies a reliable second reference voltage to the address pin.

Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

Abstract: A semiconductor device including a plurality of capacitance units connected in parallel between a first voltage and a second voltage. Each of the plurality of capacitance units includes: a capacitance element connected with the first voltage; and a capacitance disconnecting circuit connected between the second voltage and the capacitance element. The capacitance disconnecting circuit includes a non-volatile memory cell with a threshold voltage changed based on a change of a leakage current which flows from the capacitance element, and blocks off the leakage current based on a rise of the threshold voltage of the non-volatile memory cell when the leakage current exceeds a predetermined value.

Abstract: A semiconductor storage device includes: a cell array including a plurality of first wirings, a plurality of second wirings intersecting the first wirings, and memory cells positioned at intersecting portions between the first wirings and the second wirings, each of the memory cells having a series circuit of a non-ohmic element and a variable resistance element; a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit from a low resistance state to a high resistance state, to the memory cells through the first wirings and the second wirings; and a bias voltage application circuit configured to apply a bias voltage, which suppresses a potential variation caused by the transition of the variable resistance element from the low resistance state to the high resistance state, to one end of the variable resistance element.

Abstract: A semiconductor memory device includes: a reference voltage generation unit configured to generate first and second reference voltages, wherein a level of the first reference voltage increases with decreasing internal temperature, and a level of the second reference voltage decreases with decreasing internal temperature; and a level control unit configured to control an internal voltage in response to the first and second reference voltages so as to decrease the absolute value of the internal voltage.

Abstract: A nonvolatile memory device includes a memory cell array configured to comprise a number of cell strings, a number of page buffers each coupled to the cell strings of the memory cell array through bit lines, and a bit line precharge circuit configured to precharge a selected bit line up to a voltage of a first level before one of the page buffers precharges the selected bit line.

Abstract: Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.

Abstract: A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending on the operation speed; and an internal circuit operated using the internal voltage.

Abstract: Methods of encoding data to and decoding data from flash memory devices are provided. User data having an unknown ratio of 1's to 0's is received. The user data is utilized in generating transformed data that has a predictable ratio of 1's to 0's. The transformed data is stored to flash memory. The transformed data is illustratively generate by either applying an “exclusive or” function to the user data or by converting the user data into a number having a greater number of bits.

Abstract: Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method further includes a second read step including reading the first memory cell by applying a second set of read voltages and none of the voltages in the first set to the first memory cell when it is determined that the first read step results in an error and cannot be corrected with error correction. The second read step is performed by using data resulting from the first read step.

Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

Abstract: A memory device is provided. The memory device includes a first signal line, a memory cell array, first and second voltage adjustment circuits. The memory cell array is divided into first and second areas and includes first memory cells in the first area and second memory cells in the second area. The first and second memory cells are coupled the first signal line. Each of the first and second memory cells has a reference node. The first voltage adjustment circuit adjusts voltages at the reference nodes of the first memory cells. The second voltage adjustment circuit adjusts voltages at the reference nodes of the second memory cells. The reference nodes of the first memory cells are coupled to a ground through the first voltage adjustment circuit. The reference nodes of the second memory cells are coupled to the ground through the second voltage adjustment circuit.

Abstract: Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

Abstract: Sense amplifiers and operations thereof are described. More particularly, embodiments of integrated circuit having a sense amplifier coupled to a first bitline and a second bitline of a memory array are described. The sense amplifier generally includes: a latch circuit and a group select input/output circuit, as well as read, reference voltage, and precharge circuitry. Further described is an embodiment of a method for a refresh operation. First data states of a group of memory cells of an array are read and written back as second data states without changing voltages at sense nodes of the latch circuits from the reading, where the second data states are an inverse of the first data states.

Abstract: A method for reading a memory element within a crossbar array includes switching a column line connected to a target memory element of the crossbar array to connected to an input of a current mirror; applying an error voltage to unselected rows of the crossbar array; applying a sense voltage to a row line connected to the target memory element; and measuring an output current of the current mirror.

Abstract: A nonvolatile memory device includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

Abstract: A digital memory system includes a memory controller having a driver configured for generating a digital signal. A memory module has a receiver in communication with the driver. The driver is configured for selectively directing the digital signal to the receiver of the memory module. A voltage control module is configured for determining a traffic intensity at which the digital signal is directed to the receiver and dynamically adjusting the reference voltage as a function of the traffic intensity at which the digital signal is directed to the receiver.

Abstract: Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.

Abstract: When overdriving a first power supply voltage supplied to a sense amplifier, a line for the first power supply voltage and a line for a second power supply voltage which is higher than the first power supply voltage are connected to each other by a first transistor, thereby boosting the first power supply voltage. When the first power supply voltage drops upon activation of the sense amplifier, the line for the first power supply voltage and the line for the second power supply voltage are connected to each other by a second transistor, thereby increasing the current supply capability. The first transistor and the second transistor are fully driven to operate as switches.

Abstract: A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

Abstract: In a semiconductor nonvolatile memory device, nonvolatile memory cells are plurally arranged in a memory array portion. An output circuit outputs setting information selected from plural sets of setting information to generate reference currents with different current values. A reference current circuit generates a reference current with a current value according to the setting information outputted from the output circuit. An amplifier circuit compares a cell current outputted from a selected memory cell of the memory array portion with the reference current generated by the reference current circuit.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.

Abstract: An internal voltage generating circuit of a semiconductor memory apparatus includes a first voltage generating unit to output a first output voltage to a common node, the first output voltage is generated in response to a first reference voltage, and a second voltage generating unit to output a second output voltage to the common node, the second output voltage is generated in response to a second reference voltage.

Abstract: A verification circuit for a capacitor power supply measures at least two voltages across the terminals of the capacitor at two points in time, the two points in time defining a time interval dT. A change in voltage dV over the time interval dT is determined. An operation powered by the capacitor is initiated, or not, by deriving from the time interval dT and/or the voltage change dV, a total required time or a total required voltage for completing the operation, and comparing the total required time or total required voltage to a pre-determined necessary total time or predetermined necessary total voltage, respectively (a “time interval test”).

Abstract: Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a first detecting circuit, a second detecting circuit, a switching circuit and a recovery control circuit. The first detecting circuit outputs a first detection signal which shows whether an externally supplied external power supply is equal to or more than a first voltage. The second detecting circuit outputs, at a higher speed than the first detecting circuit, a second detection signal which shows whether the external power supply is equal to or more than the first voltage. In a write operation, the switching circuit outputs the second detection signal output from the second detecting circuit. In an operation other than the write operation, the switching circuit outputs the first detection signal output from the first detecting circuit. The recovery control circuit terminates the write operation according to the second detection signal output from the switching circuit.

Abstract: A first embodiment of the present invention is a system for generating a voltage comprising a comparator operable to compare an operation voltage to a reference voltage, control logic operable to selectively output as a control signal an incremented signal or a decremented signal based on a comparison of the operation voltage to the reference voltage by the comparator, and a device module operable to increase or decrease the operation voltage based on the control signal.

Abstract: In various embodiments, a reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (e.g., Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply.

Abstract: One embodiment of the present invention sets forth a clamping circuit that is used to maintain a bit line of a storage cell in a memory array at a nearly constant clamp voltage. During read operations the bit line is pulled high or low from the clamp voltage by the storage cell and a change in current on the bit line is converted by the clamping circuit to produce an amplified voltage that may be sampled to read a value stored in the storage cell. The clamping circuit maintains the nearly constant clamp voltage on the bit line. Clamping the bit line to the nearly constant clamp voltage reduces the occurrence of read disturb faults. Additionally, the clamping circuit functions with a variety of storage cells and does not require that the bit lines be precharged prior to each read operation.

Abstract: Some embodiments of the invention relate to a sense amplifier configured to determine the slope of a bitline charging voltage and to utilize the determined slope in combination with a voltage level sensing scheme to aid in reading data from a memory cell associated with the bitline. In particular, a sense amplifier circuit is configured to determine a slope of a bit line charging voltage and based upon the determined slope to adjust the slope of the bitline voltage (e.g., by adding a dynamic slope dependent current to a memory cell current configured to charge the bitline) provided to a sense amplifier. By adjusting the slope of the bitline voltage, the charging speed of memory cells in a low resistive state (e.g., having a high cell current and therefore a good SNR) can be increased.

Abstract: There is provided a non-volatile storage device including: a memory array section arrayed with plural non-volatile memory cells for electronically writable data storage; plural bit lines that are connected to respective memory cells and have voltage levels that change according to the data stored in the memory cells; a supply section that supplies a voltage of a reference level to act as a comparator reference when determining data stored in the memory cells; a comparator section that compares the voltage level of the bit line connected to the memory cell subject to reading against the reference level supplied by the supply section; and a charging section that, in preparation for comparison by the comparator section, charges the bit line connected to the memory cell subject to reading to the voltage of the reference level supplied by the supply section.

Abstract: In one embodiment, a voltage discharge (VD) system has a slow VD subsystem that provides two concurrent discharge current paths to at least begin to discharge both positive and negative voltages: a first path from the positive-voltage node to ground and a second path from the positive-voltage node to the negative-voltage node. In addition to this relatively slow VD subsystem, the VD system can also have a conventional fast VD subsystem that is turned on after the slow VD subsystem has reduced the positive and negative voltages to some degree (e.g., half of each charge removed). Such a VD system can eliminate dangerous overshoot conditions, even when control-signal skew is present.

Abstract: Deterioration of holding characteristics due to fluctuations in power supply voltage VDD is prevented. During ting ending in one of memory circuits, a pair of bit lines in the other memory circuit is controlled to a dummy-bit-line voltage ranging from a ground voltage to ½×VDD. In a subsequent precharge period, a pair of bit lines in one of the memory circuits and the pair of bit lines in the other memory circuit are coupled to a reference voltage generating circuit.

Abstract: Multiple dies can be stacked in what are commonly referred to as three-dimensional modules (or “stacks”) with interconnections between the dies, resulting in an IC module with increased circuit component capacity. Such structures can result in lower parasitics for charge transport to different components throughout the various different layers. In some embodiments, the present invention provides efficient power distribution approaches for supplying power to components in the different layers. For example, voltage levels for global supply rails may be increased to reduce required current densities for a given power objective.

Abstract: A semiconductor device includes a plurality of memory cells connected to a word line, sense amplifiers arranged correspondingly to the memory cells, and a sense-amplifier control circuit that activates the sense amplifiers in response to selection of the word line and temporarily reduces driving performance of the sense amplifiers in response to a request for writing of data to any one of the memory cells. With this configuration, inverted data can be quickly overwritten to the sense amplifier. Furthermore, because a collective control is executed on the sense amplifiers to be activated, instead of individually controlling the sense amplifiers to be activated, the circuit scale of the sense-amplifier control circuit can be reduced.

Abstract: A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify operation. The first load voltage is subsequently recharged by charge sharing from the second load voltage so that the charge pump is not initially necessary for recharging the first load voltage.

Abstract: There is provided a non-volatile storage device including: a bit line that is connected to a non-volatile storage element and is applied with a voltage of magnitude corresponding to the logic value stored in the storage element; a charging section that charges the bit line to a voltage of equivalent magnitude to the reference voltage; a voltage generation section that is connected between the reference voltage line and the bit line, comprises a capacitance load for generating coupling charge when charging by the charging section has been performed, and employs the capacitance load to generate a voltage according to a difference between the magnitude of the voltage of the reference voltage line and the magnitude of the voltage of the bit line as a voltage expressing the comparison result; and a charge absorbing section for absorbing the coupling charge generated by the capacitance load.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects which extend in a first direction and are arranged in a second direction perpendicular to the first direction, a plurality of second interconnects which extend in the second direction and are arranged in the first direction, and a plurality of first storage modules which are formed in regions where the first interconnects and the second interconnects cross. The semiconductor memory device further comprises a first interconnect control module which supplies a voltage to the first interconnects, detects a first current flowing in the first interconnects, and outputs a first voltage corresponding to the first current, a reference voltage generator module which generates a second voltage based on a second current, and a regulator which generates a third voltage based on the first voltage and the second voltage.