Abstract: A semiconductor memory device includes a cell array having a plurality of memory cells, each memory cell including a resistive element and a cell transistor between a bit line and a source line, and a source line voltage supply unit configured to supply, in a normal mode, a reference source line voltage to the source line, and in a test mode, a first source line voltage to the source line when data in a first state is recorded and a second source line voltage to the source line when data in a second state is recorded, the first source line voltage being lower than the reference source line voltage, and the second source line voltage being higher than the reference source line voltage.

Abstract: A reference generator with programmable m and b parameters and methods of use are provided. A circuit includes a first generator operable to generate a first voltage including a fraction of a supply voltage. The circuit further includes a second generator operable to generate a second voltage. The circuit further includes a mixer and buffer circuit operable to output a reference voltage including a sum of the first and second voltages.

Abstract: Among other things, techniques for facilitating a write operation to a bit cell are provided. A pulse generator initializes lowering of an internal voltage level associated with a bit cell that is to be written to by a write operation. In this way, the bit cell is placed into a writeable voltage state, such that a potential of the bit cell can be overcome by the write operation. A voltage detector sends a reset signal to the pulse generator based upon the pulse generator lowering the internal voltage level past a reset trigger level. Responsive to receiving the reset signal, the pulse generator initializes charging of the internal voltage level to an original voltage level. In this way, the lowering of the internal voltage level is controlled so that one or more other bit cells are not affected (e.g., suffer data retention failure) by the relatively lower internal voltage level.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: A semiconductor device comprises a first region and a second region. The first region includes a plurality of memory cells each of which holds respective data and a plurality of sense amplifiers that respectively amplify the data in the plurality of memory cells, based on a first voltage. The second region is provided along one side of the first region and includes a first power supply generation circuit that generates the first voltage, based on a second voltage. The second voltage being supplied to the first power supply circuit by a first power supply interconnect extends on the first region in a first direction parallel to the one side of the first region.

Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of memory array processed by a program operation according to input data, and the comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array, a control circuit, a current limiting circuit and a current suppression circuit. The memory cell array has a first line, a second line, and a memory cell arranged therein, the memory cell being connected between the first line and the second line and including a variable resistance element. The control circuit is configured to apply, via the first line and the second line, a voltage required in operation of the memory cell. The current limiting circuit is connected to the first line and configured to limit a current flowing in the memory cell to a certain limit value. The current suppression circuit is configured connectable to the second line and configured to suppress a current flowing in the second line according to a kind of operation on the memory cell.

Abstract: A circuit includes a memory array comprising K number of rows. The circuit further including a reference column. The reference column includes M cells of a first cell type configured to provide a first leakage current, K-M cells of a second cell type different from the first cell type, the K-M cells are configured to provide a second leakage current, and a reference data line connected to the cells of the first cell type and the cells of the second cell type. The circuit further includes a sensing circuit configured to determine a value stored in a memory cell of the memory array based on a voltage of the reference data line.

Abstract: The present disclosure includes devices, methods, and systems for sensing memory, such as resistance variable memory, among other types of memory. One or more embodiments can include a method for generating currents to be used in sensing a memory cell, the method including providing a number of initial currents, and generating a number of reference currents by summing particular combinations of the initial currents.

Abstract: A bit alterable memory may include current generators in a periphery outside the main memory core. Current may be generated in the periphery and driven into the core. As a result, the capacitance of the memory cells has a lowered effect. The current may be generated using the chip supply voltage and then mirrored using a pump voltage. In some embodiments, the mirroring may be ratioed at the partition level and multiplied at the plane level. A delay may be provided before applying the currents to the cell to accommodate for transients.

Abstract: An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations.

Abstract: A device that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit.

Abstract: A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit further includes voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, and (ii) apply a second voltage to a second group of associated bit lines, and (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage.

Abstract: Semiconductor device capable of preventing off-leakage of the transistor may include a pulse voltage generator configured to generate a pulse voltage, and a transistor configured to have a gate provided with the pulse voltage. The transistor is in an off state in response to the pulse voltage.

Abstract: The present technology relates to an electronic device, and more particularly, to a semiconductor device. The semiconductor device includes a peripheral circuit, a power output line connected to the peripheral circuit and configured to transmit an operation voltage to the peripheral circuit, a current compensator including an OP-amplifier connected to the power output line, and a capacitor connected between an output terminal of the OP-amplifier and the power output line.

Abstract: A memory circuit including at least one memory cell connected to a bit line. The memory circuit further includes a means for providing a bit line reference voltage VBLref to the bit line. A VBLref/VDD ratio of the bit line reference voltage VBLref to a power voltage VDD is adjustable corresponding to a change of the power voltage VDD, and the VBLref/VDD ratio ranges from about 0.4 to about 0.53.

Abstract: Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

Abstract: A semiconductor integrated circuit includes a write path coupled to a pad, a read path coupled to the pad, and a reference voltage output control block configured to apply a reference voltage to the pad through the write path in response to a reference voltage monitoring signal. The read path is electrically isolated from the pad in response to the reference voltage monitoring signal.

Abstract: A semiconductor memory device and a method for generating a reference voltage needed for operating the same are disclosed. The semiconductor memory device includes a first decoder configured to generate a default set signal in response to a reset signal and a clock enable signal, a second decoder configured to generate a reference voltage set signal in response, and a reference voltage provider configured to generate an internal reference voltage.

Abstract: A sense amplifier system includes a first path, a second path, a memory cell, a first reference cell, a second reference cell, and a switch component. The switch component is configured to switch connections between the first and second reference cells and the first and second paths according to a sampling phase and an amplification phase.

Abstract: A memory element in which the temperature coefficient of a memory cell substantially matches the temperature coefficient of a reference cell and tuning either the temperature coefficient of a memory cell to substantially match the temperature coefficient of the reference cell provides for improved precision of sensing or reading memory element states, particularly so as to minimize the affect of temperature variations on reading and sensing states.

Abstract: According to example embodiments, a nonvolatile memory device includes a memory cell array including a plurality of memory cells stacked on a substrate, a plurality of word lines connected with the memory cell array, a plurality of pass voltage generators, and a voltage control circuit. The pass voltage generators each include a plurality of current paths and are configured to generate pass driving signals applied to unselected word lines of the plurality of word lines. The voltage control circuit is configured to control rising slopes of the pass driving signals generated from the plurality of pass voltage generators, based on adjusting the number of current paths in each pass voltage generator used to generate each driving signal.

Abstract: A memory device comprises a memory cell array, a first and a second pre-charging switch circuits, a selecting circuit, an auxiliary memory cell array, a dynamic voltage controller and a sense amplifier. The auxiliary memory cell array comprises an auxiliary read bit line and a plurality of memory cells arranged in a column and electrically connected to the auxiliary read bit line. The second pre-charging switch circuit determines whether or not to supply a reference voltage to each of the aforementioned memory cells according to a pre-charging control signal. The dynamic voltage controller determines whether or not to supply a voltage to the auxiliary read bit line according to the voltage level of the output signal of the selecting circuit. The sense amplifier compares the voltage levels of the output signal of the selecting circuit and the voltage on the auxiliary read bit line to output a sensing result accordingly.

Abstract: A nonvolatile memory device including a plurality of memory cells arranged at a region where a word line and a bit line cross each other, a voltage generator configured to generate a program voltage to apply to the word line by increasing the program voltage by an increment whenever a program loop is repeated, a current sensing check unit configured to compare a number of failed memory cells among the memory cells to first and second reference values, and a control logic configured to control the voltage generator to change the increment according to the comparison result of the current sensing check unit.

Abstract: Controlling a non-volatile memory. The non-volatile memory includes a plurality of memory cells in an integrated circuit substrate. The non-volatile memory also includes a high-voltage node in power-transmissive communication with the plurality of memory cells. Further, the non-volatile memory includes an intermediate-voltage node in power-transmissive communication with the plurality of memory cells. Moreover, the non-volatile memory includes a counter-doped-gate device, coupled within the integrated circuit substrate, in power-transmissive communication between the high-voltage node and the intermediate-voltage node.

Abstract: An electronic device comprises a semiconductor memory cell having a bistable bit storage circuit having first and second power contact points. A first switch is coupled to the first power contact point to receive a first voltage. A second switch coupled to the second power contact point to receive a second voltage. Circuitry is provided for turning off the first and second switches to decouple the respective first and second voltages from the respective first and second power contact points, during stand-by operation of the electronic device.

Abstract: A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.

Abstract: An internal power source voltage generating circuit of a semiconductor memory and a corresponding method shorten an access delay upon transition of a data reading operation in an address period shorter than a prescribed minimum period to an operation in the prescribed minimum period. While a boosted voltage of an external power source voltage is supplied to the semiconductor memory as the internal power source voltage via an output line connected to one end of a condenser. A reference low potential is applied to the other end of the condenser and the external power source voltage is applied to the output line, thereby charging the condenser. If the internal power source voltage is lower than a threshold voltage, the internal power source voltage on the output line is boosted by applying the external power source voltage to the other end of the condenser.

Abstract: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

Abstract: Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node of the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.

Abstract: A circuit arrangement, having a plurality of electronic components; a plurality of first access lines and second access lines, wherein each electronic component is coupled with at least one first access line and at least one second access line; an access controller configured to control an access to at least one electronic component of the plurality of electronic components via the at least one first access line and the at least one second access line; a bias circuit configured to provide a defined potential to at least one of the first access lines, wherein the bias circuit is configured, during an access to an electronic component via one selected first access line of the plurality of first access lines, to provide the defined potential to one or two first access lines of the plurality of first access lines, wherein the one or two first access lines are arranged adjacent to the selected first access line, and, wherein during the access to the electronic component, the potentials of the first access lines of

Abstract: In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results.

Abstract: An internal voltage generation circuit includes a vblh voltage generation circuit that generates a voltage vblh that is supplied as a high-voltage power supply of a sense amplifier, and a voltage distribution control circuit that has a first current source that pulls down an output node and a second current source that pulls up the output node. The output node is pulled down by the first current source operating, and the voltage thereof is maintained at a voltage that corresponds to a lower limit of a detection voltage value. The output node is pulled up by the second current source operating, and the voltage thereof is maintained at a voltage that corresponds to an upper limit of the detection voltage value.

Abstract: Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such feedback path includes a capacitance coupled in series with a “one-way” isolation circuit through which a feedback signal is coupled. The “one-way” isolation circuit may allow the feedback signal to be coupled from a “downstream” node, such as an output node, to an “upstream” node, such as a node at which an error signal is generated to provide negative feedback. However, the “one-way” isolation circuit may substantially prevent variations in the voltage at the upstream node from being coupled to the capacitance in the isolation circuit. As a result, the voltage at the upstream node may quickly change since charging and discharging of the capacitance responsive to voltage variations at the upstream node may be avoided.

Abstract: A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.

Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

Abstract: A method includes determining a programming step size for a word line of a memory in a data storage device. The programming step size is determined at least partially based on a count of memory elements of the word line to be programmed to a particular state.

Abstract: Methods of operating nonvolatile memory devices including a plurality of cell strings each having at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor, the operating methods including receiving a command and an address, determining a voltage applying time in response to the input command and address, and applying a specific voltage to memory cells of cell strings corresponding to the input address during the determined voltage applying time.

Abstract: A nonvolatile semiconductor memory device, having a booster circuit capable of performing a boost operation with appropriate boost voltage arrival time without increasing the circuit size. The nonvolatile semiconductor memory device includes a timing generator circuit and a current load circuit which applies a current load to an output of a booster unit according to a signal from the timing generator circuit, thereby achieving an appropriate boost voltage arrival time by using the current load circuit in concert with the operation of erasing or writing on memory cells.

Abstract: A static random access memory (SRAM) is described and includes; a bit cell connected with a word line, connected between a bit line and a complementary bit line, and receiving an internal voltage from a write assist circuit. The write assist circuit includes a power control circuit that charges/discharges an internal voltage line to provide the internal voltage in response to at least one control signal, and a compensation circuit that controls a level of the internal voltage.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects which extend in a first direction and are arranged in a second direction perpendicular to the first direction, a plurality of second interconnects which extend in the second direction and are arranged in the first direction, and a plurality of first storage modules which are formed in regions where the first interconnects and the second interconnects cross. The semiconductor memory device further comprises a first interconnect control module which supplies a voltage to the first interconnects, detects a first current flowing in the first interconnects, and outputs a first voltage corresponding to the first current, a reference voltage generator module which generates a second voltage based on a second current, and a regulator which generates a third voltage based on the first voltage and the second voltage.

Abstract: A non-volatile memory device and a read method thereof are disclosed. The read method includes providing a memory block having memory cells connected to word lines and connected in serial to a bit line, sensing potential of the bit line by applying a first read voltage to a selected word line of the word lines and providing a first pass voltage to an unselected word line adjacent to the selected word line, sensing potential of the bit line by applying a second read voltage higher than the first read voltage to the selected word line and providing a second pass voltage lower than the first pass voltage to the unselected word line adjacent to the selected word line, and sensing potential of the bit line by applying a third read voltage higher than the second read voltage to the selected word line and providing a third pass voltage lower than the second pass voltage to the unselected word line adjacent to the selected word line.

Abstract: Some embodiments of the present disclosure relate to a memory array having a cell voltage generator configured to provide a cell voltage header to a plurality of memory cells. The cell voltage generator is connected to the memory cells by way of supply voltage line and controls a supply voltage of the memory cells. The cell voltage generator has a pull-down element coupled between a control node of the supply voltage line and a ground terminal, and a one or more pull-up elements connected in parallel between the control node and a cell voltage source. A control unit is configured to provide one or more variable valued pull-up enable signals to input nodes of the pull-up elements. The variable valued pull-up enable signals operate the pull-up elements to selectively connect the supply voltage line from the cell voltage source to provide a cell voltage header with a high slew rate.

Abstract: Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance.

Abstract: Providing for a two-terminal memory architecture that can mitigate sneak path current in conjunction with memory operations is described herein. By way of example, a voltage mimicking mechanism can be employed to dynamically drive un-selected bitlines of the memory architecture at a voltage observed by a selected bitline. According to these aspects, changes observed by the selected bitline can be applied to the un-selected bitlines as well. This can help reduce or avoid voltage differences between the selected bitline and the un-selected bitlines, thereby reducing or avoiding sneak path currents between respective bitlines of the memory architecture. Additionally, an input/output based configuration is provided to facilitate reduced sneak path current according to additional aspects of the subject disclosure.

Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. The comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein the output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and the comparison result indicates the number of different bits existing between the output data and the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract: A system and method to select a reference cell is disclosed. In a particular embodiment, a method is disclosed that includes receiving an address corresponding to a bit cell within a first bank of a memory. The method also includes accessing a second reference cell of a second bank of the memory in response to a first reference cell in the first bank being indicated as bypassed.

Abstract: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.