Abstract: A semiconductor device of an embodiment includes a seed generator circuit configured to generate a seed from inputted data by using first random number sequence data generated by an XorShift circuit; and a random number generator circuit configured to receive the seed as input to generate second random number sequence data by a second XorShift circuit.

Abstract: Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.

Abstract: A yield recovery scheme for configuration memory of an IC device includes asserting an override configuration value on a bitline of memory cells of the configuration memory, where a data node of a faulty one of the memory cells is coupled to a node of configurable circuitry of the IC device, and asserting a wordline of the faulty memory cell while the override configuration value is asserted on the bitline to couple the bitline to the node of the configurable circuitry through the faulty memory cell (i.e., to force a state of the data node to the override configuration value). An identifier of the faulty memory cell may be stored on the IC device (e.g., E-fuses), and control circuitry of the IC device may retrieve the identifier to configure override circuitry of the IC device.

Abstract: Semiconductor devices and methods of forming the same include forming an etch mask on a stack of alternating dielectric layers and conductor layers. An exposed portion of a dielectric layer and a conductor layer is etched away to form a wordline. The forming and etching steps are repeated, adding additional etch mask material at each iteration, to form respective wordlines at each iteration.

Abstract: Tracking circuitry for a memory device is disclosed. The tracking circuitry includes an inverter, a level shifter, delay circuitry, and a logic gate. The inverter is configured to receive a first clock signal and generate an inverted clock signal. The level shifter is configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal. The delay circuitry is configured to receive the level shifted clock signal and generate an inverted level shifted clock signal. The logic gate comprises a first input configured to receive the first clock signal and a second input configured to receive the inverted level shifted clock signal. The logic gate is configured to generate a second clock signal based on the first clock signal and the inverted level shifted clock signal.

Abstract: A semiconductor storage device includes a first signal line extending in a first direction, and second signal line extending in the first direction and adjacent to the first signal line in a second direction orthogonal to the first direction. The first signal line includes a trunk wiring extending in the first direction, and one or more branch wirings branched from the trunk wiring and extending on one side toward the second signal line in the second direction.

Abstract: A system and method for enhancing C*RAM, improving its performance for known applications such as video processing but also making it well suited to low-power implementation of neural nets. The required computing engine is decomposed into banks of enhanced C*RAM each having a SIMD controller, thus allowing operations at several scales simultaneously. Several configurations of suitable controllers are discussed, along with communication structures and enhanced processing elements.

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

Abstract: Methods, systems, and devices for techniques for communicating multi-level signals are described. A first device may be configured to communicate signals with a second device according to a modulation scheme. The first device may transmit a first signal to the second device at a first voltage level of the modulation scheme corresponding to a first multi-bit value. The first device may select a second voltage level of the modulation scheme based on a difference between the first voltage level and a third voltage level of the PAM scheme, and may transmit a second signal to the second device at the second voltage level to indicate a second multi-bit value corresponding to the third voltage level. The second device may decode the second signal to determine the second multi-bit value based on receiving the first signal at the first voltage level and the second signal at the second voltage level.

Abstract: The present disclosure relates to a shiftable memory comprising: a plurality of memory cells arranged in rows and columns, wherein the memory cells of the rows are interconnected, thereby forming chains of memory cells; at least one first serial output data port; output data logic for connecting an output of any of the chains of memory cells to the first serial output data port, or at least one first parallel output data port and at least one read shift register configured for serially collecting serial output data from the output of any of the chains of memory cells; and/or at least one first serial input data port; input data logic for connecting the first serial input data port to an input of any of the chains of memory cells, or at least one parallel input data port and at least one write shift register for serially shifting input data to the input of any of the chains of memory cells; and a controller configured to control the shifting of the data in the chains of memory cells, the controller further con

Abstract: Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.

Abstract: A method includes receiving, at a dynamic random access memory (DRAM) device, a single READ-THEN-CLEAR command. The single READ-THEN-CLEAR command has a column address of a column in an array of memory cells. Particular data content is stored in memory cells associated with the column address. The method also includes, in response to receiving the single READ-THEN-CLEAR command, reading the particular data content and clearing the particular data content after reading the particular data content.

Abstract: A latch device includes a memory cell, a pair of write switches and an output terminal. The memory cell stores a latch data, and the pair of write switches is coupled to the memory cell through a first node and a second node. The pair of write switches holds the latch data stored in the memory cell when logic values of a first input signal and a second input signal are a predetermined logic value, and updates the latch data stored in the memory cell when the logic values of the first input signal and the second input signal are mutually exclusive logic values. The output terminal is coupled to at least one of the first node and the second node and outputs an output signal based on the latch data stored in the memory cell. An operation of the latch memory is also introduced.

Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.

Abstract: In a recording device, a data memory including a DRAM having a write pointer for each of banks, and a queue control memory that stores an active flag is provided. When frame data is written into a write-target queue, a bank for which an active flag indicates an activated state is selected as a write-target bank among the banks to write the frame data, and if there is no bank for which an active flag indicates an activated state, a bank for which an active flag indicates a deactivated state is selected as a write-target bank, a row address of a write pointer of the bank is activated, and thereafter the frame data is written.

Abstract: The present disclosure provides a shift register including: a pre-charge reset circuit and an output circuit, the pre-charge reset circuit is configured to write, in a pre-charge stage, an input signal in an active level state into the pull-up node in response to the control of a first control signal, and write, in a reset stage, an input signal in an inactive level state into the pull-up node in response to the control of a second control signal; the output circuit is configured to write, in an output stage, a clock signal in an active level state into a signal output terminal in response to the control of an electric signal in an active level state at the pull-up node, and write, in the reset stage, a clock signal in an inactive level state into the signal output terminal in response to the control of the second control signal.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: A computing device in some examples includes an array of memory cells, such as 8-transistor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.

Abstract: The present disclosure includes a shift register unit circuit, including input storing module, configured to receive an input signal at an input terminal and store the input signal; storage retrieving module, configured to retrieve the input signal from the input storing module under influence of at least a first clock signal; output driving module, configured to transfer the input signal to an first output terminal under control of the storage retrieving module; and pulling-down and maintaining module, configured to pull down a voltage at the output terminal to low voltage level after output operation is completed, and maintain the voltage at low voltage level until the output driving module receives a next input signal. The present disclosure also includes a gate driver circuit including such shift register units and a method for generating gate driving signal.

Abstract: A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.

Abstract: A time-of-flight (TOF) sensor includes a light source structured to emit light and a plurality of avalanche photodiodes. The TOF sensor also includes a plurality of pulse generators, where individual pulse generators are coupled to individual avalanche photodiodes in the plurality of avalanche photodiodes. Control circuitry is coupled to the light source, the plurality of avalanche photodiodes, and the plurality of pulse generators, to perform operations. Operations may include emitting the light from the light source, and receiving the light reflected from an object with the plurality of avalanche photodiodes. In response to receiving the light with the plurality of avalanche photodiodes, a plurality of pulses may be output from the individual pulse generators corresponding to the individual photodiodes that received the light. And, in response to outputting the plurality of pulses, a timing signal may be output when the plurality of pulses overlap temporally.

Abstract: Systems, methods, and computer programs are disclosed for providing coincident memory bank access. One embodiment is a memory device comprising a first bank, a second bank, a first bank resource, and a second bank resource. The first bank has a first set of bitlines for accessing a first set of rows in a first memory cell array. The second bank has a second set of bitlines for accessing a second set of rows in a second memory cell array. The first bank resource and the second bank resource are selectively connected to the first set of bitlines or the second set of bitlines via a cross-connect switch.

Abstract: A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.

Abstract: The present disclosure provides a shift register unit. The shift register unit includes an input module, an output module and an output control module. The input module is connected to an input signal terminal, a first power supply signal terminal and a pull-up node, and is configured to transmit a first power supply signal to the pull-up node. The output module is connected to the pull-up node, a clock signal terminal and an output control node, and is configured to transmit a clock signal to the output control node. The output control module is connected to the output control node, the clock signal terminal and a signal output terminal, and is configured to transmit a signal of the output control node to the signal output terminal under the control of the clock signal.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: In a memory, multiple pieces of entry data sorted in ascending or descending order are stored associated with addresses. With whole addresses for storing the multiple pieces of entry data as an initial search area, the search circuit repeatedly performs a search operation for comparing entry data stored in a central address of the search area with the search data, outputting the address as a search result in the case of a match, and narrowing the search area for the next search based on a magnitude comparison result in the case of a mismatch.

Abstract: An address counting circuit includes an address counter suitable for counting an address in response to a counting signal; and a counting control block suitable for controlling the address counter to skip the address of at least one predetermined value.

Abstract: An address counting circuit includes an address counter suitable for counting an address in response to a counting signal; and a counting control block suitable for controlling the address counter to skip the address of at least one predetermined value.

Abstract: SRAM memory including: a matrix of memory cells; bit lines and word lines; read ports associated with the memory cells and coupled to the bit lines and to the word lines; local virtual ground, LVGND, lines each coupled to the reference potential terminals of the read ports of at least one row of memory cells; local control elements each configured to electrically couple one of the LVGND lines to a power supply potential or to a global virtual ground line, or GVGND line; a global control element configured to couple the GVGND line to the power supply electric potential or to a reference electric potential.

Abstract: Various implementations described herein are directed to circuitry having a bitcell array with bitcells arranged in columns and rows. The circuitry includes bitlines coupled to the columns of the bitcells and wordlines coupled to the rows of the bitcells. The bitcells are arranged in multiple groups of bitcells along corresponding wordlines in each row, and each group of bitcells in each row is configured to be shifted by at least one column with respect to another group of bitcells in a previous row.

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.

Abstract: A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.

Abstract: A system and method for controlling concurrent access to a shared resource in a distributed computing environment. A first user writes new data to the shared resource, then checks to see if at least one concurrent session to access the shared resource is running. If so, then the system does not allow the removal of data out of the shared resource. If not, then older data may be removed from the shared resource to make room for the new data.

Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

Abstract: Various embodiments provide for a multi-channel memory interface capable of supporting a multi-channel memory module (e.g., DIMM) that combines different memory types, such as DDR4/DDR5, DDR5/LPDDR5, or LPDDR4/LPDDR5, through a single physical layer (PHY) interface.

Abstract: A memory system has a non-volatile memory, a storage accessible at higher speed than the non-volatile memory, to store access information to the non-volatile memory before accessing the non-volatile memory, and a memory controller to control a write pulse width to the non-volatile memory based on a free space of the storage or based on the access information stored in the storage.

Abstract: Various embodiments, disclosed herein, include apparatus and methods of using the apparatus having a core array of memory cells arranged as data storage elements; and an array of latches to store repair information for the core array. Each latch can be structured as a static random access memory cell. Additional apparatus, systems, and methods are disclosed.

Abstract: Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.

Abstract: A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.

Abstract: A system and method are provided for system for adaptive refresh of a memory device having multiple integrated circuit chips. A command generation portion generates commands for actuating a plurality of operational tasks on the memory device, including at least read, write, and refresh operations for selectively addressed storage cells of the memory device. A command management portion stores the commands and selects from the commands for timely execution of corresponding operational tasks on the memory device. A refresh management portion coupled to the command generation and command management portions actuates a plurality of refresh operations adaptively interleaved with other operational tasks, such that recursive refresh of the storage cells is carried out for the memory device within a predetermined refresh window of time. The refresh management portion selectively actuates each refresh operation for a chip-based selection of storage cells, whereby the storage cells of a selected chip are refreshed.

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first electrode, a first magnetic layer, a first non-magnetic layer, a first conductive layer and a controller. The first magnetic member includes a first extending portion and a third magnetic portion. The first extending portion includes first and second magnetic portions. The third magnetic portion is connected with the second magnetic portion. The first electrode is electrically connected with the first magnetic portion. The first non-magnetic layer is provided between the first magnetic layer and at least a part of the third magnetic portion. The first conductive layer includes first and second conductive portions, and a third conductive portion being between the first conductive portion and the second conductive portion. The controller is electrically connected with the first electrode, the first magnetic layer, the first conductive portion and the second conductive portion.

Abstract: Multiport memory architecture is disclosed herein. An example memory includes an input port, a memory array, and an output port. The input port is coupled to receive data blocks and includes first and second buffers coupled to temporarily store alternate data blocks, and the output port is coupled to provide data blocks from the memory array. The memory array is partitioned into first and second partitions, with the first partition coupled to receive data blocks from the first buffer and the second partition coupled to receive data blocks from the second buffer, and the input port and the memory array are coupled to receive control signals to simultaneously receive a first data block at the first buffer, transfer a second data block from the second buffer to a first address in the second partition, and provide a third data block stored at a third address of the first partition.

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.

Abstract: A data processing method and apparatus, where the method includes acquiring a first network data packet that is sent by a target application that runs in an untrusted execution domain, where the first network data packet includes a first identifier; acquiring, in a trusted execution domain, first data corresponding to the first identifier; generating, in the trusted execution domain, a second network data packet according to the first data and the first network data packet; performing, in the trusted execution domain, encryption on the second network data packet by using a first session key to acquire an encrypted second network data packet; and sending the encrypted second network data packet to the target server. The data processing method and apparatus in the embodiments of the present invention can effectively prevent an attacker from stealing data.

Abstract: A memory device comprises an output buffer and a control circuit. The control circuit is configured to receive a system clock signal at an input of the control circuit. The control circuit is configured to generate a data transition signal based on the system clock signal. The control circuit is configured to provide the data transition signal to the output buffer of the memory device. The output buffer is configured to output memory data based on the data transition signal.

Abstract: The data transmission apparatus includes a prior stage shift register circuit and a plurality of rear stage shift register circuits. The prior stage shift register circuit is coupled to a sense amplifying device of the memory, receives sensed data from the sense amplifying device and outputs a plurality of the readout data in series by bitwise shifting out the sensed data according to a shift clock signal. The plurality of rear stage shift register circuits are coupled to the prior stage shift register circuit and respectively coupled to a plurality of pads. The plurality of rear stage shift register circuits respectively receive the readout data and respectively bitwise transport the readout data to the pads according to a clock signal. Wherein, a frequency of the shift clock signal is less than a frequency of the clock signal.

Abstract: The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments of the present disclosure include an apparatus comprising a shift register comprising an initial stage and a final stage. The shift register may be configured such that a clock signal may be initiated at the final stage of the shift register.

Abstract: An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a diode-connected device having a gate terminal coupled to the first supply node, and a source terminal coupled to second supply node; and a stack of devices coupled to the first supply node, wherein at least one device in the stack is coupled to the second supply node, and wherein the stack of devices is controllable according to an operation mode.

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.