With Shift Register Patents (Class 365/189.12)
  • Patent number: 11423823
    Abstract: The present disclosure provides a shift register including: a pre-charge reset circuit and an output circuit, the pre-charge reset circuit is configured to write, in a pre-charge stage, an input signal in an active level state into the pull-up node in response to the control of a first control signal, and write, in a reset stage, an input signal in an inactive level state into the pull-up node in response to the control of a second control signal; the output circuit is configured to write, in an output stage, a clock signal in an active level state into a signal output terminal in response to the control of an electric signal in an active level state at the pull-up node, and write, in the reset stage, a clock signal in an inactive level state into the signal output terminal in response to the control of the second control signal.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: August 23, 2022
    Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Xue, Hongmin Li, Yue Shi, Qinghua Jiang
  • Patent number: 11398267
    Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: July 26, 2022
    Assignee: III HOLDINGS 2, LLC
    Inventor: Michael C. Stephens, Jr.
  • Patent number: 11322195
    Abstract: A computing device in some examples includes an array of memory cells, such as 8-transistor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Mahmut Sinangil
  • Patent number: 11270624
    Abstract: The present disclosure includes a shift register unit circuit, including input storing module, configured to receive an input signal at an input terminal and store the input signal; storage retrieving module, configured to retrieve the input signal from the input storing module under influence of at least a first clock signal; output driving module, configured to transfer the input signal to an first output terminal under control of the storage retrieving module; and pulling-down and maintaining module, configured to pull down a voltage at the output terminal to low voltage level after output operation is completed, and maintain the voltage at low voltage level until the output driving module receives a next input signal. The present disclosure also includes a gate driver circuit including such shift register units and a method for generating gate driving signal.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: March 8, 2022
    Assignee: Peking University Shenzhen Graduate School
    Inventors: Shengdong Zhang, Yihua Ma, Congwei Liao
  • Patent number: 11037642
    Abstract: A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: June 15, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Haibo Li, Man Lung Mui
  • Patent number: 11029397
    Abstract: A time-of-flight (TOF) sensor includes a light source structured to emit light and a plurality of avalanche photodiodes. The TOF sensor also includes a plurality of pulse generators, where individual pulse generators are coupled to individual avalanche photodiodes in the plurality of avalanche photodiodes. Control circuitry is coupled to the light source, the plurality of avalanche photodiodes, and the plurality of pulse generators, to perform operations. Operations may include emitting the light from the light source, and receiving the light reflected from an object with the plurality of avalanche photodiodes. In response to receiving the light with the plurality of avalanche photodiodes, a plurality of pulses may be output from the individual pulse generators corresponding to the individual photodiodes that received the light. And, in response to outputting the plurality of pulses, a timing signal may be output when the plurality of pulses overlap temporally.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: June 8, 2021
    Assignee: OmniVision Technologies, Inc.
    Inventors: Olivier Bulteel, Eric A. G. Webster, Lindsay Grant
  • Patent number: 11024361
    Abstract: Systems, methods, and computer programs are disclosed for providing coincident memory bank access. One embodiment is a memory device comprising a first bank, a second bank, a first bank resource, and a second bank resource. The first bank has a first set of bitlines for accessing a first set of rows in a first memory cell array. The second bank has a second set of bitlines for accessing a second set of rows in a second memory cell array. The first bank resource and the second bank resource are selectively connected to the first set of bitlines or the second set of bitlines via a cross-connect switch.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: June 1, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Yanru Li, Dexter Chun, Jungwon Suh
  • Patent number: 10930338
    Abstract: A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: February 23, 2021
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Chikara Kondo
  • Patent number: 10923176
    Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 16, 2021
    Assignee: III HOLDINGS 2, LLC
    Inventor: Michael C. Stephens, Jr.
  • Patent number: 10923020
    Abstract: The present disclosure provides a shift register unit. The shift register unit includes an input module, an output module and an output control module. The input module is connected to an input signal terminal, a first power supply signal terminal and a pull-up node, and is configured to transmit a first power supply signal to the pull-up node. The output module is connected to the pull-up node, a clock signal terminal and an output control node, and is configured to transmit a clock signal to the output control node. The output control module is connected to the output control node, the clock signal terminal and a signal output terminal, and is configured to transmit a signal of the output control node to the signal output terminal under the control of the clock signal.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: February 16, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventors: Wei Xue, Hongmin Li, Ying Wang, Fengjing Tang, Li Sun
  • Patent number: 10891337
    Abstract: In a memory, multiple pieces of entry data sorted in ascending or descending order are stored associated with addresses. With whole addresses for storing the multiple pieces of entry data as an initial search area, the search circuit repeatedly performs a search operation for comparing entry data stored in a central address of the search area with the search data, outputting the address as a search result in the case of a match, and narrowing the search area for the next search based on a magnitude comparison result in the case of a mismatch.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: January 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tsutomu Makino
  • Patent number: 10867658
    Abstract: An address counting circuit includes an address counter suitable for counting an address in response to a counting signal; and a counting control block suitable for controlling the address counter to skip the address of at least one predetermined value.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Jae-Seung Lee, Hae-Rang Choi
  • Patent number: 10867659
    Abstract: An address counting circuit includes an address counter suitable for counting an address in response to a counting signal; and a counting control block suitable for controlling the address counter to skip the address of at least one predetermined value.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Jae-Seung Lee, Hae-Rang Choi
  • Patent number: 10847216
    Abstract: SRAM memory including: a matrix of memory cells; bit lines and word lines; read ports associated with the memory cells and coupled to the bit lines and to the word lines; local virtual ground, LVGND, lines each coupled to the reference potential terminals of the read ports of at least one row of memory cells; local control elements each configured to electrically couple one of the LVGND lines to a power supply potential or to a global virtual ground line, or GVGND line; a global control element configured to couple the GVGND line to the power supply electric potential or to a reference electric potential.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: November 24, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Jean-Philippe Noel
  • Patent number: 10847215
    Abstract: Various implementations described herein are directed to circuitry having a bitcell array with bitcells arranged in columns and rows. The circuitry includes bitlines coupled to the columns of the bitcells and wordlines coupled to the rows of the bitcells. The bitcells are arranged in multiple groups of bitcells along corresponding wordlines in each row, and each group of bitcells in each row is configured to be shifted by at least one column with respect to another group of bitcells in a previous row.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 24, 2020
    Assignee: Arm Limited
    Inventors: Andy Wangkun Chen, Yew Keong Chong
  • Patent number: 10789996
    Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Harish N. Venkata, Guy S. Perry
  • Patent number: 10762865
    Abstract: A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 1, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Youichi Tobita
  • Patent number: 10725997
    Abstract: A system and method for controlling concurrent access to a shared resource in a distributed computing environment. A first user writes new data to the shared resource, then checks to see if at least one concurrent session to access the shared resource is running. If so, then the system does not allow the removal of data out of the shared resource. If not, then older data may be removed from the shared resource to make room for the new data.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 28, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Shu-Shang Sam Wei, Raghavendra A. Rao, Shuaib Hasan Khwaja
  • Patent number: 10705989
    Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: July 7, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Holden Jessup
  • Patent number: 10642538
    Abstract: Various embodiments provide for a multi-channel memory interface capable of supporting a multi-channel memory module (e.g., DIMM) that combines different memory types, such as DDR4/DDR5, DDR5/LPDDR5, or LPDDR4/LPDDR5, through a single physical layer (PHY) interface.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: John M. MacLaren, Jeffrey S. Earl, Anne Hughes
  • Patent number: 10592163
    Abstract: A memory system has a non-volatile memory, a storage accessible at higher speed than the non-volatile memory, to store access information to the non-volatile memory before accessing the non-volatile memory, and a memory controller to control a write pulse width to the non-volatile memory based on a free space of the storage or based on the access information stored in the storage.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki Noguchi, Shinobu Fujita
  • Patent number: 10522235
    Abstract: Various embodiments, disclosed herein, include apparatus and methods of using the apparatus having a core array of memory cells arranged as data storage elements; and an array of latches to store repair information for the core array. Each latch can be structured as a static random access memory cell. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: December 31, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Simon J. Lovett
  • Patent number: 10483970
    Abstract: Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kallol Mazumder, Myung-Ho Bae
  • Patent number: 10452319
    Abstract: A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Liang Chen
  • Patent number: 10446215
    Abstract: A system and method are provided for system for adaptive refresh of a memory device having multiple integrated circuit chips. A command generation portion generates commands for actuating a plurality of operational tasks on the memory device, including at least read, write, and refresh operations for selectively addressed storage cells of the memory device. A command management portion stores the commands and selects from the commands for timely execution of corresponding operational tasks on the memory device. A refresh management portion coupled to the command generation and command management portions actuates a plurality of refresh operations adaptively interleaved with other operational tasks, such that recursive refresh of the storage cells is carried out for the memory device within a predetermined refresh window of time. The refresh management portion selectively actuates each refresh operation for a chip-based selection of storage cells, whereby the storage cells of a selected chip are refreshed.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: October 15, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Anne Hughes, John MacLaren, Devika Raghu
  • Patent number: 10403381
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first electrode, a first magnetic layer, a first non-magnetic layer, a first conductive layer and a controller. The first magnetic member includes a first extending portion and a third magnetic portion. The first extending portion includes first and second magnetic portions. The third magnetic portion is connected with the second magnetic portion. The first electrode is electrically connected with the first magnetic portion. The first non-magnetic layer is provided between the first magnetic layer and at least a part of the third magnetic portion. The first conductive layer includes first and second conductive portions, and a third conductive portion being between the first conductive portion and the second conductive portion. The controller is electrically connected with the first electrode, the first magnetic layer, the first conductive portion and the second conductive portion.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: September 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Michael Arnaud Quinsat, Takuya Shimada, Susumu Hashimoto, Nobuyuki Umetsu, Yasuaki Ootera, Masaki Kado, Tsuyoshi Kondo, Shiho Nakamura, Tomoya Sanuki, Yoshihiro Ueda, Yuichi Ito, Shinji Miyano, Hideaki Aochi, Yasuhito Yoshimizu
  • Patent number: 10360952
    Abstract: Multiport memory architecture is disclosed herein. An example memory includes an input port, a memory array, and an output port. The input port is coupled to receive data blocks and includes first and second buffers coupled to temporarily store alternate data blocks, and the output port is coupled to provide data blocks from the memory array. The memory array is partitioned into first and second partitions, with the first partition coupled to receive data blocks from the first buffer and the second partition coupled to receive data blocks from the second buffer, and the input port and the memory array are coupled to receive control signals to simultaneously receive a first data block at the first buffer, transfer a second data block from the second buffer to a first address in the second partition, and provide a third data block stored at a third address of the first partition.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: July 23, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventors: Taehyung Jung, Jongsik Na, Sunny Ng
  • Patent number: 10242722
    Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: March 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Harish N. Venkata, Guy S. Perry
  • Patent number: 10243933
    Abstract: A data processing method and apparatus, where the method includes acquiring a first network data packet that is sent by a target application that runs in an untrusted execution domain, where the first network data packet includes a first identifier; acquiring, in a trusted execution domain, first data corresponding to the first identifier; generating, in the trusted execution domain, a second network data packet according to the first data and the first network data packet; performing, in the trusted execution domain, encryption on the second network data packet by using a first session key to acquire an encrypted second network data packet; and sending the encrypted second network data packet to the target server. The data processing method and apparatus in the embodiments of the present invention can effectively prevent an attacker from stealing data.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: March 26, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zhichao Hua, Yubin Xia, Haibo Chen
  • Patent number: 10185697
    Abstract: A memory device comprises an output buffer and a control circuit. The control circuit is configured to receive a system clock signal at an input of the control circuit. The control circuit is configured to generate a data transition signal based on the system clock signal. The control circuit is configured to provide the data transition signal to the output buffer of the memory device. The output buffer is configured to output memory data based on the data transition signal.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: January 22, 2019
    Assignee: Macronix International Co., Ltd.
    Inventors: Shang-Chi Yang, Su-Chueh Lo
  • Patent number: 10170166
    Abstract: The data transmission apparatus includes a prior stage shift register circuit and a plurality of rear stage shift register circuits. The prior stage shift register circuit is coupled to a sense amplifying device of the memory, receives sensed data from the sense amplifying device and outputs a plurality of the readout data in series by bitwise shifting out the sensed data according to a shift clock signal. The plurality of rear stage shift register circuits are coupled to the prior stage shift register circuit and respectively coupled to a plurality of pads. The plurality of rear stage shift register circuits respectively receive the readout data and respectively bitwise transport the readout data to the pads according to a clock signal. Wherein, a frequency of the shift clock signal is less than a frequency of the clock signal.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: January 1, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Oron Michael, Poongyeub Lee
  • Patent number: 10049707
    Abstract: The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments of the present disclosure include an apparatus comprising a shift register comprising an initial stage and a final stage. The shift register may be configured such that a clock signal may be initiated at the final stage of the shift register.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: August 14, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 10049724
    Abstract: An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a diode-connected device having a gate terminal coupled to the first supply node, and a source terminal coupled to second supply node; and a stack of devices coupled to the first supply node, wherein at least one device in the stack is coupled to the second supply node, and wherein the stack of devices is controllable according to an operation mode.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Amit Agarwal, Steven K. Hsu, Sri Harsha Choday
  • Patent number: 9972367
    Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: May 15, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Harish N. Venkata, Guy S. Perry
  • Patent number: 9952831
    Abstract: A circuit for transposing a matrix comprising reversal circuitry configured, for each of one or more diagonals of the matrix, to receive elements of the matrix in a first vector and generate a second vector that includes the elements of the matrix in an order that is a reverse of an order of the elements of the matrix in the first vector, and rotation circuitry configured, for each of the one or more diagonals of the matrix, to determine a number of positions by which to rotate the elements of the matrix in the second vector, receive the second vector of elements of the matrix, and generate a third vector that includes the elements of the matrix in the second vector in an order that is a rotation of the elements of the matrix in the second vector by the determined number of positions.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 24, 2018
    Inventors: Jonathan Ross, Robert David Nuckolls, Christopher Aaron Clark, Chester Li, Gregory Michael Thorson
  • Patent number: 9928205
    Abstract: A semiconductor apparatus may include a master chip, first to nth slave chips, first to nth slave chip ID generating units, and a master chip ID generating unit. The first to nth slave chip ID generating units are disposed respectively in the first to nth slave chips and connected in series to each other. Each of the first to nth slave chip ID generating units is configured to add a predetermined code value to an mth operation code to generate an (m+1)th operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: March 27, 2018
    Assignee: SK hynix Inc.
    Inventors: Dae Suk Kim, Jong Chern Lee, Sang Jin Byeon
  • Patent number: 9905308
    Abstract: An e-fuse device includes a transferring circuit, a detecting-and-outputting circuit, and a fusing circuit. The transferring circuit transfers an input signal to a data node. The detecting-and-outputting circuit generates an output signal according to the logic level of the data node. The fusing circuit includes an e-fuse cell, a first transistor, a second transistor, and a switch element. The e-fuse cell is coupled between a high-voltage node supplied with the high voltage or a ground and a first node. The first transistor is coupled between the first node and a second node and is controlled by the output signal. The second transistor is coupled between the second node and the ground and is controlled by a fusing signal. The switch element is coupled between the first node and the data node and is controlled by a switch signal.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: February 27, 2018
    Assignee: Winbond Electronics Corp.
    Inventor: Ying-Te Tu
  • Patent number: 9824743
    Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Bruce Querbach, Kuljit Bains, John Halbert
  • Patent number: 9823302
    Abstract: A semiconductor circuit has circuit units in a plurality of stages which units are continuously connected, each of the circuit units in the plurality of stages including: a first register; a second register; a first outputter; and a second outputter. The first outputter is connected to the first register and the second register, and selects and outputs one of a first input signal inputted from the first register and a second input signal inputted from the second register. The second outputter outputs at least one of the second input signal and a third input signal to a second register in a next stage, the third input signal being outputted from a logic circuit unit that performs logic operation on the basis of an input signal containing at least one of a signals outputted from the first outputters.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: November 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Jun Hasegawa
  • Patent number: 9773556
    Abstract: Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: September 26, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Boon Bing Ng, Hang Ru Goy
  • Patent number: 9767873
    Abstract: A semiconductor device of the inventive concept includes a timing circuit configured to receive a first timing signal of a first pulse width from an external device and output a second timing signal having a pulse width which is gradually being reduced from a second pulse width longer than the pulse width of the first timing signal, and a data input/output circuit receiving the second timing signal and outputting data to the external device in synchronization with the second timing signal.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seonkyoo Lee, Taesung Lee, Jeongdon Ihm, Byunghoon Jeong
  • Patent number: 9761300
    Abstract: The present disclosure includes data shift apparatuses and methods. An example apparatus includes a memory device. The example memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. A first shared input/output (I/O) line is configured to selectably couple a first subset of the plurality of sense lines and a second shared I/O line is configured to selectably couple a second subset of the plurality of sense lines. A shift element is configured to selectably couple the first shared I/O line to the second shared I/O line to enable a data shift operation. A controller is configured to direct selectable coupling of the array, the sensing circuitry, and the shift element to enable a shift of a data value from the first shared I/O line to the second shared I/O line.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: September 12, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Jeremiah J. Willcock
  • Patent number: 9734890
    Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: August 15, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Farrukh Aquil, Michael Drop, Vaishnav Srinivas, Philip Clovis
  • Patent number: 9734878
    Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: August 15, 2017
    Inventors: Farrukh Aquil, Michael Drop, Vaishnav Srinivas, Philip Clovis
  • Patent number: 9727267
    Abstract: In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventors: Donia Sebastian, Simon D. Ramage, Curtis A. Gittens, Scott Nelson, David B. Carlton, Kai-Uwe Schmidt
  • Patent number: 9674153
    Abstract: A secure data processing apparatus and method are disclosed. The secure data processing apparatus is operable to securely process user data provided by a user and includes a trusted domain having a trusted bus; a trusted domain controller coupling the trusted bus with an untrusted bus of an untrusted domain, the trusted domain controller being operable to ensure that encrypted incoming user data received over the untrusted bus is decrypted and provided over the trusted bus as the incoming user data and to ensure that outgoing user data is encrypted and provided over the untrusted bus as encrypted outgoing data. The trusted domain controller that only encrypted data is provided in the untrusted domain reducing the chance of the data being compromised. The trusted domain controller ensures that access to the unencrypted data within the trusted domain can be avoided. Confidentiality of the data can be assured without performance shortfalls.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: June 6, 2017
    Assignee: Alcatel Lucent
    Inventors: Tommaso Cucinotta, Davide Cherubini, Eric B. Jul
  • Patent number: 9660648
    Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: May 23, 2017
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 9659626
    Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Bruce Querbach, Kuljit S. Bains, John B. Halbert
  • Patent number: 9653141
    Abstract: A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Yun Kim, Jong-Pil Son, Su-A Kim, Chul-Woo Park, Hong-Sun Hwang
  • Patent number: 9653140
    Abstract: A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: May 16, 2017
    Assignee: SK hynix Inc.
    Inventors: Chang Hyun Kim, Min Chang Kim, Do Yun Lee, Yong Woo Lee, Jae Jin Lee, Hun Sam Jung, Hoe Kwon Jung