Abstract: A nonvolatile memory device includes a nonvolatile memory array including a plurality of charge retaining transistors arranged in rows and columns. The device has a plurality source lines formed in parallel with the bit lines associated with each column. Row decode/driver circuits are connected to blocks of the charge retaining transistors for controlling the application of the necessary read, program, and erase signals. Erase count registers, each of the erase count registers associated with one block of the array of the charge retaining transistors for storing an erase count for the associated block for determining whether a refresh operation is to be executed. Groupings on each column of the array of charge retaining transistors are connected as NAND series strings where each NAND string has a select gating charge retaining transistor connected to the top charge retaining transistor for connecting the NAND series string to the bit lines.

Abstract: A semiconductor integrated circuit device includes a first block, a second block, and a control section. The first block includes a first fuse, a first switching configured to write data to the first fuse, a first holding portion capable of holding a first instruction, and a first instruction portion configured to turn on the first switching when a second instruction is given thereto with the first instruction. The second block includes a second fuse, a second switching configured to write data to the second fuse, a second holding portion capable of holding the first instruction, and a second instruction portion configured to turn on the second switching when the second instruction is given thereto with the first instruction. The control section issues the second instruction at a point in time when the first instruction is held in the first and second holding portions.

Abstract: A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift dock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register.

Abstract: A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: According to one embodiment, a shift register memory device includes a shift register, a program/read element, and a rotating force application unit. The shift register includes a plurality of rotors arranged along one direction and provided with a uniaxial anisotropy. Each of the plurality of rotors has a characteristic direction rotatable around a rotational axis extending in the one direction. The program/read element is configured to program data to the shift register by causing the characteristic direction of one of the rotors to match one selected from two directions conforming to the uniaxial anisotropy and configured to read the data by detecting the characteristic direction. The rotating force application unit is configured to apply a rotating force to the shift register to urge the characteristic direction to rotate. The plurality of rotors are organized into a plurality of pairs of every two mutually adjacent rotors.

Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

Abstract: A circuit for controlling the read cycle includes plurality of shift stages configured to sequentially shift read signals; and an activating unit configured to activate a read cycle signal which represents a read cycle, by performing logical operation for output signals of the plurality of the shift stages, wherein the plurality of the shift stages are configured to sequentially shift the read signals for a period corresponding to burst setting information.

Abstract: A semiconductor memory device is capable of controlling an address and data mask information through the use of a common part, thereby reducing chip size. The semiconductor memory device for receiving the addresses and data mask information via a common pin includes a buffer unit and a shift register unit. The buffer unit receives the addresses and data mask information. The shift register unit is comprised of a plurality of latch stages connected in series, for sequentially latching the addresses and data mask information being inputted in series, and an address output unit and a data mask information output unit for outputting information from different latch stages.

Abstract: A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command.

Abstract: A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronized with each other.

Abstract: Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the clock signals. A write latch enable block may be used to develop a write latch enable signal for issuance along with a corresponding address signal. The write latch enable signal can be timed such that it arrives at an appropriate time to issue the data corresponding to the issued address.

Abstract: A primary-side regulation (PSR) controller integrated circuit includes a PSR CC/CV controller and a non-volatile shift register. An assembled power supply that includes the integrated circuit is in-circuit tested to determine errors in power supply output voltage and/or current. Programming information is determined and shifted into the shift register. During programming, the power supply regulates to a different output voltage, and the different voltage is used for shift register programming. After programming, the power supply operates in a normal mode so that the output voltage and current are within specification. The voltage and current to which the power supply regulates are set by some of the bits of the programming information.

Abstract: A pipe latch circuit includes a division unit configured to output a division signal, a multiplexing unit configured to multiplex a plurality of source signals according to periods determined by the division signal and generate a plurality of pipe input control signals, and a pipe latch unit configured to sequentially latch a plurality of data signals in response to the pipe input control signals, wherein the source signals are sequentially activated in response to an input/output (I/O) strobe signal.

Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.

Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.

Abstract: The disclosed invention provides a structure and method for increasing the operating speed and reduce the overall programming time of a memory array. In one embodiment, the method and structure provided herein reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). Specifically, the write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit. This interleaving of data bit write windows allows a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) reducing overall memory write time.

Abstract: Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an initial delay value within a delay lock loop. This delay value is then changed until a preferred delay value, resulting in synchronization, is found. In various embodiments, used of the initial delay value increases the speed, reliability or other beneficial features of the synchronization.

Abstract: The present invention provides a circuit for controlling a column-command address corresponding to a specific column of a DRAM array. The circuit includes a control unit and a FIFO register. The control unit determines a period number, and synchronously produces an input pointer and an output pointer, wherein the output pointer is lagged behind the input pointer by the period number. The FIFO register utilizes the input pointer to store the column-command address, and utilizes the output pointer to output the column-command address.

Abstract: A precharge voltage supplying circuit comprises a control signal generating unit for generating a first control signal in response to a power-up signal and a clock enable signal, and a precharge voltage control unit having a bleeder circuit and driving the bleeder circuit in response to the first control signal to control a precharge voltage. The precharge voltage supplying circuit can be widely used in various devices which need the generation of a voltage, a level of which is adjustable according to a PVT characteristic change, and a range of change of which is not so large.

Abstract: An active memory element is provided. A bipolar memory two-terminal element includes polarity-dependent switching. A probability of switching of the bi-polar memory element between a first state and a second state decays exponentially based on time delay and a difference between received signals at the two terminals and a switching threshold magnitude.

Abstract: An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal.

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. To control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed.

Abstract: An apparatus for controlling an operation timing in a semiconductor memory device, comprising: a shift information generator configured to generate shift information based on data path delay information and latency information; and a shift register configured to shift a command based on the shift information and produce a shifted command to control an operation timing.

Abstract: A variable reference voltage circuit for performing memory operation on non-volatile memory includes a multi-level voltage source and a selector circuit. The multi-level voltage source generates multiple voltages. The selector circuit includes a selector input and a selector output. The selector input is coupled to the multi-level voltage source to selectively couple any of the multiple voltages to the selector output. The selector output of the selector circuit is coupled to a non-volatile memory array to provide the NV memory array with a selectable program voltage for programming the NV memory array and a selectable erase voltage for erasing the NV memory array.

Abstract: A level shifter includes a level shifter module that receives a first input signal having high and low states and at least one voltage supply signal, and that generates a latch control signal based on the high and low states of the first input signal. A latch module receives the latch control signal, a data input signal, and the at least one voltage supply signal. The latch module selectively stores data associated with the data input signal based on the latch control signal. The latch module selectively changes the at least one voltage supply signal from a first level to a second level and outputs the data according to the second level based on the latch control signal.

Abstract: A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write data conversion circuit generates write data from bit data input from the same data input/output terminal in a set of a plurality of data of j bits input at different timings.

Abstract: An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements.

Abstract: Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous path. In another embodiment, the initiation of the bank address signals may be provided asynchronously to the assertion of the Write-with-Autoprecharge signal.

Abstract: In one embodiment of the invention, an integrated circuit such as a programmable logic device includes volatile memory, nonvolatile memory, and a data shift register for reading data from the nonvolatile memory and for reading data from and writing data to the volatile memory. A built in self test (BIST) circuit is operable to test the nonvolatile memory without the data shift register reading data from the nonvolatile memory. The BIST circuit may include a finite state machine for performing at least one of the following tests on the nonvolatile memory: bulk erase, bulk program; margin bulk program; and/or margin bulk erase. A memory controller responsive to the finite state machine is operable to write data to and read data from the nonvolatile memory during testing of the nonvolatile memory.

Abstract: An apparatus for adjustment of a digital delay function of a data memory unit comprising said data memory unit (102), an elastic store register, ESR, (104) and read clock and write clock adapted to control read and write operations, a write counter associated with the write clock and a read counter associated with the read clock. Said memory (102) works in series with said ESR (104). The memory (102) delivers two data elements from two logically neighbouring cells. Said ESR (104) writes the two data elements from the memory (102) at every cycle of the write clock, wherein if the write counter is increased by one at a cycle of the write clock the output position in the memory (102) is not changed, and if the write counter is increased by two at one cycle of the write clock the output position in the memory (102) is moved backward by one data element and if the write counter is not changed at one cycle of the write clock the output position in the memory (102) is moved forward by one data element.

Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the plurality of multiple bit information storing memory cells, and a controller configured to control an access operation to access at least one multiple bit information storing memory cell using the buffer circuit coupled to the at least one multiple bit information storing memory cell to be accessed, and a buffer circuit of at least one other multiple bit information storing memory cell being coupled to at least one other multiple bit information storing memory cell.

Abstract: Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

Abstract: A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift dock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register.

Abstract: An integrated circuit and a method for transferring data is provided. One embodiment provides a method for transferring data in an integrated circuit. The method includes driving a first line in accordance with data to be transferred. The data is transmitted from the first line to a second line based on a capacitive coupling.

Abstract: In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.

Abstract: According to one embodiment, a method of reading data in a semiconductor memory device including a plurality of memory cells associated with rows and columns and a plurality of latch circuits associated with the columns includes reading flag data from the memory cells associated with one of the columns into associated one of the latch circuits, selecting one of the latch circuits sequentially, while shifting one of the latch circuits to be selected, and reading the flag data from one of the latch circuits selected in an Nth one of the shifts. N is an integer not less than 0).

Abstract: A semiconductor memory device includes a thermosensor that senses present temperatures of the device and confirms whether the temperature values are valid. The thermosensor includes a temperature sensing unit, a storage unit and an initializing unit. The temperature sensing unit senses temperatures in response to a driving signal. The storage unit stores output signals of the temperature sensing unit and outputs temperature values. The initializing unit initializes the storage unit after a predetermined time from an activation of the driving signal. A driving method includes driving the thermosensor in response to the driving signal, requesting a re-driving after a predetermined time from the activation of the driving signal, and re-driving the thermosensor in response to the driving signal input again.

Abstract: Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count pointer associated with a present queue to read (write) flag logic, (3) adjusting the read (write) count pointer associated with the present queue in response to each read (write) operation performed by the present queue, (4) indicating a read (write) queue switch from the present queue to a next queue, (5) retrieving a read (write) count pointer associated with the next queue; and then (6) simultaneously providing the read (write) count pointer associated with the present queue and the read (write) count pointer associated with the next queue to the read (write) flag logic.

Abstract: A circuit block access module (ICAM) residing on an integrated circuit and adapted to access a circuit block on the integrated circuit, the module comprising control logic adapted to extract data from a serial data line into two or more parallel data lines, wherein at least one of the parallel data lines is associated with a circuit block address line; and the control logic is further adapted to override or bypass at least a portion of a primary control circuit of said integrated circuit.

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. to control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed.

Abstract: A memory circuit includes a memory cell, a pair of conducting lines operable to signal the logic state of the memory cell and read circuitry operable to perform a read operation by detecting a voltage level of at least one of the pair of conducting lines. The memory circuit includes a pull-down circuit having an on configuration in which it is operable to pull-down a voltage level of at least one of the pair of conducting lines so as to affect the read operation and an off-configuration in which the pull-down circuit cannot affect the read operation. Control circuitry is configured to control whether the pull-down circuit is in the on configuration or the off configuration. The memory circuit can be incorporated in a data processing apparatus and a method of operating a memory circuit is provided in which a pull-down circuit is controlled to be in an on configuration or in an off configuration.

Abstract: A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.

Abstract: Test circuitry for determining whether a memory can operate at a lower operating voltage. The test circuitry includes a sense circuit having a delayed sensing characteristic as compared to other sense amplifier circuits of the memory. With this circuitry, the test circuitry can determine if the sense circuit can provide valid data under more severe sensing conditions. In one example, the sense circuit includes a delay circuit in the sense enable signal path. If sense circuit can provide data at more server operating conditions, then the memory operating voltage can be lowered.

Abstract: A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register.

Abstract: A semiconductor memory device comprises a first exclusive-OR circuit which compares mth N-bit first data with (m+1)th N-bit second data, a majority circuit which generates flag data to invert the second data if a comparison result of the first exclusive-OR circuit indicates that the number of mismatch bits between the first data and the second data is not less than N/2, and generates flag data to noninvert the second data if the number of mismatch bits between the first data and the second data is less than N/2, a second exclusive-OR circuit which inverts or noninverts the second data based on the flag data, a shift register which stores the flag data generated by the majority circuit, and a pad to serially output both the inverted or noninverted second data and the flag data.