Abstract: Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to determine that a block of the blocks is an open block based on an open block information, and in response to the block of the blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.

Abstract: A disturb mitigation scheme is described for a 1TnC or multi-element ferroelectric gain bit-cell where after writing to a selected capacitor of the bit-cell, a cure phase is initiated. Between the cure phase and the write phase, there may be zero or more cycles where the selected word-line, bit-line, and plate-lines are pulled-down to ground. The cure phase may occur immediately before the write phase. In the cure phase, the word-line is asserted again just like in the write phase. In the cure phase, the voltage on bit-line is inverted compared to the voltage on the bit-line in the write phase. By programming a value in a selected capacitor to be opposite of the value written in the write phase of that selected capacitor, time accumulation of disturb is negated. This allows to substantially zero out disturb field on the unselected capacitors of the same bit-cell and/or other unselected bit-cells.

Abstract: A pipe register control signal generation circuit includes a sense amplifier configured to drive a global input/output line according to a result of sensing a voltage difference between a pair of local input/output lines according to a sense amplifier enable signal. The pipe register control signal generation circuit also includes a duplicate sense amplifier configured to simulate the sense amplifier and configured to generate a pipe register control signal according to a result of sensing a difference between a first voltage and a second voltage according to the sense amplifier enable signal.

Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: A power device includes a packaged semiconductor switch containing first and second series-connected insulated-gate transistors, first and second control terminals electrically connected to the first and second insulated-gate transistors, respectively, first and second current carrying terminals electrically connected to the first and second insulated-gate transistors, respectively, and a voltage-monitoring terminal electrically connected to an internal node shared by first and second current carrying regions within the first and second insulated-gate transistors, respectively. The first and second control terminals can be electrically connected to a gate of the first insulated-gate transistor and a gate of the second insulated-gate transistor, respectively; and the first and second current carrying terminals can be electrically connected to a source of the first insulated-gate transistor and a drain (or collector) of the second insulated-gate transistor.

Abstract: An in-memory computing method and apparatus, adapted for a processor to perform MAC operations on a memory, are provided. In the method, a format of binary data of weights is transformed from a floating-point format into a quantized format by truncating at least a portion of fraction bits of the binary data and calculating complements of remaining bits, and programming the transformed binary data into cells of the memory. A tuning procedure is performed by iteratively inputting binary data of input signals into the memory, integrating outputs of the memory, and adjusting the weights programmed to the cells based on the integrated outputs. The binary data of the weights is reshaped based on a probability of reducing bits with a value of one in the binary data of each weight. The tuning procedure is repeated until an end condition is met.

Abstract: A circuit includes a delay generation circuit. The delay generation circuit is configured to generate a sub-grab signal for each of the storage areas based on an initial grab signal and data transmission delay of each of the storage areas, and generate a grab enable signal based on all the sub-grab signals. A time interval between a time when the read-write control circuit receives data transmitted from each of the storage areas by a global data line and a time when the read-write control circuit receives the sub-grab signal corresponding to the storage area satisfies a preset range. The read-write control circuit is configured to read out data of the global data line to a data bus based on the grab enable signal. Therefore, the tCCD of the DRAM is optimized.

Abstract: The memory device includes a plurality of dies, and each die includes a plurality of blocks with a plurality of word lines. Some of the word lines are arranged in a plurality of exclusive OR (XOR) sets with each XOR set containing word lines in the same positions across the plurality of dies. The memory device further includes a controller that is configured to program the word lines of the blocks of at least one of the dies in a first programming direction. The controller is further configured to program the word lines of the blocks of at least one other die in a second programming direction that is opposite of the first programming direction.

Abstract: A nonvolatile memory device includes a plurality of memory cells that have a first state and a second state different from each other. A method of searching a read voltage of the nonvolatile memory device includes determining a number n that represents a number of times a data read operation is performed, selecting n read voltage levels of the read voltage such that a number of read voltage levels is equal to the number of times the data read operation, where the n read voltage levels differ from each other, generating n cell count values by performing n data read operations on the plurality of memory cells using all of the n read voltage levels, and generating an optimal read voltage level of the read voltage by performing a regression analysis based on a first-order polynomial using the n read voltage levels and the n cell count values.

Abstract: Methods, systems, and devices for sensing a memory with shared sense components are described. A device may activate a word line and a plate line each coupled with a set of memory cells, where each memory cell of the set of memory cells is coupled with a respective digit line of a set of digit lines. The device may activate a set of switching components to couple each digit line of the set of digit lines with a respective sense component of a set of sense components, where each switching component of the set of switching components is coupled with a respective memory cell of the set of memory cells. The device may sense the set of memory cells based on activating the word line and the plate line and based on coupling the set of digit lines with the set of sense components.

Abstract: Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to, in response to a block of the plurality of blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.

Abstract: Apparatuses, systems, and methods for read clock timing alignment in a stacked memory. An interface die provides a read clock to a core die. The core die includes a serializer which generates data with timing based on the read clock and an adjustable delay circuit which provides a delayed read clock back to the interface die. The interface die outputs the data with timing based on the delayed read clock received from the core die. In this way, the read clock passes along a return clock path from the interface die, through a delay circuit of the core die and back to the interface die before controlling data output timing. Each core die may adjust the timing of the delay of the read clock in order to better align the read clock with the timing of data provided from that die.

Abstract: Memory might include a controller configured to determine, for each sense circuit of a plurality of sense circuits, a respective plurality of first logic levels for that sense circuit while capacitively coupling a respective plurality of voltage levels to its respective sense node, to determine a particular voltage level in response to each respective plurality of first logic levels for the plurality of sense circuits and their respective plurality of voltage levels, and to determine, for each sense circuit of the plurality of sense circuits, a respective second logic level for that sense circuit while capacitively coupling the particular voltage level to its respective sense node.

Abstract: The present disclosure includes apparatuses, methods, and systems for predicting and compensating for degradation of memory cells. An embodiment includes a memory having a group of memory cells, and circuitry configured to, upon a quantity of sense operations performed on the group of memory cells meeting or exceeding a threshold quantity, perform a sense operation on the group of memory cells using a positive sensing voltage and perform a sense operation on the group of memory cells using a negative sensing voltage, and perform an operation to program the memory cells of the group determined to be in a reset data state by both of the sense operations to the reset data state.

Abstract: The disclosure relates to a low-loss arithmetic circuit, which includes a plurality of arithmetic units, a plurality of storage units, and one or more reset MOSFETs. Each arithmetic unit includes 4 MOSFETs. The disclosure also relates to an operating method of the low-loss arithmetic circuit and a low-loss Processing-in-Memory circuit.

Abstract: Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a data storage element; and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the data storage element. A delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The delay-sensing element is configured to sense a timing delay between a first signal on the active current path and a second signal on the reference current path. The delay-sensing element is further configured to determine a data state stored in the data storage element based on the timing delay.

Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

Abstract: A method for finding an optimum read voltage includes acquiring difference values between state bit counts of different positions. A direction for finding the optimum read voltage is determined based on the difference values. An offset for finding the optimum read voltage is determined based on correspondence between a difference value of bit count and offset. Reading is performed with the offset applied to a current read reference voltage, wherein upon read-success, the current reference voltage superimposed with the offset is the optimum read voltage, and upon read-error, new first and second positions are obtained based on the direction and the offset for finding the optimum read voltage until reading becomes successful.

Abstract: Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.

Abstract: The present disclosure relates to a method for accessing an array of memory cells, including storing a set of user data in a plurality of memory cells, storing, in a portion of the array, additional information representative of a voltage difference between a first threshold voltage and a second threshold voltage of the memory cells programmed to a first logic state, applying to the array a read voltage to activate a first group of memory cells corresponding to a preset number of memory cells, determining that the first group of memory cells has been activated based on applying the read voltage, wherein the read voltage is equal to the first threshold voltage when the first group of memory cells has been activated, and based on the additional data information, applying the voltage difference to the array to activate a second group of memory cells programmed to the first logic state.

Abstract: A memory device includes a first nonvolatile memory including a resistive memory cell; and a controller. The controller may be configured to provide the first nonvolatile memory with a first data, a first program command, and a first address. The controller may be configured to receive a second data, which is a verify read from the resistive memory cell programmed with the first data, from the first nonvolatile memory in response to the first program command. The controller may be configured to compare the first data with the second data to detect a number of fail cells. When the number of detected fail cells is greater than a reference value, the controller may be configured to generate a third data obtained by inversing the first data, and provide the third data to the first nonvolatile memory. The first data may include an inversion flag bit.

Abstract: A request to perform a read operation on a memory device is received. The memory device includes a first group of memory cells. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The read operation is performed by obtaining a first read signal for a first memory cell and a second read signal for a second memory cell of the first group of memory cells. A first rule logic is applied to the first read signal to generate a first updated signal and a second rule logic is applied to the second read signal to generate a second updated signal. Logic functions are applied to the first and second updated signals to generate an output signal indicating the first sequence of bits stored by the first group of memory cells.

Abstract: A computation apparatus includes a plurality of memory cells and a plurality of sense amplifiers, in which each of the memory cells includes a memory circuit and a calculation circuit. The memory circuits of the memory cells are configured to receive input values from a plurality of word lines, generate a computation result based on the input values and output the computation result to a bit line. The calculation circuits of the memory cells are configured to receive calculation input values from a plurality of calculation word lines, generate calculation output values based on the calculation input values, and output the calculation output values to a plurality of calculation bit lines. The sense amplifiers are configured to sense the calculation output values from the calculation bit lines to generate sensed values, wherein a value of the computation result is determined based on the sensed values and the calculation output values.

Abstract: Methods, systems, and devices for dynamic read voltage techniques are described. In some examples, a memory device may include one or more partitions made up of multiple disjoint subsets of memory arrays. The memory device may receive a read command to read the one or more partitions and enter a drift determination phase. During the drift determination phase, the memory device may concurrently apply a respective voltage of a set of voltages to each disjoint subset and determine a quantity of memory cells in each disjoint subset that have a threshold voltage below the applied voltage. Based on a comparison between the determined quantity of memory cells and a predetermined quantity of memory cells, the memory device may select a voltage from the set of voltages and utilize the selected voltage to read the one or more partitions.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: Systems and methods are provided that provide protection from undesired latching that may be caused by indeterminate interamble periods in an input/output data strobe (DQS) signal. Interamble compensation circuitry selectively filters out interamble states of the DQS signal to reduce provision of interamble signals to downstream components that use the DQS signal to identify data latching times.

Abstract: A semiconductor device that can compensate for threshold fluctuations in memory cells using capacitive coupling. The flash memory includes a NAND-type memory cell array, a programing device, a reading device, and an offset voltage determining unit. The programing device programs the memory cells connected to a selected word line. The reading device reads the memory cells connected to a selected word line. The programing device programs the memory cells of a monitoring NAND string simultaneously when programing a word line. The reading device comprises a current detecting unit applying a read voltage to an unselected word line n+1, and detecting the current of the monitoring NAND string. The offset voltage determining unit determines the first and second offset voltage based on the detected current, and a reading pass voltage is applied to the unselected word line, a read voltage is applied to the selected word line.

Abstract: The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.

Abstract: A memory device includes an input/output circuit configured to receive a status read command from a memory controller, a toggle counter configured to count a number of toggles of a signal received from the memory controller, and a status register configured to store status information of the memory device and configured to output the status information to the input/output circuit. The memory device also includes a status output controller configured to determine whether the number of toggles counted by the toggle counter corresponds to a reference number of toggles and configured to control the status register to transmit the status information to the memory controller through the input/output circuit, in response to the status read command.

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

Abstract: A method is provided for determining log-likelihood ratio (LLR) for soft decoding based on information obtained from hard decoding, in a storage system configured to perform hard decoding and soft decoding of low-density parity-check (LDPC) codewords. The method includes performing hard decoding of codewords in a page, the hard decoding including a first hard read and one or more re-reads using predetermined hard read threshold voltages, and grouping memory cells in the page into a plurality of bins based on the read threshold voltages for the first hard read and the one or more re-reads. The method also includes computing parity checksum and one's count for memory cells in each bin, and determining LLR for each bin of memory cells based on read data, checksums, and one's count for each bin.

Abstract: Non-volatile memory structures are presented for a content addressable memory (CAM) that can perform in-memory search operations for both ternary and binary valued key values. Each ternary or binary valued key bit is stored in a pair of memory cells along a bit line of a NAND memory array, with the stored keys searched by applying each ternary or binary valued bit of an input key as voltage levels on a pair of word lines. The system is highly scalable. The system can also be used to perform nearest neighbor searches between stored vectors and an input vector to find stored vectors withing a specified Hamming distance of the input vector.

Abstract: Disclosed is a memory structure including an array of memory cells and a read circuit. The read circuit includes two registers configured to capture and store two different digital-to-analog converter (DAC) codes, which correspond to two different reference currents that approximate two different output currents generated on a bitline during consecutive single-ended current sensing processes directed to the same selected memory cell but using different input voltages. Optionally, the read circuit can also include a current-voltage (I-V) slope calculator, which uses the two different DAC codes to calculate an I-V slope characteristic of the selected memory cell, and a bit generator, which performs a comparison of the I-V slope characteristic and a reference I-V slope characteristic and based on results of the comparison, generates and outputs a bit with a logic value that represents the data storage state of the selected memory cell. Also disclosed is an associated method.

Abstract: Apparatuses and techniques are described for recovering from errors in a read operation. When a read operation results in an uncorrectable read error, recovery read operations are performed for each read voltage of a page of data. Each recovery read operation uses a different timing. The different timings can involve a time period which is allocated for a voltage transition, such as a settling time of a word line or bit line voltage, or a time allocated for an under kick or over kick of a word line or bit line voltage. An error count is obtained for each different timing, and an optimum timing is determined based on the lowest error count. A retry read operation is performed in which an optimum timing is used for the voltage transition for each read voltage of the page.

Abstract: A delay circuit of a delay-locked loop (DLL) circuit includes: a phase splitter configured to split a phase of a reference clock signal to output a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees; a logic gate configured to delay the second reference clock signal to output a delayed reference clock signal; and a delay line circuit including a plurality of delay cells that are cascade-connected, the delay line circuit configured to delay the first reference clock signal and the delayed reference clock signal based on a control code set, and to output a first delayed clock signal and a second delayed clock signal having a delay amount corresponding to a delay of one logic gate included in the plurality of delay cells.

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

Abstract: A delay locked loop circuit and a semiconductor memory device are provided. The delay locked loop circuit includes a phase detection and delay control circuit configured to detect a phase difference between a first internally generated clock signal the feedback clock signal to generate a first phase difference detection signal in response to a first selection signal being activated, to detect a phase difference between a second internally generated clock signal and the feedback clock signal to generate a second phase difference detection signal in response to a second selection signal being activated, and to change a code value in response to the first phase difference detection signal or the second phase difference detection signal.

Abstract: A circuit includes a bit line, a pass gate coupled between the bit line and a power node having a first power voltage level, and a driver coupled between the bit line and a reference node having a reference voltage level. The pass gate couples the bit line to the power node when the first signal has the reference voltage level and decouples the bit line from the power node when the first signal has the first power voltage level. The driver receives a second signal based on a control signal, couples the bit line to the reference node when the second signal has a second power voltage level below the first power voltage level, and decouples the bit line from the reference node when the second signal has the reference voltage level. An input circuit generates the first signal independent of the control signal.

Abstract: A memory system may include a memory device and a memory controller. The memory device may include memory cells. The memory controller may estimate and use an read voltage to distinguish one or more memory cells corresponding to a first threshold voltage distribution from one or more memory cells corresponding to a second threshold voltage distribution, the read voltage being estimated based on standard deviations and average threshold voltages of the first and the second threshold voltage distributions and probability density functions corresponding to the first and the second threshold voltage distributions, respectively. The memory controller may be structured and operable to calculate the standard deviation of the first threshold voltage distribution, based on a first probability area distinguished by a first target read voltage, a second probability area distinguished by a second target read voltage, and inverse Q-function values corresponding to the first and the second probability areas.

Abstract: A data driving circuit may include a trigger circuit and a pre-driver. The trigger circuit may be configured to block a remaining signal path among a plurality of signal paths for transmitting data except for a signal path corresponding to a currently selected driving strength. The pre-driver may be configured to drive data, which are transmitted through the signal path corresponding to the currently selected driving strength, using an impedance determined in accordance with a plurality of impedance control codes.

Abstract: A processing device in a memory system incrementally adjusts a center read voltage for a first block of a memory device by a first offset amount to generate an adjusted read voltage and causes the adjusted read voltage to be applied to the first block to determine an adjusted bit count associated with the adjusted read voltage. The processing device further determines whether a difference between the adjusted bit count and a previous bit count associated with a previous read voltage satisfies a first threshold criterion pertaining to an error threshold, and responsive to the difference between the adjusted bit count and the previous bit count not satisfying the first threshold criterion, determines a read window for the first block based on the previous read voltage.

Abstract: A semiconductor memory device includes a memory cell region; a memory mat end region; a memory mat including the memory cell region and the memory mat region; a plurality of first silicon regions arranged in the memory cell region; a second silicon region arranged in the memory mat end region; a first conductive layer provided in the memory cell region and the memory mat end region; and wherein upper surface position of the second silicon region in the memory mat end region is higher than the upper surface position of the first silicon region in the memory cell region; and wherein the upper surface position of the first conductive layer in the memory mat end region is higher than the upper surface position of the first conductive layer in the memory cell region.

Abstract: Read operations can be performed to read data stored at a data block. Parameters reflective of a separation between a pair of programming distributions associated with the data block can be determined based on the plurality of read operations. A read request to read the data stored at the data block can be received. In response to receiving the read request, a read operation can be performed to read the data stored at the data block based on the parameters that are reflective of the separation between the pair of programming distributions associated with the data block.

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

Abstract: A method of denoising intrinsic sneak currents in a PRAM memory array of M wordlines and N bitlines includes receiving, by the PRAM memory array, an input read address; and selecting from a table of wordline distances from a sense-amplifier versus estimated optimal currents for those wordline distances an estimated optimal reference current for a distance closest to the received input read address. The reference current determines whether a read current is ‘0’ or ‘1’ and minimizes a bit error rate due to effects of sneak paths and parasitic elements that distorts the read current.

Abstract: A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a pair of global read bitlines, a local group read port arranged between the pair of local bitlines and the pair of global read bitlines for selectively accessing one of the local bitlines depending on a state of a selected bitcell, and a local group precharge circuit operatively arranged between the pair of local bitlines.

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.

Abstract: Described are mechanisms and methods for amortizing the cost of address decode, row-decode and wordline firing across multiple read accesses (instead of just on one read access). Some or all memory locations that share a wordline (WL) may be read, by walking through column multiplexor addresses (instead of just reading out one column multiplexor address per WL fire or memory access). The mechanisms and methods disclosed herein may advantageously enable N distinct memory words to be read out if the array uses an N-to-1 column multiplexor. Since memories such as embedded DRAMs (eDRAMs) may undergo a destructive read, for a given WL fire, a design may be disposed to sense N distinct memory words and restore them in order.

Abstract: A method of performing a write operation on a static random access memory (SRAM) bit cell includes activating the bit cell by supplying a signal to a p-type pass gate of the bit cell, the signal causing the p-type pass gate to be in a conductive state, using a p-type transistor of a write multiplexer to maintain a data line at a logically high voltage, and transferring bit information from the data line to the activated bit cell using the p-type pass gate.