Particular Read Circuit Patents (Class 365/189.15)
  • Patent number: 10090027
    Abstract: A memory system includes a first memory bank, a first path selector, a second memory bank, a second path selector, and a sensing device. The first memory bank includes a plurality of first memory cells. The second memory bank includes a plurality of second memory cells. The first path selector includes a plurality of input terminals coupled to the first memory cells through a plurality of first bit lines, and two output terminals. The second path selector includes a plurality of input terminals coupled to the second memory cells through a plurality of second bit lines, and two output terminals. The sensing device is coupled to the output terminals of the first bank selector and the second bank selector, and senses the difference between currents outputted from two of the reference current source, and the terminals of the two bank selectors according to the required operations.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 2, 2018
    Assignee: eMemory Technology Inc.
    Inventor: Po-Ching Wu
  • Patent number: 10082823
    Abstract: An apparatus comprising an open loop circuit and a delay circuit. The open loop circuit may be configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal. The delay circuit may be configured to (i) generate the delayed version of the strobe signal in response to (a) the strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit and (ii) adjust a delay of transferring a data signal through the apparatus in response to (a) the delay amount and (b) the in-phase clock signal. The data signal may be received from the memory interface. The delay of transferring the data signal may be implemented to keep a latency of a data transfer within a pre-defined range.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: September 25, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: David Chang, Xudong Shi
  • Patent number: 10078456
    Abstract: Techniques are disclosed relating to resolving memory access hazards. In one embodiment, an apparatus includes a memory and circuitry coupled to or comprised in the memory. In this embodiment, the circuitry is configured to receive a sequence of memory access requests for the memory, where the sequence of memory access requests is configured to access locations associated with entries in a matrix. In this embodiment, the circuitry is configured with memory access constraints for the sequence of memory access requests. In this embodiment, the circuitry is configured to grant the sequence of memory access requests subject to the memory access constraints, thereby avoiding memory access hazards for a sequence of memory accesses corresponding to the sequence of memory access requests.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: September 18, 2018
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventors: Tai A. Ly, Swapnil D. Mhaske, Hojin Kee, Adam T. Arnesen, David C. Uliana, Newton G. Petersen
  • Patent number: 10079045
    Abstract: A sense amplifier may be provided. The sense amplifier may include an amplification circuit and/or a cell current control circuit. The amplification circuit may be configured to compare a voltage level of a signal line with a level of a read voltage. The cell current control circuit may be configured to decrease the voltage level of the signal line based on an output signal.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: September 18, 2018
    Assignee: SK hynix Inc.
    Inventor: Seok Joon Kang
  • Patent number: 10073833
    Abstract: Large lists of domain-specific terms are classified as a particular kind of linguistic object, e.g., lexical answer type T versus canonical answer E, based on features from a domain-specific corpus which have been found to distinguish between the linguistic objects. The distinguishing features can be identified in the corpus based on sets of the linguistic objects derived from question-and-answer pairs. A classifier can be trained using the distinguishing features, and the classification carried out using that classifier. The distinguishing features can include one or more syntactic features or one or more lexical features. The linguistic objects (the T and E training sets) can be extracted from the question-and-answer pairs automatically via text analysis if manually curated lists are not available. The classified terms can be included in a domain-specific lexicon which facilitates a deep question answering system to yield an answer to a question.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles E. Beller, Paul J. Chase, Jr., Richard L. Darden, Michael Drzewucki, Edward G. Katz, Christopher Phipps, James E. Ramirez
  • Patent number: 10073831
    Abstract: Large lists of domain-specific terms are classified as a particular kind of linguistic object, e.g., lexical answer type T versus canonical answer E, based on features from a domain-specific corpus which have been found to distinguish between the linguistic objects. The distinguishing features can be identified in the corpus based on sets of the linguistic objects derived from question-and-answer pairs. A classifier can be trained using the distinguishing features, and the classification carried out using that classifier. The distinguishing features can include one or more syntactic features or one or more lexical features. The linguistic objects (the T and E training sets) can be extracted from the question-and-answer pairs automatically via text analysis if manually curated lists are not available. The classified terms can be included in a domain-specific lexicon which facilitates a deep question answering system to yield an answer to a question.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles E. Beller, Paul J. Chase, Jr., Richard L. Darden, Michael Drzewucki, Edward G. Katz, Christopher Phipps, James E. Ramirez
  • Patent number: 10031907
    Abstract: An aspect of auto-completion of text entered by a user includes configurable data collection components that collect from software applications text data and metadata representing an initial state of each of the applications and text data and metadata representing changes to the state of one or more of the applications. A central text matching component receives and stores the text data and metadata. A sending component sends text entered by the user in a text-entry field and any metadata associated with it to the central text matching component. A comparison component compares the entered text and associated metadata to the stored text data and metadata and locates matching text strings. A weighted ordering component ranks the matching text strings using the metadata and its configuration settings. A completion component completes the entered text at the text-entry field based on a selection of one of the located matching text strings.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David R. Bell, Peter J. Cullen, John W. Duffell, Darren J. Sullivan
  • Patent number: 9997232
    Abstract: Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: June 12, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Richard C. Murphy
  • Patent number: 9966147
    Abstract: Systems and methods presented herein provide for computing read voltages for a storage device. In one embodiment, a controller is controller is operable to soft read data from a portion of the storage device, and to iteratively test the soft read data a predetermined number of times. For example, the controller may test the soft read data a number of times by applying a different probability weight to the soft read data each time the soft read data is tested. The controller may then decode the soft read data based on the probability weight, and determine an error metric of the decoded soft read data. Then, the controller determines a read voltage for the portion of the storage device based on the probability weight and the error metric.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: May 8, 2018
    Assignee: Seagate Technology
    Inventors: Nicholas Odin Lien, Ryan James Goss
  • Patent number: 9953716
    Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 24, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Matsunaga
  • Patent number: 9947279
    Abstract: A display device has a data-holding circuit with a capacitance and a display portion with a plurality of pixel electrodes, formed on a first carrier substrate. In the display device, a second carrier substrate disposed opposite the first carrier substrate is placed above the display portion, but the opposing substrate is not present above the area in which the data-holding circuit is disposed. The parasitic capacitance of the data-holding circuit can thereby be reduced. Therefore, the capacitance in the data-holding circuit can be reduced and the area required can be reduced as well. The display data of all the pixels is sent serially to the liquid crystal module without high-speed transfer for each frame time interval, and size can be reduced because the controller IC and interface circuit are formed on the same substrate as the display device substrate.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 17, 2018
    Assignee: NLT TECHNOLOGIES, LTD.
    Inventors: Kenichi Takatori, Hiroshi Haga
  • Patent number: 9898586
    Abstract: Systems and methods for use in providing input relating to medical data are provided. A method includes receiving a partial textual input relating to medical data. The method further includes determining one or more suggested input strings associated with the partial textual input. Determining the suggested input string(s) includes: (1) for each of a plurality of reference input strings contained within one or more of a plurality of reference files within a database, identifying a frequency with which the reference input string appears in the plurality of reference files, and (2) determining the suggested input string(s) further includes determining the suggested input string(s) from among the plurality of reference input strings based on the frequencies with which the reference input strings appear in the plurality of reference files. The method further includes providing the suggested input string(s) to the user as suggestions for completing the partial textual input.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 20, 2018
    Assignee: Mortara Instrument, Inc.
    Inventors: Justin Mortara, Scott Dorsey
  • Patent number: 9824769
    Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: November 21, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sunil Kumar Dusa, Richard Allen Bailey, Archana Venugopal, John Anthony Rodriguez, Michael Allen Ball
  • Patent number: 9823853
    Abstract: A data storage device includes a first nonvolatile memory device including a target memory region, and a controller suitable for performing a first data input operation to transmit first data, which is to be stored in the target memory region, to the first nonvolatile memory device, regardless of whether a size of the first data corresponds to the target memory region.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: November 21, 2017
    Assignee: SK Hynix Inc.
    Inventor: Beom Ju Shin
  • Patent number: 9742603
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for link training between a host device and a device. The host device includes a clock source, front-end circuitry, a duty cycle monitor (DCM), link training logic, and a duty cycle adjustor (DCA). The front-end circuitry is to transmit a training sequence and a forward clock signal to the device and is to receive a strobe signal from the device over a physical transmission media. The DCM is to monitor duty cycle of the strobe signal and duty cycle of the clock signal. The link training logic is to determine a adjustment to the clock signal and is to generate a control signal. The DCA is to receive the clock signal and the control signal and is to adjust the clock signal to generate an adjusted forward clock signal in view of the control signal.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Chenchu Punnarao Bandi, Amit Kumar Srivastava, Sabyasachi Mohapatra
  • Patent number: 9721630
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: August 1, 2017
    Assignee: RAMBUS INC.
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • Patent number: 9686131
    Abstract: A system, a gateway, and a method for automatic setting configuration by learning commands are provided. The invention collects communication commands sent in a first network, stores target data accessed by a first device in the first network according to the communication command to an address, and maps the address to an I/O module used to access the target data by a second device. The system and the method can set the configuration of a gateway automatically, and achieve the effect of enhancing the efficiency of gateway configuration setting.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: June 20, 2017
    Assignee: MOXA INC.
    Inventors: Bo Er Wei, Kuo Wei Chu
  • Patent number: 9659613
    Abstract: A disclosed example accesses a binary value latched by a sense amplifier in circuit with a memory cell, the binary value latched by the sense amplifier in response to a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cell; determines a programmed state of the memory cell based on the binary value; and performs a memory operation based on the programmed state of the memory cell.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Feng Pan, Ramin Ghodsi
  • Patent number: 9571704
    Abstract: According to an embodiment a signal multiplexing apparatus includes a clock selector, a data selector, and a converter. The clock selector selects either a first clock signal synchronized with a first data signal or a second clock signal different from the first clock signal to obtain a third clock signal. The data selector selects a subset of a first signal set at each timing controlled by the third clock signal to generate a first parallel signal. The first signal set includes the first data signal and a second data signal whose speed is lower than a speed of the first data signal. The converter converts the first parallel signal into a serial signal in accordance with the third clock signal.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: February 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Akita, Yukako Tsutsumi
  • Patent number: 9559796
    Abstract: A location sensitive, public security advisory system and method that communicates with the service subscriber app running on mobile devices, and utilizes the real-time location information to present comprehensive subscriber status information in a given area of interest to security agents. This system can also identify zones at different security status and direct the apps on the mobile devices to display textual alerts and visual geographical zone alerts on the map and blueprint of the area of interest. The system can also provide escape route advice to the subscribers textually or visually on the app's map.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 31, 2017
    Inventor: Calvin Jiawei Wang
  • Patent number: 9496010
    Abstract: A semiconductor device and a memory system including the same are disclosed, which relate to a technology for reducing a toggle current of a global input output (GIO) of a semiconductor device configured to use a data bus inversion (DBI) scheme. The semiconductor device includes:a local input/output (LIO) line driver configured to perform inversion or non-inversion of data of a global input/output (GIO) line according to a control signal, and to output the inversion or non-inversion result to the LIO line; and an inversion processor configured to combine an inversion control signal and mat information, and output the control signal for controlling inversion or non-inversion of data to the LIO line driver.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: November 15, 2016
    Assignee: SK hynix Inc.
    Inventor: Jae Woong Yun
  • Patent number: 9406351
    Abstract: There is provided a memory unit comprising one or more global bit lines connected to a sense amplifier, and a plurality of memory cells that are grouped into a plurality of memory cell groups, each memory cell group having one or more local bit lines operatively connected to each of the memory cells in the memory cell group. Each memory cell group is configured such that, when a memory cell of the memory cell group is being read, the one or more local bit lines of the memory cell group are provided as inputs to a logic circuit and are not connected to the global bit lines, the logic circuit being configured to cause a capacitance element to be connected to one of the one or more global bit lines in dependence upon the states of the one or more local bit lines of the memory cell group.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: August 2, 2016
    Assignee: SURECORE LIMITED
    Inventor: Anthony Stansfield
  • Patent number: 9401698
    Abstract: Electronic circuits and memory circuits are provided for implementing a method for transforming a chip clock signal to a local clock signal. The method includes: generating a first clock signal in response to the chip clock signal, a first control signal and a second control signal; generating a second clock signal by delaying the first clock signal with a second clock delay; generating the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, where the first control signal goes from high-to-low with a control signal delay after the second control signal goes from high-to-low, and vice versa; and generating the local clock signal based on the second clock signal.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: July 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yuen Hung Chan, Juergen Pille, Rolf Sautter, Tobias Werner
  • Patent number: 9396805
    Abstract: A non-volatile memory system and a method of operating a non-volatile memory system are provided. The method includes receiving a command from a host, generating a strobe signal using a clock signal, generating a command response synchronized with the strobe signal and corresponding to the received command and outputting the strobe signal and the command response.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: July 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-Pil Lee
  • Patent number: 9390804
    Abstract: A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least one page of the flash memory. A second phase of updating the counter programs a state zero in the flash memory each time the counter is incremented/decremented.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: July 12, 2016
    Assignee: PROTON WORLD INTERNATIONAL N.V.
    Inventors: Ronny Van Keer, Youssef Ahssini
  • Patent number: 9390789
    Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: July 12, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuichiro Ishii
  • Patent number: 9355695
    Abstract: A semiconductor memory device includes a row input section suitable for receiving a first row signal including a first row command and a first row address, corresponding to an active command, during a test operation of the active command, a column input section suitable for receiving a second row signal including a second row address corresponding to the active command during the test operation of the active command, and a signal control section suitable for generating an internal row signal for an operation of the active command by transforming the first row signal and the second row signal outputted from the row input section and the column input section.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: May 31, 2016
    Assignee: SK Hynix Inc.
    Inventor: Chun-Seok Jeong
  • Patent number: 9348679
    Abstract: A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller performs a page remapping operation in parallel with a normal operation of a scheduling unit to perform a latency overhead hidden function. A chip size of the DRAM is reduced or minimized. A DRAM controller performs a latency overhead hidden function to control a DRAM.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 24, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Hee Yoo, Sung Hyun Lee, Dongsoo Kang, Sua Kim, Haksoo Yu, Jaeyoun Youn, Hyojin Choi
  • Patent number: 9268690
    Abstract: A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and from a memory array. The same input/output line or pairs of complementary global input/output lines may be used for coupling both write data signals and read data signals.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: February 23, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Shigeki Tomishima
  • Patent number: 9251912
    Abstract: A semiconductor memory device comprising a memory cell array with a plurality of word lines, first and second dummy word lines, and a dummy word line driver suitable for separately driving the first and second dummy word lines for a wafer burn-in test where the word lines are driven by group.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: February 2, 2016
    Assignee: SK Hynix Inc.
    Inventors: Hyun-Sung Lee, Kee-Teok Park
  • Patent number: 9230643
    Abstract: Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (PCMS) devices. The read pulses may be applied at a first voltage for a first period of time. A threshold event for the phase change memory cell may be detected during a sense window. The sense window may close after the expiration of the first period of time for which the read pulses are applied.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: January 5, 2016
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Hernan Castro, Timothy C. Langtry, Richard Dodge, Ilya Karpov
  • Patent number: 9230621
    Abstract: A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a buffer that inputs a first signal and outputs a first delay signal, a command decoder that outputs a second signal, a mask pulse signal generator that inputs the first delay signal and the second signal and generates a mask pulse signal, and a signal reshaper that inputs the first delay signal, the second signal and the mask pulse signal and reshapes the first delay signal or the second signal.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: January 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Shim, In-Dal Song
  • Patent number: 9190120
    Abstract: A data storage device including a reset circuit and a method of resetting thereof includes a memory device to receive a driving voltage through a power terminal thereof, a voltage regulator to adjust an external voltage to provide the adjusted voltage to the power terminal of the memory device, and a reset circuit to discharge an enable terminal of the voltage regulator or the power terminal of the memory device according to a change of the external voltage.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: November 17, 2015
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Hojun Shim, Woo-Sung Cho
  • Patent number: 9161188
    Abstract: Disclosed is a system and method for suggesting messages that are automatically learned, personalized and diversified by leveraging messages sent by a large number of users in order to provide message completions that are as engaging as possible. The disclosed systems and methods learn from recurrent messages sent to a recipient, and suggest message completions based upon user behavior. The systems and methods compute a ranked list of suggested message completions after every key stroke or character input, and if the list satisfies a given confidence threshold, it is returned and displayed to the user.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: October 13, 2015
    Inventors: Yoelle Maarek Smadja, Nadav Goldbandi
  • Patent number: 9142285
    Abstract: A multi-port SRAM with shared write bit-line architecture and selective read path for low power operation includes a first memory cell, a second memory cell, and a common switch set. The second memory cell makes use of the common switch set to share the A-port write bit-line and the B-port write bit-line with the first memory cell so as to reduce half write bit-line number and reduce the write current consumption caused by pre-charging the bit-line to VDD. It also provides a selective read path structure for read operation. Replacing the ground connection in the read port with a virtual VSS controlled by a Y-select signal reduces read-port current consumption.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: September 22, 2015
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Wei Hwang, Dao-Ping Wang
  • Patent number: 9135984
    Abstract: Disclosed are apparatuses and methods for writing data to a memory array of a buffer. One such apparatus may include a multiplexer that receives data words and a data mask. The multiplexer may change the order of the data words to group masked data words together and to group unmasked data words together. The multiplexer may also change the order of the data mask to group masking bits together and to group unmasking bits together. The apparatus may use the data words with the changed order and the data mask with the changed order to write data to the memory array.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: September 15, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Parthasarathy Gajapathy, David R. Brown
  • Patent number: 9105353
    Abstract: A memory device includes a level shifter which includes a first input terminal, a second input terminal, a first output terminal configured to output a first signal, and a second output terminal configured to output an inverted signal of the first signal, a first buffer, a second buffer, a first node, and a second node. The first node, where an output terminal of the first buffer and the first input terminal of the level shifter are connected, is configured to hold a first data. The second node, where an output terminal of the second buffer and the second input terminal of the level shifter are connected, is configured to hold a second data.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: August 11, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuji Nishijima
  • Patent number: 9082486
    Abstract: A row decoding circuit and a memory are provided. The row decoding circuit is adapted for providing a word line operation voltage and a control-gate line operation voltage to a dual-bit split gate flash memory array, and includes a dummy row decoding unit, at least one row decoding unit and a driving voltage generating circuit. The dummy row decoding unit includes a first dummy control-gate line voltage output, a second dummy control-gate line voltage output and at least one dummy word line voltage output. The row decoding unit includes a first control-gate line voltage output, a second control-gate line voltage output and at least one word line voltage output. The driving voltage generating circuit is adapted for providing a third driving voltage to the first control-gate line voltage output and the second control-gate line voltage output.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: July 14, 2015
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Guangjun Yang
  • Patent number: 9063520
    Abstract: An apparatus for inserting delay according to an embodiment includes a signal generating circuit, a plurality of carry elements, and a delay chain circuit. The delay chain circuit includes one or more delay modules selected from the plurality of carry elements, at least one feedback line connected between at least one of the delay modules and the signal generating circuit, and a plurality of enable inputs. Each of the plurality of enable inputs is provided in a respective one of the delay modules. The delay chain circuit is configured to generate an amount of delay based on a delay selection signal that is received at the enable inputs and that selects the amount of delay, and is configured to provide the selected amount of delay to the signal generating circuit, which is configured to incorporate the delay into the start signal.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: June 23, 2015
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Medical Systems Corporation
    Inventor: Gregory J. Mann
  • Patent number: 9058871
    Abstract: The resistive random access memory (ReRAM) device includes a first amplifier configured to amplify a sensing current corresponding to data sensed in a memory cell, and a second amplifier configured to store the sensing current amplified by the first amplifier, and amplify electric charges when storing the amplified sensing current.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 16, 2015
    Assignee: SK HYNIX INC.
    Inventor: Kwang Seok Kim
  • Patent number: 9058874
    Abstract: A sensing circuit includes a plurality of cell read current generators, a reference current generator and a plurality of sense amplifiers. Each of the cell read current generators generates a cell read current from each of a plurality of memory cells. The reference current generator sums the cell read currents to generate a sum current. Each of the sense amplifiers determines data state stored in each of the memory cells based on each of the cell read currents and an average current. The average current is obtained based on the sum current.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: June 16, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Don Choi, Mu-Hui Park, Hyun-Kook Park, Ickhyun Song
  • Patent number: 9042182
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array, a plurality of local sense amplifiers, a global sense amplifier and an address decoder. The address decoder is configured to switch between a first verification and a second verification. The first verification operates the plurality of local sense amplifiers and simultaneously verifies data of a plurality of memory cells connected to the plurality of local sense amplifiers. The second verification stops the plurality of local sense amplifiers, directly connects the local bit line connected to each of the local sense amplifiers with the global bit line, and simultaneously verifies data of the plurality of memory cells connected to the plurality of local sense amplifiers.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: May 26, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Mitsuharu Sakakibara
  • Patent number: 9042148
    Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: May 26, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
  • Patent number: 9036395
    Abstract: A method for programmed-state detection in memristor stacks includes applying a first secondary switching voltage across a memristor stack to produce a first programmed-state-dependent secondary switching response in a memristor in the memristor stack. The programmed-state-dependent secondary switching response results in a detectable change in the electrical resistance of the memristor stack. The method also includes measuring a first electrical resistance of the memristor stack and inferring the programmed state of the memristor stack from the measured electrical resistance.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: May 19, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Richard J. Carter
  • Patent number: 9036432
    Abstract: A method for controlling data write operation of a mass storage device is provided. The mass storage device has a controller and a memory unit. The method includes connecting the mass storage device to a host device, and receiving a voltage provided from the host device; sensing and monitoring whether the voltage is lower than a first predefined voltage; writing data to the mass storage device with a first frequency when the sensed voltage is higher than the first predefined voltage; and writing data to the mass storage device with a second frequency when the sensed voltage is lower than the first predefined voltage, wherein the second frequency is adjusted by decreasing the first frequency.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: May 19, 2015
    Assignee: Transcend Information, Inc.
    Inventor: Chun-Chieh Wang
  • Patent number: 9036410
    Abstract: A Y-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: May 19, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
  • Patent number: 9036431
    Abstract: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: May 19, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Bum Kim, Hyung Gon Kim, Chul Ho Lee, Hong Seok Chang
  • Patent number: 9030906
    Abstract: An embodiment may include local row and column circuitry that are local to a memory cell of a memory device. Either the local row circuitry or the local column circuitry may be electrically isolated, at least in part, from at least one remaining portion of the memory device during the establishing of a voltage differential between the local row circuitry and the local column circuitry that is to permit the memory cell to be read during a read of the memory cell. The read may occur subsequent to the establishing of the voltage differential. Many variations, modifications, and alternatives are possible without departing from this embodiment.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: May 12, 2015
    Assignee: Intel Corporation
    Inventors: Doyle Rivers, Prashant S. Damle, Raymond W. Zeng
  • Patent number: 9030892
    Abstract: There is disclosed a data reading device in which data of a nonvolatile storage element is reflected in a circuit to be regulated, with a minimum necessary delay width after turning a power on or after reset cancellation, and wrong writing due to a static electricity is prevented. A delay circuit is additionally disposed to output a delayed data reading signal after a signal of turning the power on or a signal of the reset cancellation is generated. A delay time T2 and a static electricity convergence time T1 are set so as to keep a relation of T1<T2.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: May 12, 2015
    Assignee: Seiko Instruments Inc.
    Inventors: Kotaro Watanabe, Makoto Mitani
  • Patent number: RE46203
    Abstract: A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (1), when a selected memory cell transistor (115) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a PMOS transistor (9b) while low voltage as writing voltage is applied from an NMOS transistor (15a). Thus, a role of applying voltage to either the selected memory cell transistor (115) or a non-selected memory cell transistor (116) is shared by the PMOS transistor (9b) and the NMOS transistor (15a). Therefore, the gate voltage and the source voltage of the PMOS transistor (9b) and those of the NMOS transistor (15a) can be separately adjusted, and gate-to-substrate voltage thereof can be finally set to be, for instance, 4[V] or etc.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: November 15, 2016
    Assignee: Floadia Corporation
    Inventors: Yutaka Shinagawa, Hideo Kasai, Yasuhiro Taniguchi