Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

Abstract: A display device has a data-holding circuit with a capacitance and a display portion with a plurality of pixel electrodes, formed on a first carrier substrate. In the display device, a second carrier substrate disposed opposite the first carrier substrate is placed above the display portion, but the opposing substrate is not present above the area in which the data-holding circuit is disposed. The parasitic capacitance of the data-holding circuit can thereby be reduced. Therefore, the capacitance in the data-holding circuit can be reduced and the area required can be reduced as well. The display data of all the pixels is sent serially to the liquid crystal module without high-speed transfer for each frame time interval, and size can be reduced because the controller IC and interface circuit are formed on the same substrate as the display device substrate.

Abstract: Systems and methods for use in providing input relating to medical data are provided. A method includes receiving a partial textual input relating to medical data. The method further includes determining one or more suggested input strings associated with the partial textual input. Determining the suggested input string(s) includes: (1) for each of a plurality of reference input strings contained within one or more of a plurality of reference files within a database, identifying a frequency with which the reference input string appears in the plurality of reference files, and (2) determining the suggested input string(s) further includes determining the suggested input string(s) from among the plurality of reference input strings based on the frequencies with which the reference input strings appear in the plurality of reference files. The method further includes providing the suggested input string(s) to the user as suggestions for completing the partial textual input.

Abstract: A data storage device includes a first nonvolatile memory device including a target memory region, and a controller suitable for performing a first data input operation to transmit first data, which is to be stored in the target memory region, to the first nonvolatile memory device, regardless of whether a size of the first data corresponds to the target memory region.

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for link training between a host device and a device. The host device includes a clock source, front-end circuitry, a duty cycle monitor (DCM), link training logic, and a duty cycle adjustor (DCA). The front-end circuitry is to transmit a training sequence and a forward clock signal to the device and is to receive a strobe signal from the device over a physical transmission media. The DCM is to monitor duty cycle of the strobe signal and duty cycle of the clock signal. The link training logic is to determine a adjustment to the clock signal and is to generate a control signal. The DCA is to receive the clock signal and the control signal and is to adjust the clock signal to generate an adjusted forward clock signal in view of the control signal.

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

Abstract: A system, a gateway, and a method for automatic setting configuration by learning commands are provided. The invention collects communication commands sent in a first network, stores target data accessed by a first device in the first network according to the communication command to an address, and maps the address to an I/O module used to access the target data by a second device. The system and the method can set the configuration of a gateway automatically, and achieve the effect of enhancing the efficiency of gateway configuration setting.

Abstract: A disclosed example accesses a binary value latched by a sense amplifier in circuit with a memory cell, the binary value latched by the sense amplifier in response to a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cell; determines a programmed state of the memory cell based on the binary value; and performs a memory operation based on the programmed state of the memory cell.

Abstract: According to an embodiment a signal multiplexing apparatus includes a clock selector, a data selector, and a converter. The clock selector selects either a first clock signal synchronized with a first data signal or a second clock signal different from the first clock signal to obtain a third clock signal. The data selector selects a subset of a first signal set at each timing controlled by the third clock signal to generate a first parallel signal. The first signal set includes the first data signal and a second data signal whose speed is lower than a speed of the first data signal. The converter converts the first parallel signal into a serial signal in accordance with the third clock signal.

Abstract: A location sensitive, public security advisory system and method that communicates with the service subscriber app running on mobile devices, and utilizes the real-time location information to present comprehensive subscriber status information in a given area of interest to security agents. This system can also identify zones at different security status and direct the apps on the mobile devices to display textual alerts and visual geographical zone alerts on the map and blueprint of the area of interest. The system can also provide escape route advice to the subscribers textually or visually on the app's map.

Abstract: A semiconductor device and a memory system including the same are disclosed, which relate to a technology for reducing a toggle current of a global input output (GIO) of a semiconductor device configured to use a data bus inversion (DBI) scheme. The semiconductor device includes:a local input/output (LIO) line driver configured to perform inversion or non-inversion of data of a global input/output (GIO) line according to a control signal, and to output the inversion or non-inversion result to the LIO line; and an inversion processor configured to combine an inversion control signal and mat information, and output the control signal for controlling inversion or non-inversion of data to the LIO line driver.

Abstract: There is provided a memory unit comprising one or more global bit lines connected to a sense amplifier, and a plurality of memory cells that are grouped into a plurality of memory cell groups, each memory cell group having one or more local bit lines operatively connected to each of the memory cells in the memory cell group. Each memory cell group is configured such that, when a memory cell of the memory cell group is being read, the one or more local bit lines of the memory cell group are provided as inputs to a logic circuit and are not connected to the global bit lines, the logic circuit being configured to cause a capacitance element to be connected to one of the one or more global bit lines in dependence upon the states of the one or more local bit lines of the memory cell group.

Abstract: Electronic circuits and memory circuits are provided for implementing a method for transforming a chip clock signal to a local clock signal. The method includes: generating a first clock signal in response to the chip clock signal, a first control signal and a second control signal; generating a second clock signal by delaying the first clock signal with a second clock delay; generating the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, where the first control signal goes from high-to-low with a control signal delay after the second control signal goes from high-to-low, and vice versa; and generating the local clock signal based on the second clock signal.

Abstract: A non-volatile memory system and a method of operating a non-volatile memory system are provided. The method includes receiving a command from a host, generating a strobe signal using a clock signal, generating a command response synchronized with the strobe signal and corresponding to the received command and outputting the strobe signal and the command response.

Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

Abstract: A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least one page of the flash memory. A second phase of updating the counter programs a state zero in the flash memory each time the counter is incremented/decremented.

Abstract: A semiconductor memory device includes a row input section suitable for receiving a first row signal including a first row command and a first row address, corresponding to an active command, during a test operation of the active command, a column input section suitable for receiving a second row signal including a second row address corresponding to the active command during the test operation of the active command, and a signal control section suitable for generating an internal row signal for an operation of the active command by transforming the first row signal and the second row signal outputted from the row input section and the column input section.

Abstract: A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller performs a page remapping operation in parallel with a normal operation of a scheduling unit to perform a latency overhead hidden function. A chip size of the DRAM is reduced or minimized. A DRAM controller performs a latency overhead hidden function to control a DRAM.

Abstract: A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and from a memory array. The same input/output line or pairs of complementary global input/output lines may be used for coupling both write data signals and read data signals.

Abstract: A semiconductor memory device comprising a memory cell array with a plurality of word lines, first and second dummy word lines, and a dummy word line driver suitable for separately driving the first and second dummy word lines for a wafer burn-in test where the word lines are driven by group.

Abstract: A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a buffer that inputs a first signal and outputs a first delay signal, a command decoder that outputs a second signal, a mask pulse signal generator that inputs the first delay signal and the second signal and generates a mask pulse signal, and a signal reshaper that inputs the first delay signal, the second signal and the mask pulse signal and reshapes the first delay signal or the second signal.

Abstract: Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (PCMS) devices. The read pulses may be applied at a first voltage for a first period of time. A threshold event for the phase change memory cell may be detected during a sense window. The sense window may close after the expiration of the first period of time for which the read pulses are applied.

Abstract: A data storage device including a reset circuit and a method of resetting thereof includes a memory device to receive a driving voltage through a power terminal thereof, a voltage regulator to adjust an external voltage to provide the adjusted voltage to the power terminal of the memory device, and a reset circuit to discharge an enable terminal of the voltage regulator or the power terminal of the memory device according to a change of the external voltage.

Abstract: Disclosed is a system and method for suggesting messages that are automatically learned, personalized and diversified by leveraging messages sent by a large number of users in order to provide message completions that are as engaging as possible. The disclosed systems and methods learn from recurrent messages sent to a recipient, and suggest message completions based upon user behavior. The systems and methods compute a ranked list of suggested message completions after every key stroke or character input, and if the list satisfies a given confidence threshold, it is returned and displayed to the user.

Abstract: A multi-port SRAM with shared write bit-line architecture and selective read path for low power operation includes a first memory cell, a second memory cell, and a common switch set. The second memory cell makes use of the common switch set to share the A-port write bit-line and the B-port write bit-line with the first memory cell so as to reduce half write bit-line number and reduce the write current consumption caused by pre-charging the bit-line to VDD. It also provides a selective read path structure for read operation. Replacing the ground connection in the read port with a virtual VSS controlled by a Y-select signal reduces read-port current consumption.

Abstract: Disclosed are apparatuses and methods for writing data to a memory array of a buffer. One such apparatus may include a multiplexer that receives data words and a data mask. The multiplexer may change the order of the data words to group masked data words together and to group unmasked data words together. The multiplexer may also change the order of the data mask to group masking bits together and to group unmasking bits together. The apparatus may use the data words with the changed order and the data mask with the changed order to write data to the memory array.

Abstract: A memory device includes a level shifter which includes a first input terminal, a second input terminal, a first output terminal configured to output a first signal, and a second output terminal configured to output an inverted signal of the first signal, a first buffer, a second buffer, a first node, and a second node. The first node, where an output terminal of the first buffer and the first input terminal of the level shifter are connected, is configured to hold a first data. The second node, where an output terminal of the second buffer and the second input terminal of the level shifter are connected, is configured to hold a second data.

Abstract: A row decoding circuit and a memory are provided. The row decoding circuit is adapted for providing a word line operation voltage and a control-gate line operation voltage to a dual-bit split gate flash memory array, and includes a dummy row decoding unit, at least one row decoding unit and a driving voltage generating circuit. The dummy row decoding unit includes a first dummy control-gate line voltage output, a second dummy control-gate line voltage output and at least one dummy word line voltage output. The row decoding unit includes a first control-gate line voltage output, a second control-gate line voltage output and at least one word line voltage output. The driving voltage generating circuit is adapted for providing a third driving voltage to the first control-gate line voltage output and the second control-gate line voltage output.

Abstract: An apparatus for inserting delay according to an embodiment includes a signal generating circuit, a plurality of carry elements, and a delay chain circuit. The delay chain circuit includes one or more delay modules selected from the plurality of carry elements, at least one feedback line connected between at least one of the delay modules and the signal generating circuit, and a plurality of enable inputs. Each of the plurality of enable inputs is provided in a respective one of the delay modules. The delay chain circuit is configured to generate an amount of delay based on a delay selection signal that is received at the enable inputs and that selects the amount of delay, and is configured to provide the selected amount of delay to the signal generating circuit, which is configured to incorporate the delay into the start signal.

Abstract: A sensing circuit includes a plurality of cell read current generators, a reference current generator and a plurality of sense amplifiers. Each of the cell read current generators generates a cell read current from each of a plurality of memory cells. The reference current generator sums the cell read currents to generate a sum current. Each of the sense amplifiers determines data state stored in each of the memory cells based on each of the cell read currents and an average current. The average current is obtained based on the sum current.

Abstract: The resistive random access memory (ReRAM) device includes a first amplifier configured to amplify a sensing current corresponding to data sensed in a memory cell, and a second amplifier configured to store the sensing current amplified by the first amplifier, and amplify electric charges when storing the amplified sensing current.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array, a plurality of local sense amplifiers, a global sense amplifier and an address decoder. The address decoder is configured to switch between a first verification and a second verification. The first verification operates the plurality of local sense amplifiers and simultaneously verifies data of a plurality of memory cells connected to the plurality of local sense amplifiers. The second verification stops the plurality of local sense amplifiers, directly connects the local bit line connected to each of the local sense amplifiers with the global bit line, and simultaneously verifies data of the plurality of memory cells connected to the plurality of local sense amplifiers.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: A Y-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage.

Abstract: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.

Abstract: A method for controlling data write operation of a mass storage device is provided. The mass storage device has a controller and a memory unit. The method includes connecting the mass storage device to a host device, and receiving a voltage provided from the host device; sensing and monitoring whether the voltage is lower than a first predefined voltage; writing data to the mass storage device with a first frequency when the sensed voltage is higher than the first predefined voltage; and writing data to the mass storage device with a second frequency when the sensed voltage is lower than the first predefined voltage, wherein the second frequency is adjusted by decreasing the first frequency.

Abstract: A method for programmed-state detection in memristor stacks includes applying a first secondary switching voltage across a memristor stack to produce a first programmed-state-dependent secondary switching response in a memristor in the memristor stack. The programmed-state-dependent secondary switching response results in a detectable change in the electrical resistance of the memristor stack. The method also includes measuring a first electrical resistance of the memristor stack and inferring the programmed state of the memristor stack from the measured electrical resistance.

Abstract: There is disclosed a data reading device in which data of a nonvolatile storage element is reflected in a circuit to be regulated, with a minimum necessary delay width after turning a power on or after reset cancellation, and wrong writing due to a static electricity is prevented. A delay circuit is additionally disposed to output a delayed data reading signal after a signal of turning the power on or a signal of the reset cancellation is generated. A delay time T2 and a static electricity convergence time T1 are set so as to keep a relation of T1<T2.

Abstract: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

Abstract: An operating method of a variable resistance memory device including a pre-read step which may include the steps of: reading a first reference cell using a first reference voltage; reading a second reference cell using a second reference voltage; and setting a third reference voltage based on the first and second reference voltages; and a main read step of reading a selected memory cell using the third reference voltage.

Abstract: A three-dimensional (3D) semiconductor memory device comprises memory cell strings each comprising at least one selection transistor and at least one memory cell, a first pass transistor group sharing a first well region and comprising a first selection line pass transistor connected to the selection transistor and a first world line pass transistor connected to the memory cell, a second pass transistor group sharing a second well region and comprising a second selection line pass transistor connected to the selection transistor, and a controller that controls the first pass transistor group and the second pass transistor group. The controller applies selected voltages to the first and second well regions during read operation.

Abstract: An embodiment may include local row and column circuitry that are local to a memory cell of a memory device. Either the local row circuitry or the local column circuitry may be electrically isolated, at least in part, from at least one remaining portion of the memory device during the establishing of a voltage differential between the local row circuitry and the local column circuitry that is to permit the memory cell to be read during a read of the memory cell. The read may occur subsequent to the establishing of the voltage differential. Many variations, modifications, and alternatives are possible without departing from this embodiment.

Abstract: A flash memory device comprising a local sensing circuitry is provided in a hierarchical structure with local and global bit lines. The local sensing circuitry comprise read and pass circuits configured to sense and amplify read currents during read operations, wherein the amplified read signals may be passed to a global circuit via the local and global bit lines.

Abstract: Some embodiments include apparatuses and methods having a first data line, a second data line, a first transistor, a sense amplifier, and a circuit. The first transistor can operate to couple the first data line to a first node during a first stage of an operation of obtaining information from a memory cell associated with the first data line. The second transistor can operate to couple the second data line to a second node during the first stage. The circuit can operate to apply a first signal to a gate of the first transistor during the operation and to apply a second signal to a gate of the second transistor during the operation. The sense amplifier can operate to perform a sense function on the first and second data lines during a second stage of the operation. Additional apparatus and methods are described.

Abstract: Provided are a semiconductor memory device, a memory system including the same, and an operating method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit suitable for reading least significant bit data and most significant bit data of neighboring memory cells adjacent to selected memory cells out of the plurality of memory cells, and generating pattern flag data using the least significant bit data and the most significant bit data and a control logic suitable for controlling the peripheral circuit to set a read voltage to be applied to the selected memory cells based on the pattern flag data.

Abstract: Static random access memory (SRAM) global bitline circuits for reducing glitches during read accesses, and related methods and systems are disclosed. A global bitline scheme in SRAM can reduce output load, reducing power consumption. In certain embodiments, SRAM includes an SRAM array. The SRAM includes a global bitline circuit for each SRAM array column. Each global bitline circuit includes memory access circuit that pre-charges local bitlines corresponding to bitcells in SRAM array. The data read from selected bitcell is read from its local bitline onto aggregated read bitline, an aggregation of local bitlines. The SRAM includes bitline evaluation circuit that sends data from aggregated read bitline onto global bitline. Instead of sending data based on rising transition of clock trigger, data is sent onto the global bitline based on falling transition of clock trigger. A global bitline scheme can be employed that reduces glitches and resulting increases in power consumption.

Abstract: A semiconductor integrated circuit includes an input data line pair, a sense amplifier configured to sense and amplify data loaded in the input data line pair and transmit the amplified data to an output data line pair, in response to a control signal, and a sense amplification controller configured to sense an amplification level of the output data line pair, limit an activation period of a sense amplification enable signal, and output the limited signal as the control signal.

Abstract: According to one embodiment, a non-volatile semiconductor storage device includes a memory cell array, a row decoder, a potential generating circuit, first plural potential selection circuits, a second potential selection circuit, a first discharge circuit, and a second discharge circuit. The first plural potential selection circuits select one of output potentials of the potential generating circuit by receiving a first control signal and apply the selected output potential to a first signal line. The second potential selection circuit applies a potential of the first signal line to a second signal line connected to the row decoder by receiving a second control signal. The first discharge circuit is arranged in the first potential selection circuit. The second discharge circuit is arranged in the second potential selection circuit.

Abstract: A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (1), when a selected memory cell transistor (115) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a PMOS transistor (9b) while low voltage as writing voltage is applied from an NMOS transistor (15a). Thus, a role of applying voltage to either the selected memory cell transistor (115) or a non-selected memory cell transistor (116) is shared by the PMOS transistor (9b) and the NMOS transistor (15a). Therefore, the gate voltage and the source voltage of the PMOS transistor (9b) and those of the NMOS transistor (15a) can be separately adjusted, and gate-to-substrate voltage thereof can be finally set to be, for instance, 4[V] or etc.