Particular Write Circuit Patents (Class 365/189.16)
  • Patent number: 11024378
    Abstract: Memory systems and memory programming methods are described.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 1, 2021
    Assignee: Micron Technology , Inc.
    Inventors: Emiliano Faraoni, Scott E. Sills, Alessandro Calderoni, Adam Johnson
  • Patent number: 10978167
    Abstract: A disclosed circuit arrangement includes a bank of efuse cells, first and second sense amplifiers coupled to input signals representing constant logic-1 and logic-0 values, respectively, a storage circuit, an efuse control circuit, and an efuse security circuit. The efuse control circuit inputs signals from the bank of efuse cells and signals that are output from the first and second sense amplifiers, and stores data representative of values of the signals in the storage circuit. The efuse security reads the data from the storage circuit and generates an alert signal having a state that indicates a security violation in response to data representative of the value of the signal from the first sense amplifier indicating a logic-0 value or data representative of the value of the signal from the second sense amplifier indicating a logic-1 value.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventors: James D. Wesselkamper, Edward S. Peterson, Jason J. Moore, Steven E. McNeil
  • Patent number: 10937493
    Abstract: Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Yogesh Luthra
  • Patent number: 10937481
    Abstract: Various implementations described herein are directed to a device having memory circuitry having bitcells coupled together via bitlines. The device may include polarity swapping circuitry having multiple conductive paths that are configured to couple the bitlines together. In some instances, first paths of the multiple conductive paths couple the bitlines together via first passgates, and second paths of the multiple conductive paths couple the bitlines together via second passgates.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 2, 2021
    Assignee: Arm Limited
    Inventors: Andy Wangkun Chen, Peixuan Tan
  • Patent number: 10861511
    Abstract: A semiconductor device includes a drive control circuit and a write control circuit. The drive control circuit generates a pre-drive control signal and a drive control signal based on a latch command and generates a pattern drive control signal based on a pattern latch command. The write control circuit stores drive data generated from data inputted based on the pre-drive control signal and the drive control signal or stores the drive data driven to a predetermined logic level based on the pattern drive control signal.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Yoo Jong Lee
  • Patent number: 10839870
    Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Harish N. Venkata, Guy S. Perry
  • Patent number: 10825511
    Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Vivek De, Sanu Mathew, Sudhir Satpathy, Vikram Suresh, Raghavan Kumar
  • Patent number: 10783962
    Abstract: A writing method of a resistive memory storage apparatus includes: applying one of a set voltage and a reset voltage serving as a first selected voltage to a memory cell and obtaining a first read current; applying a disturbance voltage to the memory cell and obtaining a second read current; and determining whether a relationship between the first and second read currents satisfies a preset relationship, and if not, applying the other of the set voltage and the reset voltage serving as a second selected voltage to the memory cell and applying the first selected voltage to the memory cell again. A polarity of the disturbance voltage is different from that of the first selected voltage, and the absolute value of the disturbance voltage is less than that of the second selected voltage. A resistive memory storage apparatus is also provided.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 22, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Lih-Wei Lin, Lung-Chi Cheng, Min-Yen Liu, Huan-Ming Chiang
  • Patent number: 10777244
    Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chieh Chiu, Chia-En Huang, Fu-An Wu, I-Han Huang, Jung-Ping Yang
  • Patent number: 10777261
    Abstract: A data-processing device, such as a memory device, includes a signal generator configured to transmit an enable-signal, and a plurality of circuit elements arranged in an array of plurality of rows spaced along a direction, each of the plurality of the circuit elements configured to receive the enable-signal from the signal generator and to input and output data as a result of receiving the enable-signal. The device also includes an input/out (I/O) interface operatively connected to the plurality of circuit elements and located to propagate data from the I/O interface to the circuit elements in a first direction relative to the direction in which the rows are spaced and receive data propagated from the circuit elements to the I/O interface in a second direction relative to the first direction. The signal generator maintains the direction of enable-signal propagation relative to the direction of data propagation regardless of the direction of data propagation.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hyunsung Hong
  • Patent number: 10755786
    Abstract: A semiconductor memory device according to an embodiment includes a plurality of strings each including a select transistor and a memory cell that can be set to any one of a plurality of different threshold voltages, a select gate line that is commonly connected to the select transistors of the plurality of strings, a plurality of bit lines that are individually connected to the plurality of strings, a word line that is commonly connected to the memory cells of the plurality of strings, and a control unit configured to execute a write sequence for repeatedly performing a plurality of loops each including a set of a program operation and a verify operation, and a voltage applied to the select gate line in the program operation of a last loop is lower than a voltage applied to the select gate line in the program operation of a first loop.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 25, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shimura, Yoshikazu Harada
  • Patent number: 10748622
    Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 18, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Lei Lin, Zhuojie Li, Tai-Yuan Tseng, Henry Chin, Gerrit Jan Hemink
  • Patent number: 10720194
    Abstract: In a semiconductor memory device, a memory cell array includes a plurality of memory cells. A write circuit includes a negative potential generating circuit that generates a potential lower than a lower power supply potential applied to the memory cells. When a write mask signal indicates an enabled state, the write circuit activates the negative potential generating circuit, and supplies the potential generated by the negative potential generating circuit to a bit line to be supplied with low data. On the other hand, when the write mask signal indicates a disabled state, the write circuit supplies no data to bit line pairs, and inactivates the negative potential generating circuit.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 21, 2020
    Assignee: SOCIONEXT INC.
    Inventor: Yoshinobu Yamagami
  • Patent number: 10691346
    Abstract: A read operation method of a nonvolatile memory includes selecting at least a first selection defence code from among a plurality of defence codes by using read voltage level determination information and read environment information, the read environment information including values respectively corresponding to a plurality of factors; determining a level of a read voltage for performing a read operation based on the first selection defence code; and performing the read operation by using the read voltage having the determined level.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Il-su Han
  • Patent number: 10529417
    Abstract: A storage device includes a nonvolatile memory and a controller. The controller is configured to generate coded data based on write data and an error correction code generated from the write data, determine whether or not to invert each bit of the coded data, based on a logical page position of the nonvolatile memory in which the write data are to be written and a value “0” or “1” of bits that are more populated in the coded data than bits having the other value of “1” and “0”, invert each bit of the coded data upon determining to invert, and write the non-inverted or inverted coded data into the logical page position of the nonvolatile memory. The logical page position is one of logical page positions including a lower page and an upper page.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: January 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • Patent number: 10446223
    Abstract: The reliability of a low-power SRAM device fabricated in a small process node can be improved by using an SRAM cell with circuitry that reduces or eliminates contention between pull-up and pull-down devices during write operations. In the first stage of a write operation, the node N that stores the SRAM cell's bit value may be decoupled from a power-supply rail (“Rail 1”) by deactivating one type of “pulling” device (e.g., the type of pulling device that can pull the voltage of node N toward the voltage of Rail 1). Using pulling device(s) of the opposite type, the voltage of node N may then be pulled toward the voltage of the other power-supply rail (“Rail 2”). In this manner, the new SRAM cell may reduce or eliminate contention between pull-up and pull-down devices at node N during the first stage of the write operation.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: October 15, 2019
    Inventor: Valerii Nebesnyi
  • Patent number: 10410694
    Abstract: Techniques related to a high bandwidth interface (HBI) for communication between multiple host devices on an interposer are described. In an example, the HBI repurposes a portion of the high bandwidth memory (HBM) interface, such as the physical layer. A computing system is provided. The computing system includes a first host device and at least a second host device. The first host device is a first die on an interposer and the second host device is a second die on the interposer. The first host device and the second host device are interconnected via at least one HBI. The HBI implements a layered protocol for communication between the first host device and the second host device. The layered protocol includes a physical layer protocol that is configured according to a HBM physical layer protocol.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: September 10, 2019
    Assignee: XILINX, INC.
    Inventors: Ygal Arbel, Sagheer Ahmad, Balakrishna Jayadev
  • Patent number: 10360949
    Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Harish N. Venkata, Guy S. Perry
  • Patent number: 10276227
    Abstract: A method for verifying a write operation in a memory cell (e.g., a non-volatile memory cell) that includes performing a first read operation of the memory cell to measure a first current associated with the memory cell and comparing the measured first current associated with the memory cell to a first predetermined threshold current to determine whether the write operation changed the state of the memory cell. If the measured first current associated with the memory cell indicates the write operation did change the state of the memory cell the method further includes performing a second read operation of the memory cell to measure a second current associated with the memory cell and comparing the measured second current associated with the memory cell to a second predetermined threshold current to determine whether the write operation changed the state of the memory cell to the desired state or an intermediate state.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Chien-Ye Lee, Jenn-Jou Wu, Yi-Chieh Chiu, Yi-Chun Shih, William J. Gallagher
  • Patent number: 10262717
    Abstract: The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: April 16, 2019
    Assignee: Invensas Corporation
    Inventors: David Edward Fisch, William C. Plants
  • Patent number: 10147482
    Abstract: A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy wordline to the dummy row cell pulldown. The write tracker is configured as a transmission gate during a read operation on the bitcell array, and is configured as having only one or more active nMOSFETs during a write operation on the bitcell array.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: December 4, 2018
    Assignee: ARM Limited
    Inventors: Jitendra Dasani, Vivek Nautiyal, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Patent number: 10139850
    Abstract: A current mirror includes an input transistor and an output transistor, wherein the sources of the input and output transistor are connected to a supply voltage node. The gates of the input and output transistors are connected through a switch. A first current source is coupled to the input transistor to provide an input current. A copy transistor has a source connected to the supply node and a gate connected to the gate of the input transistor at a mirror node. A second current source is coupled to the copy transistor to provide a copy current. A source-follower transistor has its source connected to the mirror node and its gate connected to the drain of the copy transistor. Charge sharing at the mirror node occurs in response to actuation of the switch and the source-follower transistor is turned on in response thereto to discharge the mirror node.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: November 27, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Pasotti, Laura Capecchi, Riccardo Zurla
  • Patent number: 10121532
    Abstract: Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises multiple memory banks. The memory controller further sends a signal specifying that the commands include back-to-back write commands each to access the same memory bank. In response to the signal, the memory device buffers first data of a first write command, wherein the first data is buffered at least until the memory device receives second data of a second write command. Error correction information is calculated for a combination of the first data and second data, and the combination is written to the memory bank. In another embodiment, buffering of the first data and combining of the first data with the second data is performed, based on the signal from the memory controller, in lieu of read-modify-write processing of the first data.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, John B. Halbert
  • Patent number: 10108554
    Abstract: Methods, systems, and apparatuses relating to sharing translation lookaside buffer entries are described. In one embodiment, a processor includes one or more cores to execute a plurality of threads, a translation lookaside buffer comprising a plurality of entries, each entry comprising a virtual address to physical address translation and a plurality of bit positions, and each set bit of the plurality of bit positions in each entry indicating that the virtual address to physical address translation is valid for a respective thread of the plurality of threads, and a memory management circuit to clear all set bits for a thread by asserting a reset command to a respective reset port of the translation lookaside buffer for the thread, wherein the translation lookaside buffer comprises a separate reset port for each of the plurality of threads.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Chung-Lun Chan, Ramon Matas
  • Patent number: 10032507
    Abstract: Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Hieu T. Ngo, Daniel J. Cummings
  • Patent number: 9978445
    Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: May 22, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Sano, Ken Shibata, Shinji Tanaka, Makoto Yabuuchi, Noriaki Maeda
  • Patent number: 9966116
    Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 8, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Harish N. Venkata, Guy S. Perry
  • Patent number: 9886080
    Abstract: A non-volatile memory system may include detection circuitry configured to detect that a host system is configured to initially communicate a clock signal and initialization command signals at a voltage level lower than its input/output driver circuit is configured to receive the signals. In response to the detection, the detection circuitry may switch a regulator circuit from a high voltage mode to a low voltage mode so that the input/output driver circuit is ready to receive the initialization commands at the lower voltage level.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: February 6, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Anil Kumar Thadi Suryaprakash, Krishnamurthy Dhakshinamurthy, Ajay Dhingra, Rampraveen Somasundaram, Narendhiran Chinnaanangur Ravimohan, Bhavin Odedara, Srikanth Bojja, Jayanth Thimmaiah
  • Patent number: 9870820
    Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: January 16, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Hari Giduturi, Mingdong Cui
  • Patent number: 9830993
    Abstract: A storage device includes a nonvolatile memory and a connector configured to connect the storage device to a host. The connector includes a detection terminal that provides a detection voltage to the host, a sensing resistor electrically connected to the detection terminal and having a resistance value that determines the level of the detection voltage, and a power supply terminal that receives a power supply voltage from the host, wherein the power supply voltage is selected by the host in response to the detection voltage.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Phil Kong, Hwa-Seok Oh
  • Patent number: 9824662
    Abstract: The present disclosure provides a Thin Film Transistor Array Substrate and a Liquid Crystal Display apparatus thereof, and relates to the technical field of liquid crystal displaying. The Thin Film Transistor Array Substrate of the present disclosure includes a plurality of gate lines and a plurality of data lines, wherein regions surrounded by the gate lines and the data lines are pixel regions, and wherein a high level common voltage line being used when signal on the data line is at a low level and a low level common voltage lines being used when signal on the data line is at a high level are also arranged in parallel to the gate lines in each of the pixel regions. With the Thin Film Transistor Array Substrate of the present disclosure, the Greenish phenomenon in the existing liquid crystal display apparatus may be effectively solved.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: November 21, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chao Xu, Chunfang Zhang, Yan Wei, Heecheol Kim
  • Patent number: 9817591
    Abstract: A storage device communicating with a host includes a plurality of memory devices and a memory controller. Each of the memory devices includes at least one of a plurality of memory areas that have different storage reliability levels. The memory controller controls the memory devices such that data and required level data associated with a required reliability level of the data are stored in some or all of the memory areas. The data and the required level data are provided from the host. The data is stored in a memory area having a storage reliability level corresponding to the required reliability level from among the memory areas, according to a control of the memory controller.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: November 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jooyoung Hwang
  • Patent number: 9818461
    Abstract: A semiconductor memory device includes a memory cell array; a memory cell array; a data receiver suitable for receiving a plurality of data sequentially inputted from an exterior, the plurality of data including previous data and current data; a data driving controller suitable for detecting the number of toggling values of the current data in comparison with the previous data and generating first to fourth driving control signals based on the number of toggling values; and a driver suitable for receiving input data through the data receiver and driving the input data or inverted input data to data transfer lines in response to the first to fourth driving control signals.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: November 14, 2017
    Assignee: SK Hynix Inc.
    Inventor: Yun-Gi Hong
  • Patent number: 9792998
    Abstract: Systems and methods for detecting program disturb and for programming/reading based on the detected program disturb are disclosed. Program disturb comprises unintentionally programming an unselected section of memory during the program operation of the selected section of memory. To reduce the effect of program disturb, the section of memory is analyzed in a predetermined state (such as the erase state) for program disturb. In response to identifying signs of program disturb, the voltages used to program the section of memory (such as the program verify levels for programming data into the cells of the section of memory) may be adjusted. Likewise, when reading data from the section of memory, the read voltages may be adjusted based on the adjusted voltages used for programming. In this way, using the adjusted programming and reading voltages, the effect of program disturb may be reduced.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: October 17, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Nian Niles Yang, Chris Yip, Grishma Shah
  • Patent number: 9786335
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier coupled to a pair of complementary sense lines, and a compute component coupled to the sense amplifier. The compute component includes a dynamic latch. The sensing circuitry is configured to perform a logical operation and initially store the result in the sense amplifier.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: October 10, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Troy A. Manning
  • Patent number: 9772777
    Abstract: A method and system is provided for improved access to flash memory devices. A system may include a control state module configured to receive memory access commands. The system may further include a plurality of operation sequencer modules configured to execute a pipeline schedule for the performance of the received memory access commands. The pipeline schedule may be configured to enable parallel execution of the memory access commands among a plurality of flash dies of the flash memory. Each of the operation sequencers is associated with one or more of the flash dies.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: September 26, 2017
    Assignee: SOUTHWEST RESEARCH INSTITUTE
    Inventors: Michael A. Koets, Larry T. McDaniel, III, Miles R. Darnell
  • Patent number: 9772936
    Abstract: Methods for programming compressed data to a memory array, memory devices, and memory systems are disclosed. In one such method, memory pages or blocks that are partially programmed with valid data are found. The data is collected from these partially programmed pages or blocks and the data is compressed. The compressed data is then programmed back to different locations in the memory array of the memory device.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: September 26, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Dean Klein
  • Patent number: 9767864
    Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Harish N. Venkata, Guy S. Perry
  • Patent number: 9721665
    Abstract: A data writing method for writing data to a flash memory includes writing an initial value to the data storage area, determining whether or not the writing of the initial value is performed normally based on a write flag, writing data to the data storage area when the writing is performed normally, and erasing a block including the data storage area when the writing is not performed normally. An initial value is written to the data storage area before writing data, so that whether or not an error correction code storage area contains the initial value may be confirmed. An erase operation of the block is performed only when the error correction code storage area does not contain the initial value, so that the number of times of erasure of the block may be reduced and the life of the product may be increased.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: August 1, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: Tetsuhiro Kodama
  • Patent number: 9704563
    Abstract: Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises multiple memory banks. The memory controller further sends a signal specifying that the commands include back-to-back write commands each to access the same memory bank. In response to the signal, the memory device buffers first data of a first write command, wherein the first data is buffered at least until the memory device receives second data of a second write command. Error correction information is calculated for a combination of the first data and second data, and the combination is written to the memory bank. In another embodiment, buffering of the first data and combining of the first data with the second data is performed, based on the signal from the memory controller, in lieu of read-modify-write processing of the first data.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, John B. Halbert
  • Patent number: 9652305
    Abstract: A processor includes an execution unit to execute instructions and a scheduler unit to store a queue of instructions for execution by the execution unit. The scheduler unit includes a wake array including a plurality of source slots to store source identifiers for sources associated with the instructions, a picker to schedule a particular instruction for execution in the execution unit, broadcast a destination identifier associated with the particular instruction to a first subset of the source slots, and a delay element to receive the destination identifier broadcast by the picker and communicate a delayed version of the destination identifier to a second subset of the source slots different from the first subset.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: May 16, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srikanth Arekapudi, Emil Talpes, Sahil Arora
  • Patent number: 9612954
    Abstract: Non-volatile memory array can be recovered after a power loss. In one example, pages of a memory array are scanned to find a first free page after the power loss. The first free page is marked as available, and the page marked as available is written to with the next write cycle.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: April 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Edgington, Hisham Chowdhury
  • Patent number: 9548106
    Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: January 17, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Sano, Ken Shibata, Shinji Tanaka, Makoto Yabuuchi, Noriaki Maeda
  • Patent number: 9536585
    Abstract: The present invention provides an improved SRAM memory cell based on a DICE structure, which comprises following structures: four inverter structures formed through arranging PMOS transistors and NMOS transistors in series, wherein the part between the drains of a PMOS transistor and an NMOS transistor serves as a storage node; each storage node controls the gate voltage of an NMOS transistor of the other inverter structure and of a PMOS transistor of another inverter structure; a transmission structure consisting of four NMOS transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: January 3, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Mengxin Liu, Xin Liu, Fazhan Zhao, Zhengsheng Han
  • Patent number: 9496028
    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 15, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Shigeki Obayashi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
  • Patent number: 9489299
    Abstract: A data storage device includes a memory and a controller. Mapping circuitry is configured to apply a mapping to received data to generate mapped data to be stored into the memory. The mapping is configured to reduce an average number of state changes of storage elements per write operation and is independent of the states of the storage elements prior to the writing of the mapped data.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: November 8, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Menahem Lasser
  • Patent number: 9484117
    Abstract: A semiconductor memory device having a compression test mode is provided. The semiconductor memory device comprises a memory unit, i test pads, a timing circuit, a compression circuit, and a signal distribution circuit. The memory unit comprises m memory banks divided into n activating groups, wherein each bank comprises a plurality of sensing amplifiers for sensing and amplifying data in bit lines. The timing circuit sequentially generates n control signals each for activating a plurality of sensing amplifiers in one of the n activating groups. The compression circuit compresses data sensed and amplified by the plurality of sensing amplifiers in each bank in a compression test mode. The signal distribution circuit distributes signals output from the compression circuit among the i data pads in rotation. The integer n and the integer i are adjustable.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: November 1, 2016
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Jen-Shou Hsu
  • Patent number: 9455008
    Abstract: A semiconductor apparatus includes a plurality of memory blocks divided into an even mat group and an odd mat group; and an active control block configured to activate any one group of the even mat group and the odd mat group at a first timing in response to a plurality of test signals, and activate the other group at a second timing.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: September 27, 2016
    Assignee: SK hynix Inc.
    Inventor: Don Hyun Choi
  • Patent number: 9418752
    Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Shantanu R Rajwade, Pranav Kalavade, Neal R Mielke, Krishna K Parat, Shyam Sunder Raghunathan
  • Patent number: 9396143
    Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: July 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan