Abstract: A storage device includes a memory and a controller. The controller controls the memory such that, in response to a request for a first read operation on the memory while a first write operation is performed on the memory, the first write operation is suspended, and the first read operation is performed, the suspended first write operation is resumed after the first read operation is completed, and second write operation subsequent to the first write operation is performed on the memory after the resumed first write operation is completed. The controller throttles an amount of data communicated to the memory device for the second write operation or for a second read operation subsequent to the first read operation, based on a frequency that the first write operation is suspended.

Abstract: A first impedance calibration part configured to perform a first impedance calibration operation of generating a first impedance calibration code set for adjusting an impedance of a first terminating resistor to a first target value, with reference to an external resistor having a first resistance value. A second impedance calibration part configured to perform a second impedance calibration operation of generating a second impedance calibration code set for adjusting an impedance of a second terminating resistor to a second target value, with reference to a reference resistance unit, a resistance value of which is set to a second resistance value according to a part of the first impedance calibration code set.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.

Abstract: A semiconductor memory device includes a first pad, a clock generation circuit configured to generate a first clock, an output circuit configured to output the first clock through the first pad, a designation circuit configured to designate one of a plurality of contiguous times slots, each of which is set with respect to clock cycles of the first clock, and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot.

Abstract: An imaging device in which noise can be reduced, and an electronic device using this device. The imaging device includes a light receiving element, and a read circuit. A field effect transistor in the read circuit has a semiconductor layer in which a channel is formed, a gate electrode that covers the semiconductor layer, and a gate insulating film disposed between the semiconductor layer and the gate electrode. The semiconductor layer has a main surface, and a first side surface on one end side of the main surface in a gate width direction of the field effect transistor. The gate electrode has a first portion that faces the main surface via the gate insulating film, and a second portion that faces the first side surface via the gate insulating film. A crystal plane of the first side surface is a plane or a plane equivalent to the plane.

Abstract: Methods, systems, and devices for techniques for initializing memory error correction are described. A memory system may perform operations relating to writing data to multiple memory cells belonging to one or more rows of the memory system in response to a single write command. For example, the memory system may receive (e.g., from a host system) an activation command (e.g., a row group activation command) indicating a row group address. The memory system may activate a set of rows indicated by the row group address. In response to a write command (e.g., a row group write command), the memory system may write data in a respective memory cell of each row indicated by the row group address. For example, each memory cell to be written may correspond to a column address included in the write command. The memory system may write a same logic state to each memory cell.

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

Abstract: A method for resetting an array of RAM cells by applying a sequence of N reset operations, the method including at a first reset operation, defining a first reset technique and performing the first reset operation; at a j-th reset operation of a N?1 subsequent reset operations, j being an integer between 2 and N, if a correction yield of the reset technique used at the (j?1)-th reset operation fulfils a predefined condition, applying the reset technique used at the (j?1)-th reset operation to perform the j-th reset operation, if the correction yield does not fulfil the predefined condition, defining a new reset technique and applying the new reset technique to perform the j-th reset operation, the correction yield being a cumulative correction yield or a relative correction yield, the correction yield for the N reset operations being measured prior to the first reset operation.

Abstract: A resistive random-access memory (ReRAM) cell includes a field-effect transistor (FET) and a resistive element. The FET having a gate port, a drain port, and a source port. The gate port is connected to a word-line (WL) of the ReRAM cell, the source port is connected to a bit-line (BL) of the ReRAM cell, and a first port of the resistive element is connected to the drain of the FET. A second port of the resistive element is connected to a source-line (SL) of the ReRAM cell. During reset operation SL is connected to a high-voltage and BL to a low-voltage. During set operation SL is connected to a low-voltage and BL to a high-voltage. Using this common source configuration overcomes the requirement for a wider FET width of the prior art so as to accommodate the current supply needed during reset operation, and avoids overstressing of the FET.

Abstract: A first address bus may be located in an upper layer of an integrated circuit that is associated with a memory and a memory controller. The first address bus may receive a first portion of a memory address. A second address bus may be located in a lower layer of the integrated circuit where the second address bus is to receive a second portion of the memory address. Furthermore, a data bus may be located in an intermediate layer where the data bus is to receive data corresponding to the memory address from the memory and may transmit the data to the memory controller. The intermediate layer may be between the upper layer and the lower layer. A layout of the signals of the data bus may vertically overlap with a layout of signals of the first address bus and a layout of signals of the second address bus.

Abstract: A lead-free metallic halide memristor is disclosed. The lead-free metallic halide memristor comprises a first electrode layer, an active layer and a second electrode layer, of which the active layer is made of a metallic halide material. Experimental data have proved that the lead-free metallic halide memristor possesses synaptic plasticity because of showing characteristics of short-term potentiation, short-term depression, long-term potentiation, long-term depression during the experiments. Therefore, the lead-free metallic halide memristor has significant potential for being used as an artificial synaptic element so as to be further applied in the manufacture of a reservoir computing chip.

Abstract: A semiconductor memory device implements a write disturb reduction method to reduce write disturb on unselected memory cells by alternating the order of the write logical “1” step and write logical “0” step in the write operations of selected memory cells associated with the same group of bit lines. In one embodiment, a method in an array of memory cells includes performing write operation on the memory cells in one of the memory pages to store write data into the memory cells where the write operation includes a first write step of writing a data of a first logical state and a second write step of writing data of a second logical state; and performing the write operation for each row of memory cells by alternately performing the first write step followed by the second write step and performing the second write step followed by the first write step.

Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.

Abstract: In a Coarse-Grained Reconfigurable Architecture (CGRA) system, two configuration files are used. The CGRA system has an array of configurable units that includes a plurality of switches, a print configurable unit, a source configurable unit, and one or more sink configurable units, The first configuration file, upon being executed by the CGRA system, configures the CGRA system to send output data directly from the source configurable unit to the one or more sink configurable units through the plurality of switches. The second configuration file, upon being executed into the CGRA system, configures the CGRA system to send the output data from the source configurable unit to the print configurable unit through the plurality of switches, send the output data from the print configurable unit to both a memory that is accessible by a host computing unit, and the one or more sink configurable units.

Abstract: Various implementations described herein are related to a device having multiple transistors in a single stack arranged as a cross-coupled bitcell latch. Also, the multiple transistors may be disposed in a multi-transistor stack configuration that is formed within a single monolithic semiconductor die. In some implementations, the multiple transistors may be arranged as a bitcell for single-port memory applications.

Abstract: A memory device includes a memory block, peripheral circuit, and control logic. The memory block includes a plurality of pages coupled to a plurality of word lines, respectively. The peripheral circuit is configured to perform a program loop including a program pulse operation of applying a program voltage to a selected word line, and a verify operation of applying at least one verify voltage corresponding to the program voltage to the selected word line and applying a verify pass voltage to unselected word lines. The control logic is configured to increase a level of the verify pass voltage applied to at least one unselected word line among the unselected word lines whenever the peripheral circuit performs the next program loop when threshold voltages of memory cells included in a page coupled to the selected word line are greater than a reference level.

Abstract: Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that represents a subset or superset of memory cells in a nominal page size for the array. For example, memory cells associated with a page size of a memory array may be accessed with commands to a memory array. Each command may contain a particular addressing scheme based on the page size of the memory array and may activate one or more sets of memory cells within the array. The addressing scheme may be modified based on the page size of the memory array. Upon activating a desired set of memory cells, one or more individual activated cells may be accessed.

Abstract: A semiconductor memory device includes a memory cell array, a page buffer, and control logic. The memory cell array includes a plurality of memory cells for storing data. The page buffer is coupled to at least one memory cell among the plurality of memory cells through a bit line and is configured to store data in the at least one memory cell. The control logic is configured to control an operation of the page buffer. The page buffer includes a first transistor coupled between the bit line and a first node, a second transistor coupled between the bit line and an external power voltage terminal, and an internal operation circuit coupled to the first node.

Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. A configuration unload controller connected to the bus system, including logic to execute an array configuration unload process, including distributing a command to a plurality of the configurable units in the array to unload the unit files particular to the corresponding configurable units, the unit files each comprising a plurality of ordered sub-files, receiving sub-files via the bus system from the array of configurable units, and assembling an unload configuration file by arranging the received sub-files in memory according to the configurable unit of the unit file of which the sub-file is a part, and the order of the sub-file in the unit file.

Abstract: A field programmable gate array (FPGA) utilizing resistive switching memory technology is described. The FPGA can comprise a switching block interconnect having a set of signal input lines and a set of signal output lines. Respective intersections of the signal input lines and signal output lines can have two resistive switching memory cells, a current differential latch, and a switching transistor (also referred to as a pass gate transistor) arranged in a circuit. Resistance states of the resistive switching memory cells can be programmed to control an output voltage state of the current differential latch. The output voltage state is latched into the current differential latch which can drive a gate of the switching transistor to activate or deactivate the switching transistor, which in turn activates or deactivates an intersection of the FPGA.

Abstract: Methods, systems, and devices for cache management in a memory subsystem are described. An interface controller may include a first buffer and a second buffer. The interface controller may use the first and second buffers to facilitate operating a volatile memory as a cache for a non-volatile memory. During an access operation, the interface controller may use the buffer to transfer data between the volatile memory, non-volatile memory, and another device. In response to the access operation, the interface controller may use the second buffer to transfer second data from the volatile memory to the non-volatile memory.

Abstract: Disclosed is a nonvolatile memory, which includes a plurality of input/output pads connectable to a plurality of data lines, an enable input pad, an enable output pad, and a chip address initialization circuit. The chip address initialization circuit receives a current chip address through the plurality of input/output pads, stores the current chip address in response to a current enable signal received through the enable input pad, outputs a next enable signal through the enable output pad, and outputs a next chip address through the plurality of input/output pads.

Abstract: An imaging device in which noise can be reduced, and an electronic device using this device. The imaging device includes a light receiving element, and a read circuit. A field effect transistor in the read circuit has a semiconductor layer in which a channel is formed, a gate electrode that covers the semiconductor layer, and a gate insulating film disposed between the semiconductor layer and the gate electrode. The semiconductor layer has a main surface, and a first side surface on one end side of the main surface in a gate width direction of the field effect transistor. The gate electrode has a first portion that faces the main surface via the gate insulating film, and a second portion that faces the first side surface via the gate insulating film. A crystal plane of the first side surface is a plane or a plane equivalent to the plane.

Abstract: A memory device and an operation method thereof are provided. The memory device includes memory cells, each having a static random access memory (SRAM) cell and a non-volatile memory cell. The SRAM cell is configured to store complementary data at first and second storage nodes. The non-volatile memory cell is configured to replicate and retain the complementary data before the SRAM cell loses power supply, and to rewrite the replicated data to the first and second storage nodes of the SRAM cell after the power supply of the SRAM cell is restored.

Abstract: Apparatuses and methods related to an artificial intelligence accelerator in memory are disclosed. An apparatus can include a number of registers configured to enable the apparatus to operate in an artificial intelligence mode to perform artificial intelligence operations and an artificial intelligence (AI) accelerator configured to perform the artificial intelligence operations using the data stored in the number of memory arrays. The AI accelerator can include hardware, software, and or firmware that is configured to perform operations associated with AI operations. The hardware can include circuitry configured as an adder and/or multiplier to perform operations, such as logic operations, associated with AI operations.

Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

Abstract: A memory device including an interface to receive one or more clock signals and one or more data signal a dual-sensing stage dual-tail latch arranged at the interface. The dual-sensing stage dual-tail latch includes a sensing stage to sense a differential voltage between a first signal and a second signal and to provide a first differential voltage output and a second differential voltage output to a first node and a second node, respectively. The dual-sensing stage dual-tail latch includes a complimentary sensing stage arranged in parallel with the sensing stage and to sense the differential voltage between the first signal and the second signal, where a first complimentary differential output voltage and a second complimentary differential output of the complimentary sensing stage are coupled to the first node and the second node. The dual-sensing stage dual-tail latch includes a latch stage to receive the outputs from the first node and the second node.

Abstract: A circuit includes first and second bit lines, a second power node having a voltage level below that of a first power node, a reference node having a reference voltage level, first and second pass gates and drivers, first and second logic gates coupled to the second power node, first and second conversion circuits coupled between the first power node and respective first and second logic and pass gates, and first and second NOR gates coupled between the second power node and respective first and second logic gates and drivers. The first and second pass gates selectively couple the first and second bit lines to the first power node responsive to the respective second and first logic gates and conversion circuits, and the first and second drivers selectively couple the first and second bit lines to the reference node responsive to the respective first and second logic and NOR gates.

Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more

Abstract: A memory device includes a memory array having a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction. The memory array also includes a plurality of write assist cells connected to the plurality of memory cells. At least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of memory cells in a same column.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2N levels, where N is an integer greater than 1. The level corresponds to one of 2N pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a row of target memory cells, such that each of the row of target memory cells is programmed into one of 2N/m intermediate levels based on the piece of N-bits data to be stored in the target memory cell, where m is an integer greater than 1. The peripheral circuit is also configured to program, in a second pass after the first pass, the row of target memory cells, such that each target memory cell is programmed into one of the 2N levels based on the piece of N-bits data to be stored in the target memory cell.

Abstract: Various implementations described herein refer to an integrated circuit having a first memory structure and a second memory structure. The first memory structure is disposed in a first area of the integrated circuit, and the first memory structure has first memory cells with first transistors. The second memory structure is disposed in a second area of the integrated circuit that is different than the first area, and the second memory structure has second memory cells with second transistors that are separate from the first transistors. The second transistors of the second memory cells are arranged to provide an output oscillating frequency for detecting variation of performance of the first transistors of the first memory cells.

Abstract: A circuit includes a tracking word line, a power switch, a tracking bit line, a sense circuit. The power switch is coupled between the tracking word line and a first node. The power switch is configured to discharge a voltage level on the first node in response to a clock pulse signal transmitted through the tracking word line to the power switch. The tracking bit line is coupled between the first node and a plurality of tracking cells in a memory array. The sense circuit is coupled between the first node and a second node. The sense circuit is configured to generate a negative bit line enable signal in response to that the voltage level on the first node is below a threshold voltage value of the sense circuit.

Abstract: A chip, a self-calibration circuit and method for chip parameter offset upon power-up are disclosed. The circuit includes a counting circuit, a calibration data latch circuit, a calibration data selection circuit and a parameter calibration circuit. The counting circuit outputs a sequentially scanned counting signal when receiving a valid enabling signal. The calibration data latch circuit latches the counting signal when receiving a valid latch signal. The calibration data selection circuit selects the counting signal latched by the calibration data latch circuit as a calibration signal when receiving the valid latch signal, otherwise selects the counting signal currently outputted as the calibration signal. The parameter calibration circuit implements a parameter calibration based on the calibration signal in a calibration mode, while outputs the valid latch signal when the parameter calibration satisfies a preset requirement.

Abstract: A writing method for a non-volatile memory device includes; performing a sensing operation, comparing write data with read data retrieved by the sensing operation, determining whether the write data is set state when the write data and the read data are the same, performing a set operation when the write data is set state, and not performing a write operation when the write data is not set data.

Abstract: A non-destructive memory array implements a full adder. The array includes a column connected by a bit line and a full adder unit. The column stores a first bit in a first row of the bit line, a second bit in a second row of the bit line, and an inverse of a carry-in bit in a third row of the bit line. The full adder unit stores, in the second and third rows of the bit line, a sum bit and a carry out bit output, respectively, of adding the first bit, the second bit and the carry-in bit. The full adder unit does not overwrite any of the bits when a full adder table indicates that the sum bit and the carry out bit are equivalent to the second bit and the carry-in bit.

Abstract: A timing generator, a timing generating method and an associated control chip are provided, wherein the timing generator includes a receiving circuit, a transmitting circuit coupled to the receiving circuit, and a control unit respectively coupled to the receiving circuit and the transmitting circuit. The receiving circuit may be configured to receive a timing data set from a storage device. The transmitting circuit may be configured to select a specific signal type within multiple signal types according to the timing data set, and output an output signal having the specific signal type with a specific time length, wherein the timing data set indicates the specific signal type and the specific time length. The control unit may be configured to control operations of the receiving circuit and the transmitting circuit.

Abstract: Structures including non-volatile memory elements and methods of forming such structures. The structure includes a first non-volatile memory element, a second non-volatile memory element, and temperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element.

Abstract: A memory device includes: first power pins in a first power area and configured to receive a first power voltage; data pins configured to transmit or receive data signals, the data pins being arranged in a first region and in a second region each including the first power area; control pins configured to transmit or receive control signals in the first region and in the second region; second power pins in a second power area between the first region and the second region and configured to receive a second power voltage different from the first power voltage; and ground pins in the second power area and configured to receive a ground voltage.

Abstract: Disclosed herein are related to an integrated circuit including a semiconductor layer. In one aspect, the semiconductor layer includes a first region, a second region, and a third region. The first region may include a circuit array, and the second region may include a set of interface circuits to operate the circuit array. A side of the first region may face a first side of the second region along a first direction. The third region may include a set of header circuits to provide power to the set of interface circuits through metal rails extending along a second direction. A side of the third region may face a second side of the second region along the second direction. In one aspect, the first side extending along the second direction is shorter than the second side extending along the first direction, and the metal rails are shorter than the first side.

Abstract: A memory storage apparatus including a memory circuit and a memory controller is provided. The memory circuit is configured to store data. The memory controller is coupled to the memory circuit via a data bus. The memory controller performs initial setting of the memory circuit on the basis of a width of the data bus. In addition, an operating method of a memory storage apparatus is also provided.

Abstract: A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.

Abstract: The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

Abstract: Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Abstract: To provide a data processing system that includes a nonvolatile memory device capable of storing multilevel data and enables increasing storage capacity of a main memory device when the data processing system is activated. The data processing system includes an arithmetic processing device, a main memory device, and a nonvolatile memory device. The main memory device includes a volatile memory device, and the nonvolatile memory device is configured to store multilevel data in one memory cell. When the data processing system is deactivated, the nonvolatile memory device stores binary data, whereby the stored data can be held for a long time. Upon activation, the nonvolatile memory device stores multilevel data, whereby increasing storage capacity. When the storage capacity is increased, a free space is generated in the nonvolatile memory device, which can be used as a part of the main memory device of the data processing system.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a Zener diode, a first current source, a first n-type field effect transistor (FET), a first inverter circuit, and a second current source. The Zener diode has a cathode coupled to a first node and an anode coupled to a second node. The first current source has a first terminal coupled to the second node and a second terminal coupled to a ground terminal. The first n-type FET has a gate terminal coupled to the second node, a source terminal coupled to the ground terminal, and a drain terminal coupled to a third node. The first inverter circuit has an input coupled to the third node and an output coupled to a fourth node. The second current source has a first terminal coupled to a fifth node and a second terminal coupled to the third node.

Abstract: An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the Aoutput of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.

Abstract: A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data.