Abstract: A voltage switch circuit includes four transistors. The four transistors may be transistors used to build logic gates. The operation of the voltage switch circuit may include precharging the output terminal of the voltage switch circuit, conditioning of the voltage switch circuit and boosting the voltage of the output terminal.

Abstract: A system, method, and computer program product are provided for extending a lifetime of memory. In operation, spare space in memory is increased. Additionally, a lifetime of the memory is extended, as a result of increasing the spare space in the memory.

Abstract: An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier.

Abstract: A semiconductor device includes a bit line connected to memory cells, a negative bias voltage generation circuit generating a negative bias voltage that is to be applied to the bit line during writing, and a negative bias reference voltage generation unit generating a negative bias reference voltage based on a resistance ratio between a first resistor and a second resistor.

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Abstract: A data transmission circuit includes an input line selection unit configured to transfer data of a selected input line among a plurality of input lines to an output line, a data sensing unit connected to the plurality of input lines and configured to sense the data of the selected input line, and a data amplification unit configured to amplify data of the output line in response to a data sensing result of the data sensing unit.

Abstract: A data writing method for writing data to a flash memory includes writing an initial value to the data storage area, determining whether or not the writing of the initial value is performed normally based on a write flag, writing data to the data storage area when the writing is performed normally, and erasing a block including the data storage area when the writing is not performed normally. An initial value is written to the data storage area before writing data, so that whether or not an error correction code storage area contains the initial value may be confirmed. An erase operation of the block is performed only when the error correction code storage area does not contain the initial value, so that the number of times of erasure of the block may be reduced and the life of the product may be increased.

Abstract: A nonvolatile memory device includes a first memory region and a second memory region. The nonvolatile memory device is programmed by storing program data in the first memory region, performing coarse programming and fine programming to store the program data in the second memory region, and in response to a read request, accessing the program data from the first memory region or the second memory region according to a fine program flag indicating whether the coarse programming has been completed.

Abstract: A data storage device includes a write protection data structure that includes a first set of entries corresponding to a first set of ranges of memory addresses. A first indication stored in an entry, in the first set of entries, corresponds to an absence of write-protected data between a lowest address of the range of addresses corresponding to the entry and a highest address of a memory. A second indication stored in the entry corresponds to write-protected data within the range of addresses. The data storage device also includes a write protection map that includes a second set of entries corresponding to a second set of ranges of the memory addresses. The device is configured to locate, in the write protection data structure, an entry corresponding to a range of memory addresses.

Abstract: A semiconductor memory device, including a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells coupled to the plurality of word lines and the plurality of pairs of bit lines, a plurality of sense amplifiers each coupled between a corresponding pair of bit lines, a plurality of first driver transistors coupled between the plurality of sense amplifiers and a first power supply line, a plurality of second driver transistors coupled between the plurality of sense amplifiers and a second power supply line, a pair of common data lines, and a plurality of column selection gates each coupled between the corresponding pair of bit lines and the pair of common data lines, wherein the number of the first driver transistors is more than the number of the second driver transistor.

Abstract: An electronic device includes a non-volatile memory having a plurality of memory cells, a memory controller, and an evaluator. The memory controller is configured to provide control signals to the non-volatile memory causing the non-volatile memory, or a selected memory section of the non-volatile memory, to be in one of a read state and a weak erase state, wherein the weak erase state causes the plurality of memory cells to maintain different states depending on different physical properties of the plurality of memory cells. The evaluator is configured to read out the plurality of memory cells and to provide a readout pattern during the read state, wherein the readout pattern that is provided after a preceding weak erase state corresponds to a physically unclonable function (PUF) response of the electronic device uniquely identifying the electronic device.

Abstract: A data processing apparatus includes: an instruction execution section; an instruction protection information storage section that stores instruction protection information for specifying at least one partial address space in an instruction address space for storing instructions executed by the instruction execution section; a data protection information storage section that stores data protection information for specifying multiple partial address spaces in a data address space for storing operands for use in an operation of the instruction execution section; and a protection violation determination section that determines whether to permit access from the instruction execution section based on setting of the instruction and data protection information storage sections.

Abstract: A circuit comprises a first memory cell, a second memory cell, and a disturb control circuit. The first memory cell has a first port and a second port. The first port is associated with a first write assist circuit. The second port is associated with a second write assist circuit. The second memory cell has a third port and a fourth port. The third port is associated with a third write assist circuit. The fourth port is associated with a fourth write assist circuit. The disturb control circuit is configured to selectively turn on at least one of the first write assist circuit, the second write assist circuit, the third write assist circuit, or the fourth write assist circuit according to whether the first port, the second port, the third port, or the fourth port is determined to be write disturbed.

Abstract: An electronic circuit and a method for driving data writes to an SRAM bit cell in an electronic circuit. The electronic circuit translates a first write signal in a lower voltage domain to a second write signal in a higher voltage domain. Based, at least in part, on the second write signal, the electronic circuit controls a discharge of a voltage of a data write line to a ground voltage level. The electronic circuit provides a negative voltage boost to the data write line after the voltage of the data write line has been discharged to reach or exceed a threshold value relative to the ground voltage level.

Abstract: Passive write assist passively improves SRAM performance (e.g., write margin speed) while reducing manufacturing costs (e.g., die area, packaging) and operating costs (e.g., power consumption, cooling) associated with active write assist schemes. Passive write assist may be implemented in peripheral circuitry or embedded in an SRAM array or even in each array cell or bitcell. For example, one or more memory cells may be converted to provide passive write assist to a plurality of other memory cells. As another example, each memory cell may independently implement passive write assist using one or more high resistive contacts to couple to the array power supply, resulting in the array voltage level being changed by different amounts in different memory cells according to cell variations.

Abstract: A semiconductor memory device includes a writing circuit and a reading circuit. The writing circuit executes a setting action for converting a resistance of a variable resistance element to a low resistance by applying current from one end side to the other end side of a memory cell via the variable resistance element, and a resetting action for converting the resistance to a high resistance by applying current from the other end side to the one end side via the variable resistance element. The reading circuit executes a first reading action for reading a resistance state of the variable resistance element by applying current from one end side to the other end side of the memory cell via the variable resistance element, and a second reading action for reading the resistance state by applying current from the other end side to the one end side via the variable resistance element.

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Abstract: An integrated circuit that includes an array of memory cells and an array of write logic cells. The integrated circuit also includes a write address decoder comprising a plurality of write outputs. The array of write logic cells is electrically connected to the plurality of write outputs. The array of write logic cells is electrically connected to the array of memory cells. The array of write logic cells is configured to set an operating voltage of the memory cells.

Abstract: The invention pertains to the field of the beverage preparation machines, and more particularly to a capsule adapted for delivering a beverage in a beverage producing device comprising: a storage having a memory space for storing information related to preferences of a user of the beverage producing device; a first communication interface configured to: write in the memory space the information related to the preferences of the user, received on the first communication interface; and, allow the reading of the information stored in the memory space.

Abstract: A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a second port. The first data is written from the first port to the first memory cell. The second data is based on information of the first data. The second port is configured to write the second data to the first memory cell based on a detection of a write disturb caused by the second port to the first port.

Abstract: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.

Abstract: A method for controlling data write operation of a mass storage device is provided. The mass storage device has a controller and a memory unit. The method includes connecting the mass storage device to a host device, and receiving a voltage provided from the host device; sensing and monitoring whether the voltage is lower than a first predefined voltage; writing data to the mass storage device with a first frequency when the sensed voltage is higher than the first predefined voltage; and writing data to the mass storage device with a second frequency when the sensed voltage is lower than the first predefined voltage, wherein the second frequency is adjusted by decreasing the first frequency.

Abstract: Circuitry and method for detecting occurrence of a reflow process to an embedded storage device are disclosed. A temperature sensing device includes a resistor, a temperature sensor, and a comparator. The first terminal of the resistor is coupled to a voltage source, and the second terminal of the resistor is coupled to both the first terminal of the temperature sensor and the first input of the comparator. The second terminal of the temperature sensor is grounded and the second input of the comparator is coupled to a reference voltage. The resistance state of the temperature sensor changes from a first resistance state to a second resistance state when the temperature surrounding the temperature sensor reaches a threshold. The comparator generates an output based on the resistance changes of the temperature sensor. The generated output may indicate whether a reflow process has occurred to the embedded storage device.

Abstract: A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal.

Abstract: A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddMlower to the bit cell core as well as to at least one of the local write bitline (lwbl) and local write bitline bar (lwblb). Additionally, the write assist driver circuit may also provide a periphery supply voltage VddP to a local write wordline (lwwl), where VddP?VddM>VddMlower.

Abstract: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

Abstract: Methods for programming memory cells. One such method for programming memory cells includes generating an encoded stream using a data stream and programming the memory cells using the encoded stream to represent the data stream. A particular bit position of the encoded stream has a first voltage level when the particular bit position of the data stream has a particular logical state, and the particular bit position of the encoded stream has either a second voltage level or a third voltage level when the particular bit position of the data stream has a logical state other than the particular logical state.

Abstract: A data write circuit of a semiconductor apparatus includes a data path configured to receive a pattern signal and generate a first delayed pattern signal; a data strobe signal path configured to receive the pattern signal and generate a second delayed pattern signal; a data latch block configured to latch the first delayed pattern signal in response to the second delayed pattern signal, and output a resultant signal; and a control block configured to generate the pattern signal, and vary a delay time of the data path according to a result of comparing phases of a latched signal of the data latch block and the pattern signal.

Abstract: A memory device can include a plurality of programmable impedance elements programmable between a low impedance state in response to a program voltage and a higher impedance state in response to an erase voltage having a different polarity than the program voltage; a programming circuit configured to apply the program and erase voltages to selected elements; and a pre-condition path configured to apply a pre-condition voltage only of the erase voltage polarity to fresh elements in a pre-condition operation; wherein fresh elements are elements that have not been subject to any programming voltages. The pre-condition electrical conditions can also include high voltage low current conditions that apply a greater magnitude voltage and smaller current than the first or second electrical conditions, or high voltage low current conditions that apply a greater magnitude voltage and greater current than the first or second electrical conditions.

Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.

Abstract: A data training device includes a training control block configured to activate driving signals for driving a bit line sense amplifier, with a word line deactivated, when a write training operation is performed according to a mode register write command; and the bit line sense amplifier configured to store training data according to the driving signals from the training control block.

Abstract: Disclosed is a method of controlling a semiconductor memory device including a write driver. A method of controlling a phase change memory device includes turning on switches connected to a global bit line and a local bit line, respectively, enabling a write driver connected to the switches, enabling a word line, and enabling a memory cell to be accessed by the word line, wherein control is performed so that electric charges supplied from the write driver through the switches are charged when the write driver is enabled.

Abstract: A nonvolatile semiconductor memory device according to the embodiment includes a memory cell array including memory cells; and a data write unit, the memory cells including a first selected memory cell defined for a memory cell targeted to data write, a second selected memory cell defined for a memory cell targeted to the data write next to the first selected memory cell, and non-selected memory cells defined for other memory cells, and the data write unit, at the time of write operation to the first selected memory cell, providing the second selected memory cell with a first non-selection electric pulse having electric energy within a range causing no change in the physical state of a memory element, and providing the non-selected memory cells with a second non-selection electric pulse having smaller electric energy than the first non-selection electric pulse.

Abstract: The present disclosure relates to a method and system for controlling memory access. In particular, a method for controlling memory access includes, in response to receiving a write request operative to write data to at least one memory cell of a plurality of memory cells, increasing a word line voltage above a nominal level after a predetermined delay following the receipt of the write request. A disclosed system includes a word line driver operative to increase a word line voltage above a nominal level during a write access after a predetermined delay in response to a write request.

Abstract: According to one embodiment, a non-volatile semiconductor storage device includes a memory cell array, a row decoder, a potential generating circuit, first plural potential selection circuits, a second potential selection circuit, a first discharge circuit, and a second discharge circuit. The first plural potential selection circuits select one of output potentials of the potential generating circuit by receiving a first control signal and apply the selected output potential to a first signal line. The second potential selection circuit applies a potential of the first signal line to a second signal line connected to the row decoder by receiving a second control signal. The first discharge circuit is arranged in the first potential selection circuit. The second discharge circuit is arranged in the second potential selection circuit.

Abstract: A method for limiting writing of data to a specific memory cell without disconnecting a wiring of a memory cell array or placing a prober in contact with a memory cell, a row, or a column is provided. Row address data and column address data of a memory cell to which data cannot be written are stored in a register. Enable data which controls data writing is stored in the register. Next, in order to write data to a memory cell, row address data and column address data of a memory cell to which data is written, writing enable data, and the like are output from a logic circuit; thus, writing of data to a memory cell corresponding to the address data stored in the register is inhibited.

Abstract: A memory system, and an operation method of a nonvolatile memory, include programming memory cells using a normal program pulse, reading out a first set of data from the memory cells, detecting failed cells based on the first set of data, storing information about the failed cells in a buffer, and reprogramming the failed cells using a reinforced program pulse in an idle state based on the information stored in the buffer.

Abstract: Methods and apparatuses for reduction of Read Disturb errors in a memory system utilizing modified or extra memory cells.

Abstract: Methods and apparatus for programming memory cells in a memory array are disclosed. A most recent programming time is determined, the most recent programming time being a time when a most recent programming operation was applied to a reference memory cell in the memory array. A programming signal is then applied to a target memory cell in the memory array, the programming signal having a programming parameter which depends at least in part on the most recent programming time.

Abstract: A circuit for programming a resistive switching device includes a resistive switching device characterized by a programmable resistance, the resistive switching device comprising a first terminal, a second terminal, and a resistive switching element, a first circuit configured to supply a programming voltage to the resistive switching device and to supply a predetermined current to flow in the resistive switching device, and a second circuit coupled to the first circuit and to the resistive switching device, wherein the second circuit is configured to terminate the supply of the programming voltage to the resistive switching device when the predetermined current flows in the resistive switching device.

Abstract: Driving methods of a nonvolatile memory device are provided. The driving method includes providing a start pulse adjusted based on a previous write operation to a resistive memory cell to write data, verifying whether the data has accurately been written using the start pulse, and executing a write operation on the resistive memory cell by an incremental one-way write method or a decremental one-way write method according to the verify result. Related nonvolatile memory devices are also provided.

Abstract: A semiconductor device including an internal command generator and a bias generator is provided. The internal command generator generates first to fourth internal command signals sequentially enabled in synchronization with pulses of an external program signal. The first internal command signal controls a read operation for reading out data stored in memory cells, and the second and third internal command signals control a program operation for programming the memory cells. The bias generator generates a read bias signal for controlling a level of an output voltage signal, which is applied to an internal circuit, in response to the first and fourth internal command signals.

Abstract: An integrated includes a dual port memory cell such as a SRAM cell. A first port dummy read recovery block couples the first port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the second port bit line, and couples the first port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the second port complementary bit line. A second port dummy read recovery block couples the second port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the first port bit line, and couples the second port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the first port complementary bit line.

Abstract: Integrated circuit memory devices include a memory cell configured to receive a power supply signal and a write assist circuit. The write assist circuit is configured to improve write margins by reducing a magnitude of the power supply signal supplied to the memory cell from a first voltage level to a lower second voltage level during an operation to write data into the memory cell. The memory device further includes at least one bit line electrically coupled to the memory cell and a read assist circuit. The read assist circuit may be configured to improve read reliability by partially discharging the at least one bit line from an already precharged voltage level to a lower third voltage level in preparation to read data from the memory cell.

Abstract: Provided is a semiconductor memory device in which a plurality of first and second data lines coupled to a memory cell array are alternately arranged. The semiconductor memory device includes a first write driving circuit configured to load a plurality of first write data transmitted through a plurality of third data lines into the plurality of first data lines in response to a first write enable signal; a second write driving circuit configured to load a plurality of second write data transmitted through a plurality of fourth data lines into the plurality of second data lines in response to a second write enable signal; and a column control circuit configured to activate at least one of the first and second write enable signals during a given period, in response to a plurality of data width option modes, during a parallel test mode.

Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

Abstract: A semiconductor integrated circuit includes a write path coupled to a pad, a read path coupled to the pad, and a reference voltage output control block configured to apply a reference voltage to the pad through the write path in response to a reference voltage monitoring signal. The read path is electrically isolated from the pad in response to the reference voltage monitoring signal.

Abstract: Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals.

Abstract: Embodiments of the present invention provide a method and a device for writing data. The method includes: receiving a data block that is to be written in an EDRAM; obtaining, according to a status of a bank in the EDRAM, usable addresses corresponding to usable banks in the EDRAM; selecting an address from the usable addresses as a write-in address of the data block; and writing the data block in a bank corresponding to the write-in address. In the embodiments of the present invention, problems in the prior art that a conflict occurs when a data block is written in a bank and a conflict occurs when a data block is read from a bank can be avoided, and working efficiency of the EDRAM is improved.

Abstract: A semiconductor memory device and a method of operating a semiconductor memory device includes connecting selected even bit lines to selected even cell strings, programming memory cells in the selected even cell strings by using a second program permission voltage higher than a first program permission voltage, connecting selected odd bit lines to selected odd cell strings when programming of the memory cells is finished, and programming memory cells in the selected odd cell strings by using the first program permission voltage.