Abstract: Methods, systems, and devices that support fuseload architectures for system-on-chip (SoC) reconfiguration and repurposing are described. Trim data may be loaded from fuses to registers on a die based on a fuse header. For example, a set of registers coupled with a set of fuses on the die may be identified, where the set of fuses may store trim data to be copied to the registers as part of a fuseload procedure. In such cases, one or more fuse headers may be identified within the trim data, and each fuse header may correspond to a fuse group that includes a subset of fuses. Based on one or more subfields within a fuse header, a mapping between fuse addresses and register addresses may be determined, and the trim data from each fuse group may be copied into a set of registers based on the mapping.

Abstract: An apparatus may include multiple address registers each storing an address signal and multiple counter circuits each storing a count value corresponding to an associated one of the address registers. The apparatus may include a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

Abstract: An operation method of a semiconductor device is disclosed. The semiconductor device includes separate first and second dies in a package and receives first types of signals through first and second respective channels independent of each other and corresponding to the first and second respective dies. The method includes a step in which when information for controlling internal operations of the first and second dies is first applied to the first die through a first pad, the first die performs the internal operation and also transmits the information to the second die through an internal interface connecting the first die and the second die, and a step in which when the information is transmitted to the second die, the second die performs the internal operation.

Abstract: A method and apparatus for accumulating and storing respective access counts of a plurality of word lines in a memory module are provided. The method may include: within a memory bank positioned in the memory module, providing a plurality of extraordinary storage cells coupled to the plurality of word lines; and utilizing the plurality of extraordinary storage cells to accumulate and store the respective access counts of the plurality of word lines, wherein multiple sets of extraordinary storage cells in the plurality of extraordinary storage cells correspond to the plurality of word lines, respectively.

Abstract: A memory unit is controlled by a word line, a reference voltage and a bit-line clamping voltage. A non-volatile memory cell is controlled by the word line and stores a weight. A clamping module is electrically connected to the non-volatile memory cell via a bit line and controlled by the reference voltage and the bit-line clamping voltage. A clamping transistor of the clamping module is controlled by the bit-line clamping voltage to adjust a bit-line current. A cell detector of the clamping module is configured to detect the bit-line current to generate a comparison output according to the reference voltage. A clamping control circuit of the clamping module switches the clamping transistor according to the comparison output and the bit-line clamping voltage. When the clamping transistor is turned on by the clamping control circuit, the bit-line current is corresponding to the bit-line clamping voltage multiplied by the weight.

Abstract: A novel memory device is provided. The memory device including a plurality of memory cells arranged in a matrix, and each of the memory cells includes a transistor and a capacitor. The transistor includes a first gate and a second gate, which include a region where they overlap with each other with a semiconductor layer therebetween. The memory device has a function of operating in a “writing mode”, a “reading mode”, a “refresh mode”, and an “NV mode”. In the “refresh mode”, data retained in the memory cell is read, and then the read data is written to the memory cell again for first time. In the “NV mode”, data retained in the memory cell is read, the read data is written to the memory cell again for second time, and then a potential at which the transistor is turned off is supplied to the second gate. The “NV mode” operation enables data to be stored for a long time even when power supply to the memory cell is stopped. The memory cell can store multilevel data.

Abstract: A method of processing memory instructions including receiving a memory related command from a client system in communication with a memory appliance via a communication protocol, wherein the memory appliance comprises a processor, a memory unit controller and a plurality of memory devices coupled to said memory unit controller. The memory related command is translated by the processor into a plurality of commands that are formatted to perform prescribed data manipulation operations on data of the plurality of memory devices stored in data structures. The plurality of primitive commands is executed on data stored in the memory devices to produce a result, wherein the executing is performed by the memory unit controller. A direct memory transfer of the result is established over the communication protocol to a network.

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.

Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a main controller to begin a power down of a non-volatile memory storage during a first time period, while operating in a first voltage range, wherein the main controller is to begin the power down of the non-volatile memory in response to an indication of a voltage level being below a predetermined threshold; and a sequencer to continue the power down of the memory storage during a second time period, while operating within a second voltage range lower than the first voltage range. In some embodiments, the sequencer may include a state machine to perform a discharge sequence, where the state machine includes a micro-action output to output a micro-action command to the memory storage based at least in part on a current state of the state machine. Other embodiments may be described and/or claimed.

Abstract: A memory system has a nonvolatile memory to have a memory capacity equal to or less than a memory capacity of a volatile memory, and store at least a part of data stored in the volatile memory, a first controller to refresh data in the volatile memory, and a second controller to overwrite the nonvolatile memory with data read from the volatile memory in a first period between a second period to refresh data in the volatile memory and a third period to subsequently refresh data in the volatile memory.

Abstract: A memory device is able to store data using both on-chip dynamic random-access memory (“DRAM”) and nonvolatile memory (“NVM”). The memory device, in one aspect, includes NVM cells, word lines (“WLs”), a cell channel, and a DRAM mode select. The NVM cells are capable of retaining information persistently and the WLs are configured to select one of the NVM cells to be accessed. The cell channel, in one embodiment, is configured to interconnect the NVM cells to form a NVM string. The DRAM mode select can temporarily store data in the cell channel when the DRAM mode select is active.

Abstract: Embodiments of the disclosure provide a method and apparatus for controlling a startup bootstrap program of an intelligent TV set, and relate to the field of an embedded system so as to shorten a period of time for startup boot while initializing a screen normally. In the disclosure, after a system is powered on, a first task of initializing a screen in a startup bootstrap program is executed, and the length of preset time required for executing the first task is obtained, wherein the startup bootstrap program is a bootstrap program for initializing pieces of software/hardware of the system; executing a second initialization task unrelated to initializing the screen in the startup bootstrap program is executed while the first task is being executed, thus addressing the problem in the related art.

Abstract: A semiconductor device includes a group control circuit configured to generate a specified address and a control code in response to a row address and an active command, a comparison control signal generation circuit configured to generate a comparison control signal in response to the active command and a set code, and a target address generation circuit configured to output the specified address as a target address in response to the control code and the comparison control signal.

Abstract: A storage infrastructure, device and associated method for processing immutable data objects using in-flash processing. An in-flash processing system is provided that includes: an input/output manager that receives parameters from a host to perform back-end data processing tasks on immutable objects and that outputs commands to read and write immutable data objects to and from super-pages in a set of flash memory storage devices; a priority manager that ensures that front-end data processing tasks takes priority over back-end data processing tasks; and a back-end processing system that processes at least one immutable object in order to generate at least one new immutable object.

Abstract: The present disclosure relates to a technology for generating, executing, cloning, and managing application programming interface recipes. A software recipe comprises code including a trigger and one or more executable actions. The system implements a method for cloning software recipes by receiving a software recipe clone request from a user device and responsive to receiving the software clone request, computing requirements of the software recipe. The method involves retrieving input schema and output schema for the trigger and each of the one or more actions. The method involves saving a new instance of the software recipe with updated schema. The method further involves verifying whether the computed requirements are satisfied by the new instance of the software recipe.

Abstract: A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains in a linked-list data structure. The engine manages the linked-list data structure. The engine also is coupled to the fuse domains via the bus. The interface is coupled to the engine and receives commands and data for operating the engine.

Abstract: An apparatus includes a fuse array and a stores. The fuse array is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores. Each of the plurality of cores has sleep logic. The sleep logic is configured to subsequently access a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following a power gating event.

Abstract: An apparatus includes a fuse array, a stores, and a plurality of cores. The fuse array is programmed with compressed configuration data. The stores is for storage and access of decompressed configuration data sets. One of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store the decompressed configuration data sets for one or more cache memories in the stores. Each of the plurality of cores includes reset logic and sleep logic. The reset logic is configured to employ the decompressed configuration data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic is configured to determine that power is restored following a power gating event, and is configured to subsequently access the stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following the power gating event.

Abstract: An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

Abstract: An apparatus includes a programmer, a stores, and a plurality of cores. The programmer programs a fuse array with compressed configuration data. The stores provides for storage and access of decompressed configuration data sets. Each of a plurality of cores is coupled to the fuse array. One of the cores is accesses the fuse array upon power-up/reset to decompress and store decompressed configuration data sets for one or more cache memories. Each of the cores includes reset logic and sleep logic. The reset logic employs the decompressed configuration data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following the power gating event.

Abstract: An apparatus includes a device programmer and a stores. The device programmer programs a semiconductor fuse array with compressed configuration data for a plurality of cores disposed on a die. The stores includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores is configured to access the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores, and where, following a power gating event, one of the each of the plurality of cores subsequently accesses a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches.

Abstract: An apparatus includes a device programmer and a plurality of cores. The programmer programs a semiconductor fuse array with compressed configuration data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and stores decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

Abstract: An apparatus including a device programmer, a stores, and a plurality of cores. The device programmer programs a semiconductor fuse array with compressed configuration data for a plurality of cores disposed on a die. The stores has a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores is configured to access the semiconductor fuse array upon power-up/reset to read and decompress the configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores. The plurality of cores each has sleep logic that is configured to subsequently access a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following a power gating event.

Abstract: An apparatus includes a fuse array and a stores. The fuse array is disposed on a die, and is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompresses the compressed configuration data, and stores a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores, and where, following a power gating event, one of the each of the plurality of cores subsequently accesses a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the caches.

Abstract: An apparatus includes a fuse array and a stores. The fuse array is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores. Each of the plurality of cores has sleep logic. The sleep logic is configured to subsequently access a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following a power gating event.

Abstract: A method of controlling data transfers between a volatile memory and a non-volatile storage, the volatile memory being on a memory device operatively coupled to a computer system, the data transfers comprising: storing data from the volatile memory to the non-volatile storage when a power source of the computer system fails, the method comprising following re-establishment of the previously failed power source, the step of: selectively restoring data from the non-volatile storage to the volatile memory by a controller software after restart operations.

Abstract: Non-transitory computer-readable media having information embodied therein that includes a description of an integrated circuit device. The information includes descriptions of a volatile storage die having a first addressable range of storage cells and a non-volatile storage die. The description of the non-volatile storage die having a second addressable range of storage cells that defines an overlapping region with the first addressable range of storage cells. The information also includes a description of an interface circuit coupled to the volatile and non-volatile storage die to selectively transfer data stored in the overlapping region of storage cells between the die.

Abstract: The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a second transistor (104) coupled between a second storage node and said first supply line (GND, VDD), control terminals of said first and second transistors being coupled to said second and first storage nodes respectively; a third transistor (110) coupled between said first storage node and a first access line (BL) and controllable via a first control line (WL1); a fourth transistor (112, 712) coupled between said second storage node (108) and a second access line (BLB) and controllable via a second control line; and a first resistance switching element (202) coupled in series with said first transistor and programmable to have one of first and second resistive states.

Abstract: The present inventive concept provides a driving method of memory controller controlling nonvolatile memory device using variable resistive element. The memory controller may control a plurality of first memory devices and a second memory device. A number of write drivers in the second memory device may be driven when a number of first memory devices among the plurality of first memory devices are used. A different number of write drivers in the second memory device may be driven when a different number of first memory devices among the plurality of first memory devices are used.

Abstract: An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the core, where the fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for the core, where the compressed configuration data is generated by compression of data within a virtual fuse array that corresponds to the core, and where the core accesses and decompresses the compressed configuration data upon power-up/reset, for initialization of elements within the core.

Abstract: In a memory element including a pair of inverters, a capacitor which holds data, and a switching element which controls accumulating and releasing of electric charge of the capacitor are provided. For example, one electrode of the capacitor is connected to a first node, which is an input or output terminal of one of the pair of inverters, and the other electrode of the capacitor is connected to one electrode the switching element. The other electrode of the switching element is connected to a second node, which is the output or input terminal of the one of the pair of inverters. With such a connection structure, the absolute value of the potential difference between the first node and the second node at the time of data restoring can be large enough, whereby errors at the time of data restoring can be reduced.

Abstract: A cache and disk management method is provided. In the cache and disk management method, a command to delete all valid data stored in a cache, or specific data corresponding to a part of the valid data may be transmitted to a plurality of member disks. That is, all of the valid data or the specific data may exist in the cache only, and may be deleted from the plurality of member disks. Accordingly, the plurality of member disks may secure more space, an internal copy overhead may be reduced, and more particularly, solid state disks may achieve better performance.

Abstract: In some examples, a memory device is configured with non-volatile memory array(s) having one or more associated volatile memory arrays. The memory device may include a non-destructive write mode configured to prevent access to the non-volatile memory array(s) during an initiation or calibration sequence performed by the memory device or an electronic device associated with the memory device to calibrate read and write access timing associated with the memory device.

Abstract: Apparatus and methods of increasing the data rate and bandwidth of system memory including stacked memory device dice. The system memory includes a memory device having a plurality of memory device dice in a stacked configuration, a memory controller coupled to the stacked memory device dice, and a partitioned data bus. The memory device dice each include one, two, or more groups of memory banks. By configuring each memory device die to deliver all of its bandwidth over a different single partition of the data channel, the system memory can achieve an increased data rate and bandwidth without significantly increasing costs over typical system memory configurations that include stacked memory device dice.

Abstract: A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.

Abstract: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.

Abstract: A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.

Abstract: A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept commands from a host and to convert the commands into recipes. Each recipe includes a list of multiple memory operations to be performed sequentially in the non-volatile memory devices belonging to one of the sets. Each of the processors is associated with a respective set of the non-volatile memory devices, and is configured to receive one or more of the recipes from the main controller and to execute the memory operations specified in the received recipes in the non-volatile memory devices belonging to the respective set.

Abstract: An embedded memory device includes a mask ROM including a plurality of mask ROM cells and an address decoder configured to decode an address of the plurality of mask ROM cells; and an e-fuse memory configured to replace a part of data stored in the mask ROM with replacement data, the e-fuse memory including, a plurality of e-fuse memory cells configured to store the replacement data, and an e-fuse address selector configured to decode an address of the plurality of e-fuse memory cells and to selectively cause data of one or more of the plurality of e-fuse memory cells to be output based on the decoding result.

Abstract: A disk drive including a disk configured to spin at a target spin speed, a servo core configured to access the disk, a first non-volatile memory configured to store a first initialization firmware, a second non-volatile memory configured to store a second initialization firmware, a first volatile memory, a second volatile memory, a non-volatile memory core configured to access the first non-volatile memory, and a main core. The main core is configured to load the second initialization firmware from the second non-volatile memory to the second volatile memory concurrently with the loading of the first initialization firmware from the first non-volatile memory to the first volatile memory by the non-volatile memory core, control the servo core to initiate spinning of the disk, and communicate with the non-volatile memory core to service host commands from the first non-volatile memory when the disk is not spinning at the target spin speed.

Abstract: An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm.

Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

Abstract: A hierarchical on-chip memory (400) includes an area distributed CMOS layer (310) comprising input/output functionality and volatile memory and via array (325, 330), the area distributed CMOS layer (310) configured to selectively address the via array (325, 330). A crossbar memory (305) overlies the area distributed CMOS layer (310) and includes programmable crosspoint devices (315) which are uniquely accessed through the via array (325, 330). A method for utilizing hierarchical on-chip memory (400) includes storing frequently rewritten data in a volatile memory and storing data which is not frequently rewritten in a non-volatile memory (305), where the volatile memory is contained within an area distributed CMOS layer (310) and the non-volatile memory (305) is formed over and accessed through the area distributed CMOS layer (310).

Abstract: An apparatus includes a semiconductor fuse array and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed configuration data. The array has a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores the configuration data in an encoded and compressed format. The second plurality of fuses stores first compressed fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the array and accesses all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores.

Abstract: A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared interface circuit to receive memory access commands directed to the first storage die and the second storage die and to convey read and write data between an external data path and the first and second storage dice.

Abstract: A shiftable memory employs row shifting to shift data along a row. The shiftable memory includes memory cells arranged as a plurality of rows and a plurality of columns. The shiftable memory further includes shift logic to shift data from an output of a first column to an input of a second column. The shifted data is provided by a memory cell of the first column in a selected row. The shifted data is received and stored by a memory cell in the selected row of the second column. The shift logic facilitates shifting data along the selected row.

Abstract: A hybrid memory device is provided. The hybrid memory device includes a DRAM, a non-volatile memory and a control circuit. The control circuit selects one of output data of the DRAM and output data of the non-volatile memory according to a mode selecting signal and output the selected data. The control circuit outputs data requested to be output from the DRAM when the data requested to be output is in the DRAM, and may output the data requested to be output from the non-volatile memory when the data requested to be output is in the non-volatile memory. Accordingly, the hybrid memory device has a high speed in a read and write operation, and has low power consumption.

Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits.

Abstract: A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. A memory device includes a logic circuit including a first node and a second node, a first memory circuit connected to the first node, a second memory circuit connected to the second node, and a precharge circuit connected to the first node, the second node, the first memory circuit, and the second memory circuit. When reading data is performed, the precharge circuit outputs a precharge potential to the first node and the second node. The first memory circuit and the second memory circuit each include a transistor in which a channel is formed in an oxide semiconductor film.

Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.