Using Different Memory Types Patents (Class 365/189.2)
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Patent number: 8773896Abstract: One embodiment of a nonvolatile latch circuit comprises a latch circuitry configurated to temporarily hold data and comprising a first output terminal, the latch circuitry is coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal, and a first nonvolatile memory element configurated to store said data and comprising a low resistance and a high resistance. The first memory element is connected in-series with a first transistor and coupled between the first output terminal and an intermediate voltage source. The resistance of the first memory element is changed by a bidirectional current running between the first output terminal and the intermediate voltage source, wherein an electrical potential of the intermediate voltage source is higher than that of the low voltage source but lower than that of the high voltage source. Other embodiments are described and shown.Type: GrantFiled: March 27, 2013Date of Patent: July 8, 2014Inventor: Alexander Mikhailovich Shukh
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Patent number: 8760920Abstract: A semiconductor memory device includes a first memory device formed on a semiconductor substrate, including a first storage unit, a source, and a drain, a second memory device, including a second storage unit, and a bit line, wherein the second memory device is connected in series between the bit line and the drain.Type: GrantFiled: December 30, 2010Date of Patent: June 24, 2014Assignee: Hynix Semiconductor Inc.Inventors: Sook Joo Kim, Min Gyu Sung
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Patent number: 8730746Abstract: A semiconductor integrated circuit includes a first pad allocated to receive a row address, a second pad allocated to discriminate a first input/output mode and a second input/output mode, a detector configured to generate a detection signal in response to logic levels of the first and second pads, and a column address controller configured to deassert a column address to a logic low level in response to a deasserted detection signal. The semiconductor integrated circuit may selectively support one of first and second memory capacities and one of the first and second input/output modes using the logic levels of the first and second pads.Type: GrantFiled: December 30, 2011Date of Patent: May 20, 2014Assignee: SK Hynix Inc.Inventors: Keun Soo Song, Nak Kyu Park
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Patent number: 8724361Abstract: A device includes a nonvolatile memory array, a Static Random Access Memory (SRAM) array including a plurality of bit lines, including first and second bit lines paired with each other, and a pad. A first circuit is coupled between the nonvolatile memory array and the first and second bit lines, and interfaces with the SRAM array. A second circuit is coupled between the pad and the first and second bit lines, and interfaces with the SRAM array. A control circuit performs a first operation to access the nonvolatile memory array via the SRAM array and the first and second circuits and performs a second operation by producing an electrical path connecting from the pad to the nonvolatile memory array through at least one of the first and second bit lines of the SRAM array without intervening at least one of the first and second circuits.Type: GrantFiled: February 2, 2012Date of Patent: May 13, 2014Inventors: Mauro Pagliato, Giulio Martinozzi, Francesco Pessina
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Patent number: 8724407Abstract: To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a first nonvolatile memory circuit for storing data held in the volatile memory circuit, the memory includes a plurality of second nonvolatile memory circuits, and the first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor having a channel in an oxide semiconductor layer and a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off.Type: GrantFiled: March 23, 2012Date of Patent: May 13, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidetomo Kobayashi, Yukio Maehashi
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Patent number: 8711623Abstract: One of objects is to provide a nonvolatile memory device in which the occurrence of a defect in data writing is suppressed and whose area can be suppressed, or a semiconductor device including the nonvolatile memory device. A first memory portion including a nonvolatile memory element and a second memory portion (data buffer) for temporarily storing data in verifying operation in which whether the data is correctly written into the first memory portion is verified are provided. Further, the second memory portion includes a memory element and an insulated gate field effect transistor for controlling the holding of charge in the memory element; the off-state current or the leakage current of the transistor is extremely low.Type: GrantFiled: March 22, 2013Date of Patent: April 29, 2014Assignee: Semicondoctor Energy Laboratory Co., Ltd.Inventors: Toshihiko Saito, Shuhei Nagatsuka
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Patent number: 8711628Abstract: Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array.Type: GrantFiled: May 8, 2013Date of Patent: April 29, 2014Assignee: Micron Technology, Inc.Inventor: Ramin Ghodsi
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Patent number: 8665658Abstract: A semiconductor memory includes a memory array having at least one bit line, a tracking bit line, and a global tracking circuit. The tracking bit line is configured to emulate a voltage transition of the at least one bit line. The global tracking circuit is configured to generate a timing signal for generating a negative voltage with respect to ground on the at least one bit line of the memory array.Type: GrantFiled: December 7, 2011Date of Patent: March 4, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yen-Huei Chen
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Patent number: 8644104Abstract: A memory system that includes a memory device and a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row in a second storage region of the memory bank. The memory request includes a first row address identifying the first row and a second row address identifying the second row. Next, the memory device routes the first row address and the second row address to a first row decoder and a second row decoder in the memory bank, respectively. Finally, the memory device uses the first row decoder to decode the first row address to access the first row and concurrently uses the second row decoder to decode the second row address to access the second row.Type: GrantFiled: December 15, 2011Date of Patent: February 4, 2014Assignee: Rambus Inc.Inventor: Richard E. Perego
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Patent number: 8638620Abstract: A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.Type: GrantFiled: August 30, 2012Date of Patent: January 28, 2014Assignee: Mentor Graphics CorporationInventor: Peer Schmitt
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Patent number: 8576643Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has a maximum variation width of a threshold voltage for memorizing an information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.Type: GrantFiled: February 8, 2012Date of Patent: November 5, 2013Assignee: Renesas Electronics CorporationInventors: Yutaka Shinagawa, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Patent number: 8553478Abstract: A semiconductor integrated circuit includes a first chip and a second chip stacked together with the first chip. A first memory area is formed on the second chip, and a second memory area for repairing a failure of the first memory area is formed on the first chip.Type: GrantFiled: July 25, 2011Date of Patent: October 8, 2013Assignee: SK Hynix Inc.Inventors: Tae Sik Yun, Kang Seol Lee
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Patent number: 8525270Abstract: The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance.Type: GrantFiled: February 26, 2010Date of Patent: September 3, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Wee Teo, Ming Zhu, Chi-Ju Lee, Sheng-Chen Chung, Kai-Shyang You, Harry-Hak-Lay Chuang
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Patent number: 8503258Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.Type: GrantFiled: September 14, 2012Date of Patent: August 6, 2013Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
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Patent number: 8493797Abstract: A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.Type: GrantFiled: August 6, 2012Date of Patent: July 23, 2013Assignee: Round Rock Research, LLCInventor: Dean A. Klein
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Patent number: 8488397Abstract: Providing increased capacity in heterogeneous storage elements including a method for reading from memory. The method includes receiving a read word from a block of memory cells, where physical characteristics of the memory cells support different sets of data levels. The read word is separated into two or more virtual read vectors. For each of the virtual read vectors, the codebook that was utilized to generate the virtual read vector is identified and a partial read data vector is generated. The generating includes multiplying the virtual read vector by a matrix that represents the codebook. The partial read data vectors are combined into a read message and the read message is output.Type: GrantFiled: July 25, 2012Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Ibrahim M. Elfadel, Michele Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano, Mayank Sharma
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Patent number: 8488379Abstract: A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.Type: GrantFiled: October 11, 2011Date of Patent: July 16, 2013Assignee: Cypress Semiconductor CorporationInventors: Andreas Scade, Stefan Guenther
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Patent number: 8467260Abstract: Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.Type: GrantFiled: August 5, 2011Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Kevin W. Gorman, Michael R. Ouellette, Michael A. Ziegerhofer
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Patent number: 8446748Abstract: What is disclosed is a novel memory array and process for creating a memory array to reduce wireline variability. The method includes accessing a routing design of a memory array with a plurality of memory cells. Each memory cell in the array includes one or more access devices, and a group of wires electrically connected between one or more of the memory cells and peripheral circuitry (PC). The group of the group of wires is divided into at least one subgroup (N). Next, a capacitance (C1, C2 . . . CN) of each wire in the subgroup (N) is calculated. Continuing further, a maximum capacitance (CMAX) of wires in the subgroup (N) is determined. An add-on capacitance to be added to a number (NA) of the wires in the subgroup (N) is calculated.Type: GrantFiled: August 4, 2011Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Chung Hon Lam, Jing Li, Robert Montoye
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Patent number: 8437203Abstract: A nonvolatile memory apparatus includes a memory device having a configuration information storage block for storing a first configuration data group and a second configuration data group having fewer bits than the first configuration data group and a configuration information processing circuit configured to determine a majority of the first configuration data group outputted from the memory device, during a first period of a power-up operation, and determine a majority of the second configuration data group outputted from the memory device, during a second period after the first period.Type: GrantFiled: December 31, 2010Date of Patent: May 7, 2013Assignee: SK Hynix Inc.Inventors: Kyoung Nam Kim, Beom Ju Shin
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Patent number: 8427891Abstract: A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared interface circuit to receive memory access commands directed to the first storage die and the second storage die and to convey read and write data between an external data path and the first and second storage dice.Type: GrantFiled: April 17, 2008Date of Patent: April 23, 2013Assignee: Rambus Inc.Inventor: Scott C. Best
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Patent number: 8422298Abstract: One of objects is to provide a nonvolatile memory device in which the occurrence of a defect in data writing is suppressed and whose area can be suppressed, or a semiconductor device including the nonvolatile memory device. A first memory portion including a nonvolatile memory element and a second memory portion (data buffer) for temporarily storing data in verifying operation in which whether the data is correctly written into the first memory portion is verified are provided. Further, the second memory portion includes a memory element and an insulated gate field effect transistor for controlling the holding of charge in the memory element; the off-state current or the leakage current of the transistor is extremely low.Type: GrantFiled: March 10, 2011Date of Patent: April 16, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshihiko Saito, Shuhei Nagatsuka
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Patent number: 8400870Abstract: A memory device is provided. The memory device comprises a plurality of memory chips. The plurality of memory chips receive an input address code and alternately operate in an active mode. Each memory chip receives a selection signal and operates according to an internal address counter code. For each memory chip, the respective internal address counter code is initially set according to the input address code and the respective selection signal.Type: GrantFiled: January 4, 2011Date of Patent: March 19, 2013Assignee: Winbond Electronics Corp.Inventor: Ying Te Tu
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Patent number: 8380917Abstract: Systems, methods, and circuits for command control for synchronous memory device are disclosed. In one embodiment, a memory device comprises a first synchronous memory controlled by a second group of commands which includes a first command receiving section for receiving a first group of commands, and a second command receiving section for receiving a command that is unique to the first synchronous memory and different from the first group of commands during execution of the first group of commands received by the first command receiving section. The synchronous memory further comprises a second synchronous memory controlled by the first group of commands, where the first synchronous memory and the second synchronous memory are coupled to a same data bus, and where the second group of commands is different from the first group of commands.Type: GrantFiled: June 12, 2008Date of Patent: February 19, 2013Assignee: Spansion LLCInventors: Kenji Shibata, Mitsuhiro Nagao, Satoru Kawmoto
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Patent number: 8369176Abstract: A multi-chip memory device includes a number of chips and a control circuit included in each of the chips and configured to generate an internal chip enable signal in response to set data stored therein and an external chip enable signalType: GrantFiled: June 29, 2010Date of Patent: February 5, 2013Assignee: SK Hynix Inc.Inventors: Min Su Kim, Sung Hoon Ahn
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Patent number: 8345478Abstract: Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array.Type: GrantFiled: February 22, 2011Date of Patent: January 1, 2013Assignee: Micron Technology, Inc.Inventor: Ramin Ghodsi
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Patent number: 8335098Abstract: Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data to be stored, the memory device being built from a one time programmable (OTP) memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets selected out of the plurality of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the plurality of memory sets which remains after the memory sets of the OTP memory block are excluded and operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block.Type: GrantFiled: January 14, 2010Date of Patent: December 18, 2012Assignee: Seiko Instruments Inc.Inventor: Biao Shen
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Patent number: 8332580Abstract: An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.Type: GrantFiled: May 13, 2009Date of Patent: December 11, 2012Assignee: ZikBit Ltd.Inventors: Avidan Akerib, Eli Ehrman, Josh Meir, Moshe Meyassed, Oren Agam, Yair Alpern
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Patent number: 8331128Abstract: A memory device may include a plurality of memory cells each having elements with at least one solid ion conductor programmable between at least two different impedance states for at least two different data retention times, the plurality of memory cells being dividable into a plurality of portions, each portion being separately configurable for one of the data retention times.Type: GrantFiled: December 2, 2009Date of Patent: December 11, 2012Assignee: Adesto Technologies CorporationInventors: Narbeh Derhacobian, Shane Charles Hollmer
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Patent number: 8332585Abstract: An electronic flash memory external storage method and device for data processing system includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores data by flash memory and access control circuit with the cooperation of the firmware and the driver with the operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in static state and is driven by software. It is plug-and-play and adapted to data processing system.Type: GrantFiled: October 27, 2011Date of Patent: December 11, 2012Assignee: Netac Technology Co., Ltd.Inventors: Guoshun Deng, Xiaohua Cheng
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Patent number: 8325541Abstract: A non-volatile semiconductor memory apparatus includes a first memory area configured to include a plurality of non-volatile memory cells, a second memory area configured to include a plurality of memory cells whose write speed is faster than the plurality of non-volatile memory cells, and a host interface configured to control the first and second memory areas, wherein the first and second memory areas are configured to be provided with the same address signal and command signal from the host interface.Type: GrantFiled: December 30, 2008Date of Patent: December 4, 2012Assignee: SK hynix Inc.Inventors: Tae Su Jang, Sung Joo Hong, Sung Woong Chung
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Patent number: 8320206Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.Type: GrantFiled: November 15, 2010Date of Patent: November 27, 2012Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
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Publication number: 20120257460Abstract: Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power.Type: ApplicationFiled: June 21, 2012Publication date: October 11, 2012Applicant: Unity Semiconductor CorporationInventor: Robert Norman
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Publication number: 20120243340Abstract: To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a first nonvolatile memory circuit for storing data held in the volatile memory circuit, the memory includes a plurality of second nonvolatile memory circuits, and the first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor having a channel in an oxide semiconductor layer and a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off.Type: ApplicationFiled: March 23, 2012Publication date: September 27, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hidetomo Kobayashi, Yukio Maehashi
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Patent number: 8259523Abstract: According to one embodiment, a semiconductor memory device includes a first memory, a second memory and a control circuit. The first memory includes a first bank number. The second memory includes a second bank number larger than the first bank number. The control circuit controls a precharge operation with respect to bit lines provided in the first and second memories. When performing, with respect to the first memory, a synchronous operation that is effected in synchronization with a clock, the control circuit changes over a second precharge operation to an operation time different from a first precharge operation during a period from the end of the initial first precharge operation to the start of the subsequent second precharge operation after receiving an address.Type: GrantFiled: July 15, 2010Date of Patent: September 4, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Toshifumi Watanabe, Tomoyuki Hamano, Shigefumi Ishiguro, Kazuto Uehara
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Patent number: 8259517Abstract: A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.Type: GrantFiled: August 11, 2010Date of Patent: September 4, 2012Assignee: Mentor Graphics CorporationInventor: Peer Schmitt
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Patent number: 8259518Abstract: A memory cell has at least two word lines and at least two bit lines. The cell also has a first select device being connected to at least one word line and one bit line and a gate capacitor element connected to at least one word line and the first select device. The cell also has a sense device being connected in series to the gate capacitor element and the first select device. The sense device is connected to at least two bit lines.Type: GrantFiled: June 8, 2010Date of Patent: September 4, 2012Assignee: Sichuan Kiloway Electronics Inc.Inventors: Jack Z. Peng, David Fong
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Patent number: 8244971Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).Type: GrantFiled: October 30, 2007Date of Patent: August 14, 2012Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 8238148Abstract: A semiconductor device having an architecture for reducing an area is provided. The semiconductor device includes a memory cell array including a plurality of non-volatile memory cells, a plurality of registers each configured to store pre-fetch unit data, and a write driver circuit configured to write pre-fetch unit data sequentially output from the plurality of registers to the memory cell array during a write operation. The semiconductor device also includes a sense amplifier circuit configured to sense and amplify pre-fetch unit data sequentially output from the memory cell array and to sequentially store the amplified pre-fetch unit data in the plurality of registers, respectively, during a read operation.Type: GrantFiled: January 5, 2010Date of Patent: August 7, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ho Jung Kim, Chul Woo Park, Sang Beom Kang, Jung Min Lee, Hyun Ho Choi
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Patent number: 8208319Abstract: Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power.Type: GrantFiled: November 22, 2011Date of Patent: June 26, 2012Inventor: Robert Norman
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Patent number: 8209479Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).Type: GrantFiled: October 30, 2007Date of Patent: June 26, 2012Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Publication number: 20120155172Abstract: According to one embodiment, a semiconductor memory device includes a first memory and a second memory, a data path between the first memory and the second memory, a register configured to store first data transferred through the data path in a first direction, and a comparison circuit configured to compare second data transferred through the data path in a second direction with the first data stored in the register so as to detect a fault location.Type: ApplicationFiled: September 23, 2011Publication date: June 21, 2012Inventors: Toshifumi WATANABE, Mitsuhiro Abe, Kenji Ishizuka
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Publication number: 20120155160Abstract: A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).Type: ApplicationFiled: December 16, 2011Publication date: June 21, 2012Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Syed M. Alam, Thomas Andre, Dietmar Gogl
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Patent number: 8199590Abstract: A multiple time programmable non-volatile memory element and associated programming methods that allow for integration of non-volatile memory with other CMOS integrated circuitry utilizing standard CMOS processing. The multiple time programmable non-volatile memory element includes a capacitor, an access transistor that is electrically coupled to the capacitor at a connection node, and a plurality of one time programmable non-volatile memory cells. Each of the plurality of one time programmable non-volatile memory cells is electrically coupled to the connection node and includes a select transistor that is electrically coupled to an antifuse element. The antifuse element is configured to have changed resistivity in response to one or more voltage pulses received at the connection node, the change in resistivity representing a change in logic state.Type: GrantFiled: September 24, 2010Date of Patent: June 12, 2012Assignee: Novocell Semiconductor, Inc.Inventors: Walter Novosel, Ethan Sieg, Timothy Fiscus, David Novosel, Elaine Novosel, legal representative
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Publication number: 20120127804Abstract: Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.Type: ApplicationFiled: January 25, 2011Publication date: May 24, 2012Applicant: Grandis, Inc.Inventors: Adrian E. Ong, Vladimir Nitikin
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Patent number: 8169838Abstract: A memory device includes a single or a plurality of memory chips. In the memory device (memory module), the single memory chip or each of the plurality of memory chips has a memory part storing control data such as specification data and function data, and control data stored on the memory part is rewritable. Control data stored on the memory part separately disposed on each memory chip enables separate use of the memory chip, which improves compatibility and flexibility of the memory.Type: GrantFiled: September 30, 2008Date of Patent: May 1, 2012Assignee: Fujitsu LimitedInventors: Toshihiro Miyamoto, Akio Takigami, Masaya Inoko, Takayoshi Suzuki, Hiroyuki Ono
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Patent number: 8169825Abstract: A method for data storage in a non-volatile memory includes storing data in the non-volatile memory using a first storage configuration while the non-volatile memory is supplied with electrical power. After storing the data, an indication is accepted, indicating that shut-off of the electrical power is imminent. Responsively to the indication and before the shut-off, at least some of the data is re-programmed in the non-volatile memory using a second storage configuration.Type: GrantFiled: September 1, 2009Date of Patent: May 1, 2012Assignee: Anobit Technologies Ltd.Inventors: Ofir Shalvi, Naftali Sommer, Barak Rotbard, Oren Golov, Micha Anholt, Uri Perlmutter
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Patent number: 8169839Abstract: A memory device for use with a primary power source including: non-volatile memory; volatile memory; an interface for connecting to a backup power source; isolation logic for controlling access to the volatile memory by a host processor, said isolation logic having a first mode during which the isolation logic provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation logic isolates the volatile memory from access by the host processor; and a controller controlling the isolation logic, said controller programmed to place the isolation logic in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation logic in the second mode and transfer data from the volatile memory to the non-volatile memory.Type: GrantFiled: February 11, 2009Date of Patent: May 1, 2012Assignee: STEC, Inc.Inventors: Mark Moshayedi, Douglas Finke
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Publication number: 20120092935Abstract: A semiconductor memory device includes a first memory device formed on a semiconductor substrate, including a first storage unit, a source, and a drain, a second memory device, including a second storage unit, and a bit line, wherein the second memory device is connected in series between the bit line and the drain.Type: ApplicationFiled: December 30, 2010Publication date: April 19, 2012Applicant: Hynix Semiconductor Inc.Inventors: Sook Joo KIM, Min Gyu Sung
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Patent number: 8159868Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.Type: GrantFiled: August 21, 2009Date of Patent: April 17, 2012Assignee: Zeno Semiconductor, Inc.Inventor: Yuniarto Widjaja