Abstract: Described are various configurations of high-speed via structures. Various embodiments can reduce or entirely eliminate insertion loss in high-speed signal processing environments by using impedance compensation structures that decrease a mismatch in components of a circuit. An impedance compensation structure can include a metallic structure placed near a via to lower an impedance difference between the via and a conductive pathway connected to the via.

Abstract: A millimeter-wave active antenna unit and an interconnection structure between PCBs is provided. The interconnection structure between PCBs comprises a mainboard and an AIP antenna module. The mainboard is a first multilayer PCB on which a signal transmission line and a first pad electrically connected to the signal transmission line are provided. The AIP antenna module is a second multilayer PCB on which a second pad, an impedance matching transformation branch, an impedance line and a signal processing circuit are provided. The mainboard and the AIP antenna module are interconnected by directly welding multiple PCBs.

Abstract: An impedance compensation structure for a broadband near-field magnetic-field probe, includes: a signal via; and a plurality of grounding vias provided around the signal via to form a coaxial via array; wherein the grounding via and the signal via have an identical size, all distances of each of the plurality of the grounding vias to the signal via are equal, and the plurality of the grounding vias forms a circle centered at the signal via; wherein each of the plurality of the grounding vias is connected with a magnetic field probe top layer shield plane and a magnetic field probe bottom layer shield plane; each of the plurality of the grounding vias keeps in a conducting state from a direct current to a high frequency, in such a manner that impedance matching of the broadband near-field magnetic-field probe is achieved.

Abstract: A method for sending data by inductive coupling includes: extracting an antenna signal from an antenna circuit, extracting from the antenna signal a first periodic signal, producing a second periodic signal by way of a synchronous oscillator, placing the oscillator in a free oscillation mode and applying to the antenna circuit the second periodic signal, modifying the impedance of the antenna circuit, restoring the amplitude of the antenna signal, then resynchronizing the oscillator on the first periodic signal.

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that may include memory storage for the RFID tag, the memory storage may include one time programmable (OTP) memory and many time programmable (MTP) memory and the storage of the information may be within the OTP and MTP memory.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency identification (RFID) tag that includes an OTP-based hardened memory system for the RFID tag.

Abstract: RFID tag ICs employ tunneling-voltage profile calibration during IC manufacturing to determine and store, typically in nonvolatile memory, a tunneling-voltage profile for writing data to the IC's nonvolatile memory. The IC may subsequently read the profile at power-up, prior to writing the memory, or at other times as determined by the IC or by an interrogating reader, and may determine an actual ramp profile for writing to the nonvolatile memory based on the read profile and one or more operating conditions. By using the read profile to determine an actual ramp profile for writing to the nonvolatile memory, the IC may reduce nonvolatile memory write time and oxide stress.

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract: Termination of a high-speed signaling link is effected by simultaneously engaging on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that provide enhanced memory capabilities, redundant functionality, and multiple frequency capabilities to the RFID tag using an inter-RF network node communication connection. The inter-RF network node communication may allow the coordination of RFID tag memory and functionality.

Abstract: RFID tag ICs employ tunneling-voltage profile calibration during IC manufacturing to determine and store, typically in nonvolatile memory, a tunneling-voltage profile for writing data to the IC's nonvolatile memory. The IC may subsequently read the profile at power-up, prior to writing the memory, or at other times as determined by the IC or by an interrogating reader. By using the stored profile when writing to the nonvolatile memory the IC may reduce nonvolatile memory write time and oxide stress.

Abstract: A global line sharing circuit of a semiconductor memory device includes: a ZQ calibration unit configured to adjust an impedance of a DQ output driver; a test unit configured to control a test operation; and a shared global line coupled to and used in common by the ZQ calibration unit and the test unit.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that provide enhanced memory capabilities, redundant functionality, and multiple frequency capabilities to the RFID tag using an inter-RF network node communication connection. The inter-RF network node communication may allow the coordination of RFID tag memory and functionality.

Abstract: A RFID registration system is provided with a reader for reading an ID of an object to be identified by an RFID, an RFID existence position indicating the position of the RFID, and the RFID; an associating apparatus for associating the read RFID with the ID of the object to be identified by the RFID, a position information generation apparatus for obtaining the read position at the same time the position has been read, and a collation apparatus for obtaining an ID of the object to be identified by the RFID based on the read position and the RFID existence position. The RFID registration system can be avoid making the mistaken association between the RFID and the object to which the identification ID is attached.

Abstract: In embodiments of the present invention improved capabilities are described for a passive radio frequency identification (RFID) tag, where the passive RFID tag contains an RF network node and communication facility. The RF network node includes an RF and analog block for receiving and transmitting an RFID reader signal, a data processing and controller block for digital information processing, a memory store, and a power management block for managing power requirements of the RF network node. The communication facility communicates at least in part with an external display facility. The distribution of power to the RF network node functional blocks is controlled using the power management block to select between an extended operational time and an increase in available functionality.

Abstract: In embodiments of the present invention improved capabilities are described for a method of memory mapping disparate memories on a composite radio frequency identification (RFID) tag, where the RFID tag includes a plurality of individual RFID devices each having a memory store with a physical memory address range and mounted to a common substrate, where at least one of the individual RFID devices comprises memory configuration information, and where a memory addressing facility maps the physical memory address ranges of each of the individual RFID devices to a single logical addressing space and presents the address space as a single memory, where the memory addressing facility is included on a computing facility separate from the composite RFID tag.

Abstract: A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus, it is difficult to provide a memory with few defects. It is an object of the present invention to provide a write-once memory where the probability of a defect is reduced considerably. A nonvolatile memory that can be written only once includes a redundant memory cell, a first circuit which allocates an address to the redundant memory cell, a second circuit which outputs a determination signal that expresses whether writing is performed normally or not, and a third circuit, to which the determination signal is inputted, which controls the first circuit and the second circuit.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that provide enhanced memory capabilities, redundant functionality, and multiple frequency capabilities to the RFID tag using an inter-RF network node communication connection. The inter-RF network node communication may allow the coordination of RFID tag memory and functionality.

Abstract: It is an object of the present invention to provide a volatile organic memory in which data can be written other than during manufacturing and falsification by rewriting can be prevented, and to provide a semiconductor device including such an organic memory. It is a feature of the invention that a semiconductor device includes a plurality of bit lines extending in a first direction; a plurality of word lines extending in a second direction different from the first direction; a memory cell array including a plurality of memory cells each provided at one of intersections of the bit lines and the word lines; and memory elements provided in the memory cells, wherein the memory elements include bit lines, an organic compound layer, and the word lines, and the organic compound layer includes a layer in which an inorganic compound and an organic compound are mixed.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that provide enhanced memory capabilities, redundant functionality, and multiple frequency capabilities to the RFID tag using an inter-RF network node communication connection. The inter-RF network node communication may allow the coordination of RFID tag memory and functionality.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that provide enhanced memory capabilities, redundant functionality, and multiple frequency capabilities to the RFID tag using an inter-RF network node communication connection. The inter-RF network node communication may allow the coordination of RFID tag memory and functionality.

Abstract: An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that may include memory storage for the RFID tag, the memory storage may include one time programmable (OTP) memory and many time programmable (MTP) memory and the storage of the information may be within the OTP and MTP memory.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that may include memory storage for the RFID tag, the memory storage may include one time programmable (OTP) memory and many time programmable (MTP) memory and the storage of the information may be within the OTP and MTP memory.

Abstract: A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that provide enhanced memory capabilities, redundant functionality, and multiple frequency capabilities to the RFID tag using an inter-RF network node communication connection. The inter-RF network node communication may allow the coordination of RFID tag memory and functionality.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that provide enhanced memory capabilities, redundant functionality, and multiple frequency capabilities to the RFID tag using an inter-RF network node communication connection. The inter-RF network node communication may allow the coordination of RFID tag memory and functionality.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that provide enhanced memory capabilities, redundant functionality, and multiple frequency capabilities to the RFID tag using an inter-RF network node communication connection. The inter-RF network node communication may allow the coordination of RFID tag memory and functionality.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that may include memory storage for the RFID tag, the memory storage may include one time programmable (OTP) memory and many time programmable (MTP) memory and the storage of the information may be within the OTP and MTP memory.

Abstract: In embodiments of the present invention improved capabilities are described for a composite RFID tag, where the composite RFID tag may include a plurality of individual tags that are arranged to respond to a reader as one tag.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that provide enhanced memory capabilities, redundant functionality, and multiple frequency capabilities to the RFID tag using an inter-RF network node communication connection. The inter-RF network node communication may allow the coordination of RFID tag memory and functionality.

Abstract: A radio frequency (RF) transmitter includes a transmitter processing module that generates a processed signal and a modulating signal based on outbound data. An up-conversion module up-converts the processed signal to generate an up-converted signal. A programmable filter module generates a first plurality of delayed signals from the up-converted signal and that generates a filtered up-converted signal by combining the up-converted signal and the first plurality of delayed signals, wherein a delayed signal of the first plurality of delayed signals is scaled based on one of a first plurality of coefficients, wherein the first plurality of coefficients are selected based on a control signal. A polar amplifier amplifies and amplitude modulates the filtered up-converted signal based on the modulating signal to generate a transmit signal. A processing module generates the control signal to attenuate at least one RF spur of the up-converted signal.

Abstract: An automated system for the processing of radio frequency identification (RFID) tags. The automated system allows for the simultaneous processing of multiple individual tags through the use of multiple processing stations. A table is provided that is capable of moving the individual tags from one processing station to the next. Tables are also provided for receiving unprocessed tags for input into the system and processed tags for packaging. Individual tags are moved between the tables by a transfer mechanism.

Abstract: Since a power source voltage is generated from a communication signal in a wireless chip, there is a risk that a large amount of voltage be generated in the wireless chip to electrically destroy a circuit in the case of supplying a strong communication signal. Therefore, the present invention is made with an aim to provide a wireless chip having resistance to a strong communication signal. A wireless chip of the present invention has an element in which a power source wire and a grounding wire are electrically short-circuited if a power source voltage exceeds a voltage at which an electric circuit is destroyed, i.e., exceeds the specified voltage range. Accordingly, a wireless chip of the present invention has resistance to a strong communication signal.

Abstract: A device includes a memory configured so that, in the event that one pass-gate transistor associated with a bit cell is determined to be excessively weak such that reading the bit cell could be undesirably difficult, a second pass-gate transistor can be configured to support a read operation. For example, during a manufacturing test procedure, the access speed of each bit cell at a memory device is determined. If a bit cell fails to achieve a desired access speed, the column of the memory that includes the defective bit cell can be configured to access information stored at the bit cell using the second bit line associated with the second pass-gate transistor.

Abstract: In an organic memory which is included in a radio chip formed from a thin film, data are written to the organic memory by a signal inputted with a wired connection, and the data is read with a signal by radio transmission. A bit line and a word line which form the organic memory are each selected by a signal which specifies an address generated based on the signal inputted with a wired connection. A voltage is applied to a selected memory element. Thus writing is performed. Reading is performed by a clock signal or the like which are generated from a radio signal.

Abstract: An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE.

Abstract: A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

Abstract: A RFID tag capable of storing and restoring flag data is described. The RFID tag includes an analog block for generating a driving power using a radio frequency signal received through an antenna. The driving power is used to store the flag data. A digital block is operated using the generated driving power and processes RF data that is transmitted and received via the analog block in order to store the flag data in the analog block. A memory block reads and writes data to a nonvolatile ferroelectric capacitor depending on a control signal from the digital block. The analog block supplies the flag data to the digital block during an activation time period of a power-on reset signal.

Abstract: An oscillating device including: an oscillator generating an oscillation signal according to an enable signal; a counter counting an oscillation number of the oscillation signal and being able to reset at the oscillation number indicated by a first signal; and a comparator comparing the counted oscillation number and a reference number, is provided.

Abstract: A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal.

Abstract: The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency.

Abstract: A number of read cycles applied to a selected memory location of a memory device, such as a variable-resistance memory device, is monitored. Write data to be written to the selected memory location is received. Selective pre-write verifying and writing of the received write data to the selected memory location occurs based on the monitored number of read cycles. Selectively pre-write verifying and writing of the received write data may include, for example, writing received write data to the selected memory cell region without pre-write verification responsive to the monitored number of read cycles being greater than a predetermined number of read cycles.

Abstract: Provided are a method and system for testing a semiconductor memory device using an internal clock signal of the semiconductor memory device as a data strobe signal. The internally-generated data strobe signal may be delayed to synchronize with test data. Because a test device need not supply the data strobe signal, the number of semiconductor memory modules that can be simultaneously tested can be increased, and an average test time for a unit memory module can be decreased.

Abstract: A configurable memory device includes an array of configurable memory units arranged into rows and columns. The configurable memory unit includes a memory cell comprising a first storage element configured to store a first value and a second storage element configured to store a second value. The memory unit can be either a single-ended or a differential configuration. In the single-ended configuration, the stored value of each storage element is interpreted as one bit. In the differential configuration, the stored first and second values of the storage elements are interpreted as a differential single bit. An external control signal determines in which configuration the unit is in.

Abstract: Methods and systems are provided for improved protection of radio frequency identification tag memory by using two or more “brownout-safe” pointer registers (instead of a single pointer register) that are logically concatenated to form a complete address for the boundary between a locked portion and an unlocked portion of the tag memory. A first pointer is a coarse pointer identifying a block of memory containing the boundary. A second pointer is a fine pointer identifying a specific location within the identified coarse block of memory. The coarse pointer may be a gray-coded or linear pointer. Similarly, the fine pointer may be a gray-coded or linear pointer.

Abstract: A nonvolatile memory, such as a write-once memory, includes a memory cell array that has first memory cells and at least one second memory cell. The memory also includes a first writing circuit that is capable of writing data to the first memory cells and the second memory cell, a second writing circuit, and a verify circuit which is capable of confirming whether the data is normally stored in the first memory cells. When the writing of data to one of the first memory cells fails, the second writing circuit is arranged to assign an address of the one of the first memory cells to the second memory cell. The first memory cells and the second memory cell are arranged to irreversibly change their electrical resistance when the data is stored in them. The first memory cells and the second memory cell include an organic compound layer interposed between a pair of electrodes.

Abstract: A state storage device for use in an RFID tag includes, in at least one embodiment, a capacitor coupled to a high impedance node. The storage device can be configured to indicate a high or low bit condition. The high impedance node can be designed to dissipate the stored electrical charge at a user-controlled, predefined, or known rate. The state storage device can be configured to store the bit condition for no more than four seconds. In some embodiments, the high impedance node can be formed from an electrically trimmed transistor.

Abstract: A sensing device includes a sensor, a control unit, an input/output (I/O) interface, and a non-volatile magnetic memory device having one or more memory cells, each of the memory cells, wherein each memory cell of the non-volatile magnetic memory device includes a magnetic switch including a magnetic component and a write coil located proximate the magnetic component, the write coil coupled to receive a current sufficient to create a remnant magnetic polarity in the magnetic component, and a Hall sensor, positioned proximate the magnetic component, to detect the remnant magnetic polarity indicative of a stored data bit.