Delay Patents (Class 365/194)
  • Patent number: 11329651
    Abstract: An integrated circuit including: a clock generation circuit configured to generate first and second divided clock signals by dividing an external clock signal; and a command generation circuit configured to synchronize and decode an external command signal based on a divided clock signal of the first and second divided clock signals, which is synchronized with a chip select signal.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 11309000
    Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sanjeev Kumar Jain, Sahil Preet Singh, Atul Katoch
  • Patent number: 11302391
    Abstract: Methods, circuits, and systems for reading memory cells are described. The method may include: applying a first voltage with a first polarity to a plurality of the memory cells; applying a second voltage with a second polarity to one or more of said plurality of the memory cells; applying at least a third voltage with the first polarity to one or more of said plurality of the memory cells; detecting electrical responses of memory cells to the first voltage, the second voltage, and the third voltage; and determining a logic state of respective memory cells based on the electrical responses of the memory cells to the first voltage, the second voltage, and the third voltage.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Di Vincenzo, Riccardo Muzzetto, Ferdinando Bedeschi
  • Patent number: 11302380
    Abstract: A memory controller device includes a delay line circuitry, data sampler circuits, phase detector circuits, and a control logic circuit. The delay line circuitry delays a data strobe signal to generate first to third clock signals, in which the second clock signal is for reading a data signal, and phases of the first to the third clock signals are sequentially differentiated by a predetermined value. The data sampler circuits sample the data signal according to the first to the third clock signals, in order to generate first to third signals. The phase detector circuits compare the first signal with the second signal to generate a first detection signal, and compare the third signal with the second signal to generate a second detection signal. The control logic circuit adjusts the first to the third clock signals according to the first and the second detection signals.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: April 12, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Jie Zheng
  • Patent number: 11270757
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor degradations in word line characteristics. The memory device may generate a reference signal in response to an access command directed to a memory array including a plurality of word lines, in some embodiments. The memory array may include a victim word line configured to accumulate adverse effects of executing multiple access commands at the word lines of the memory array. When the degradation in the word line characteristics causes reliability issues (e.g., corrupted data), the memory array is deemed unreliable, and may be blocked from memory operations. The memory device may compare the reference signal and a signal from the victim word line to determine whether preventive measures may be appropriate to avoid (or mitigate) such reliability issues.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: March 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Gitanjali T. Ghosh, Debra M. Bell, Arunmozhi R. Subramaniam, Roya Baghi, Deepika Thumsi Umesh, Sue-Fern Ng
  • Patent number: 11211139
    Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: December 28, 2021
    Assignee: Rambus Inc.
    Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
  • Patent number: 11200480
    Abstract: A counter readout circuit includes a plurality of counter registers and an output data computing unit. The plurality of counter registers, each includes a counter which counts per clock signal cycle. The output data computing unit includes a computing unit which adds, for output, the counter value of a counter register to the total clock count from a first timing to a second timing. The counter register is selected from the plurality of counter registers. The first timing is common to all of the plurality of counter registers. The second timing is a timing of selection of the selected counter register.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: December 14, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoru Matsuyama, Satoshi Matsumura, Kazuhiro Nakamuta
  • Patent number: 11200942
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for lossy row access counting. Row addresses along a to address bus may be sampled. When the row address is sampled it may be compared to a plurality of stored addresses in a data storage unit. If the sampled address matches one of the stored addresses, a count value associated with that address may be updated in a first direction (such as being increased). Periodically, all of the count values may also be updated in a second direction (for example, decreased).
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Matthew D. Jenkinson, Jiyun Li, Dennis G. Montierth, Nathaniel J. Meier
  • Patent number: 11188264
    Abstract: A memory system includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay. The system can select to perform memory access operations with the NV memory device with the asymmetry, in which case write operations have a lower delay than read operations. The system can alternatively select to perform memory access operations with the NV memory device where a configured write operation delay that matches the read operation delay.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Shekoufeh Qawami, Philip Hillier, Benjamin Graniello, Rajesh Sundaram
  • Patent number: 11184009
    Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Tso Lin, Chin-Ming Fu, Mao-Ruei Li
  • Patent number: 11183252
    Abstract: A dynamic voltage supply circuit of a nonvolatile memory device includes a voltage amplification/output circuit and a dynamic voltage output circuit. The voltage amplification/output circuit receives a first clock signal and a second clock signal to generate a dynamic supply voltage greater than a supply voltage while the first clock signal has a “low” level. The dynamic voltage output circuit outputs the dynamic supply voltage while the first clock signal has a “low” level and outputs a ground voltage while the first clock signal has a “high” level.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: November 23, 2021
    Assignee: SK Hynix system ic Inc.
    Inventor: Hyun Min Song
  • Patent number: 11176978
    Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay (tRCD) are disclosed. In some examples, tRCD may be reduced by providing a non-zero offset voltage to a target wordline at an earlier time, such as during a threshold voltage compensation phase of a sense operation. Setting the wordline to a non-zero offset voltage at an earlier time may reduce a time for the wordline to reach an activation voltage, which may reduce tRCD. In other examples, protection against row hammer attacks during precharge phases may be improved by setting the wordline to the non-zero offset voltage.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Christopher Kawamura
  • Patent number: 11170829
    Abstract: A semiconductor device includes an internal clock generation circuit and a data processing circuit. The internal clock generation circuit delays first to fourth division clock signals, which are generated by dividing a frequency of a clock signal, by a delay time adjusted based on a first code signal and a second code signal to generate first to fourth internal clock signals. The data processing circuit aligns internal data in synchronization with the first to fourth internal clock signals to generate output data. The data processing circuit also interrupts generation of the output data based on first and second command blocking signals according to a point in time when a read command is inputted.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Min Sik Han, Sung Chun Jang, Jin Il Chung
  • Patent number: 11169562
    Abstract: An electronic device includes a latch clock generation circuit, a command decoder, and a latency shifting circuit. The latch clock generation circuit generates a latch clock based on a chip selection signal. The command decoder generates an internal operation signal from an internal chip selection signal and an internal command generated based on the latch clock. The latency shifting circuit generates an end signal by shifting the internal operation signal in synchronization with a shifting clock by a period corresponding to a latency while an internal operation is performed.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 11152044
    Abstract: A system for performing a phase matching operation includes a controller configured to output a dock, a command, and a strobe signal, and to input/output data. The system also includes a semiconductor device configured to generate an internal strobe signal by matching the phases of the command and the strobe signal according to the clock, and to input/output the data in synchronization with the internal strobe signal, wherein the semiconductor device generates the internal strobe signal from the strobe signal by compensating for a delay amount of a first path to which the command is inputted and a delay amount of a second path to which the strobe signal is inputted.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: October 19, 2021
    Assignee: SK hynix Inc.
    Inventors: Min Su Park, Min Gyu Park, Geun Ho Choi
  • Patent number: 11115006
    Abstract: An internal latch circuit having a plurality of low initial value D flip-flops, a plurality of high initial value D flip-flops, an internal latch signal generating circuit and a NAND gate, and a method for generating latch signal thereof is provided. First, an input delay signal in response to a clock signal is generated. Then, a first internal input signal, a first reverse internal input signal, a second internal input signal, and a second reverse internal input signal are generated by using the low initial value D flip-flops and the high initial value D flip-flops, based on the internal data strobe signal and in response to the input delay signal, and are transmitted to the internal latch signal generating circuit. Then, the internal latch signal generating circuit outputs the first reverse pre-output signal and the second reverse pre-output signal. Finally, an internal latch signal is generated through a NAND gate.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: September 7, 2021
    Assignee: Integrated Silicon Solution Inc.
    Inventors: Kangmin Lee, Sangmin Jun, Youngjin Yoon, Seung Cheol Bae, Kwang Kyung Lee, Sun Byeong Yoon
  • Patent number: 11113073
    Abstract: Systems and methods are disclosed, including selectively providing one of a first reset or a second reset to transition to a storage system from a low power mode to an operational power mode in response to a hardware reset signal and a value of a control bit on the storage system.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Greg A. Blodgett
  • Patent number: 11100976
    Abstract: An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: August 24, 2021
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 11100968
    Abstract: A memory system includes a representative memory device directly outputting a representative data strobe signal, at least one non-representative memory device outputting a non-representative data strobe signal through the representative memory device, and a controller generating an internal delay clock signal synchronized with the representative data strobe signal. The controller outputs a test mode code defining a delay time using the internal delay clock signal as a reference signal. The at least one non-representative memory device adjusts a phase of the non-representative data strobe signal such that the non-representative data strobe signal has a delay time corresponding to the test mode code.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventors: Seong Ju Lee, Yun Tack Han, Byung Deuk Jeon, Kyu Tae Park
  • Patent number: 11069424
    Abstract: Various implementations described herein refer to an integrated circuit having a first memory structure and a second memory structure. The first memory structure is disposed in a first area of the integrated circuit, and the first memory structure has first memory cells with first transistors. The second memory structure is disposed in a second area of the integrated circuit that is different than the first area, and the second memory structure has second memory cells with second transistors that are separate from the first transistors. The second transistors of the second memory cells are arranged to provide an output oscillating frequency for detecting variation of performance of the first transistors of the first memory cells.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 20, 2021
    Assignee: Arm Limited
    Inventors: Amit Chhabra, Rainer Herberholz
  • Patent number: 11056171
    Abstract: Apparatuses and methods for wide clock frequency range command paths are disclosed. An example apparatus includes a command decoder and a command timing circuit. The command decoder is configured to receive a command and is further configured to decode the command to provide a decoded command. The command timing circuit is configured to receive the decoded command responsive to a clock and is further configured to provide a delayed internal command having a delay relative to receiving the decoded command based on clock frequency information indicative of a clock frequency of the clock. The command timing circuit includes a plurality of command timing paths. Each of the plurality of command timing paths is configured to provide a respective delay to the decoded command for a respective range of clock frequencies.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kallol Mazumder, Kangjoo Lee, Ming-Bo Liu
  • Patent number: 11054855
    Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: July 6, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Jin Cho, Jae-Geun Park, Young-Kwang Yoo, Soon-Suk Hwang
  • Patent number: 11036410
    Abstract: A method includes varying a number of clock characteristics of each a plurality of memory devices of a memory concurrently, determining a fitness of the memory for each variation of the number of clock characteristics, selecting a particular variation of the number of clock characteristics based on the determined fitness of the memory for the particular variation, changing a setting in each of the plurality of memory devices corresponding to the particular variation to generate an additional variation of the number of clock characteristics, and determining a fitness of the memory for the additional variation.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Peter Mayer, Martin Brox, Wolfgang Anton Spirkl, Marcos Alvarez Gonzalez, Casto Salobrena Garcia, Andreas Schneider
  • Patent number: 11031064
    Abstract: A semiconductor device includes a buffer control circuit and an operation control circuit. The buffer control circuit generates an enable signal based on a self-refresh signal and to generate an end control signal and a supply control signal from a first internal chip selection signal during a self-refresh operation. The operation control circuit generates a frequency information signal from an internal command/address signal when an update signal is inputted during a mode register write operation, adjusts a shift amount based on the frequency information signal when the supply control signal is inputted during the mode register write operation, and generates an internal write command according to the adjusted shift amount during a read-modify-write operation in synchronization with an internal clock signal after generating an internal read command.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventor: Chang Hyun Kim
  • Patent number: 11031068
    Abstract: A memory device includes a command decoder configured to receive a command, a data clock receiving circuit configured to receive a data clock signal, and a control logic configured to control the data clock receiving circuit based on the command decoded by the command decoder, and enable the data clock receiving circuit. The control logic enables the data clock receiving circuit in response to the memory device receiving a dynamic data clock command. The data clock receiving circuit is in an enabled state until a predetermined particular command is received.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seongheon Yu, Joungyeal Kim, Doowon Bong
  • Patent number: 11017854
    Abstract: A storage device includes a first layer extending in a first direction, a second layer extending in a second direction intersecting the first direction, a third layer extending in a third direction intersecting the first and second directions, a first transistor including a first gate electrode electrically connected to the second layer, a first selection transistor having a first end electrically connected to the third layer and a second end electrically connected to the second layer, a first cell including a first element electrically connected between the first and second layers and to a node of the second layer that is between the first gate electrode of the first transistor and the second end of the first selection transistor, and a circuit turning on the first selection transistor to electrically connect the first cell to the third layer during a write operation performed on the first cell.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: May 25, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kunifumi Suzuki
  • Patent number: 11004495
    Abstract: A storage device comprising: a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device to determine a memory block to perform a refresh operation and to control the memory block to perform the refresh operation to recover data of the memory block.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventors: Jin Woong Kim, Ji Hoon Yim
  • Patent number: 10984844
    Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim
  • Patent number: 10983865
    Abstract: In various examples, a device comprises a memory. The memory comprises a plurality of dies and logic. The logic may: determine a tolerable bit error rate (BER) of the memory based on whether one of the plurality of dies has failed, and adjust a parameter of the memory based on the tolerable BER.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: April 20, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Martin Foltin
  • Patent number: 10978140
    Abstract: An aspect a bit selection path configured to propagate a bit selection signal. The bit selection path includes bit selection delay circuitry defining a bit selection delay. The memory array includes a row selection path configured to propagate a row selection signal. The row selection path includes row selection delay circuitry defining a row selection delay. The memory array includes local selection circuitry. The local selection circuitry is configured to receive the bit selection signal from the bit selection path before the row selection signal from the row selection path according to the bit selection delay and the row selection delay.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul Alan Bunce, John Davis, Brian James Yavoich, Russell Hayes
  • Patent number: 10978158
    Abstract: A control method, for a memory array, the control method comprises programming the bit-cell of the memory array in a programming stage; and discharging the bit-cell of the memory array in a discharge stage; wherein the programming stage comprises: programming the bit-cell of the memory array with a plurality of programming voltage pulses; wherein the discharge stage comprises: isolating a select line of the bit-cell of the memory array; and generating a programming voltage pulse to the bit-cell of the memory array; wherein the programming stage can be suspended to a suspend stage by a suspend command after the discharge stage; wherein the suspend command is received during one of the plurality of programming voltage pulse.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: April 13, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhi Chao Du, Yu Wang, Haibo Li, Ke Jiang, Ye Tian
  • Patent number: 10969430
    Abstract: A delay measurement apparatus for measuring a delay unit comprising: a clock; clock counter; a digital signal source that is uncorrelated with the clock; a first detector arranged to detect transitions of the digital signal entering the delay unit; a first accumulator arranged to accumulate the current clock counter value based on the output of the first detector; a second detector arranged to detect transitions of the digital signal exiting the delay unit; a second accumulator arranged to accumulate the current clock counter value based on the output of the second detector; a measurement counter arranged to count the number of transitions of the digital signal passing through the delay unit; and a calculation device arranged to calculate an average number of clock cycles that elapse while a transition of the digital signal passes through the delay unit based on the first accumulator, the second accumulator and the measurement counter.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: April 6, 2021
    Assignee: Novelda ASA
    Inventors: Tor Sverre Lande, Håkon André Hjortland
  • Patent number: 10963404
    Abstract: A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a same burst write sequence.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: James A. McCall, Rajat Agarwal, George Vergis, Bill Nale
  • Patent number: 10965292
    Abstract: A DLL device and an operation method for the DLL device are provided. The DLL device includes a delay line, a replica circuit, a phase detector, and a delay controller. The delay line delays an input clock in response to a delay code to provide a delayed clock. The replica circuit generates a feedback clock according to the delayed clock. The phase detector compares the input clock with the feedback clock to generate a delay control signal. The delay controller generates the delay code at a first time point according to the delay control signal based on a control clock and delays a replica delay time length to provide the delay code to the delay line at a second time point. The delay line adjusts the input clock at the second time point. A cycle of the control clock is adjusted to be larger than the replica delay time length.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: March 30, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Shinya Okuno
  • Patent number: 10964395
    Abstract: A memory system, a memory device, a memory controller and an operating method thereof. By issuing a first status check signal when a first delay time elapses since a first point in time at which a program operation for first memory cells corresponding to a first word line is started and by issuing a second status check signal when a second delay time different from the first delay time elapses since a second point in time at which a program operation for second memory cells corresponding to a second word line is started, it is possible to efficiently perform a status check operation related with a program operation of data.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: March 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Seung-Hwan Shin, Woong-Sik Shin
  • Patent number: 10957371
    Abstract: A memory device includes a memory cell array in which plural memory cells are arranged in a matrix manner, and a mode selection part. The mode selection part has at least any two of a first mode, a second mode, a third mode and selects any operation mode. The first mode is for reading and writing 1-bit data with the first memory cell or the second memory cell. The second mode is for reading and writing the 1-bit data with a cell unit including the N first memory cells and the N second memory cells connected to a bit line pair. The third mode is for reading and writing the 1-bit data with a cell unit including the M first memory cells and the M second memory cells connected to the bit line pair. M and N are 1 or more integers which are different from each other.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: March 23, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Tetsuo Endoh, Yasuhiro Ohtomo
  • Patent number: 10937471
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: March 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Su Jang, Man-Jae Yang, Jeong-Don Ihm, Go-Eun Jung, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10929290
    Abstract: System, method, and machine readable medium implementing a mechanism for selecting and providing reconfigurable hardware resources in a rack architecture system are described herein. One embodiment of a system includes a plurality of nodes and a configuration manager. Each of the nodes further includes: a plurality of memory resources and a node manager. The node manager is to track the memory resources that are available in the node, determine different possible configurations of memory resources, and generate a performance estimate for each of the possible configurations. The configuration manager is to receive a request to select one or more nodes based on a set of performance requirements, receive from each node the different possible configurations of memory resources and the performance estimate for each of the possible configurations, and iterate through collected configurations and performance estimates to determine one or more node configurations best matching the set of performance requirements.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Murugasamy K. Nachimuthu, Mohan J. Kumar
  • Patent number: 10924114
    Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Suk Seo, Seung Wook Oh, Da In Im
  • Patent number: 10896713
    Abstract: Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 10892998
    Abstract: Customers of shared resources in a multi-tenant environment can have token buckets allocated that have an associated depth and fill rate, with each token enabling the customer to obtain an amount of work from a shared resource. A resource management system can monitor one or more system or output metrics, and can adjust a global fill rate based at least in part upon values of the monitored metrics. Such an approach can provide a fair distribution of work among the customers, while ensuring that the metrics stay within acceptable ranges and there are no drastic changes in performance levels of the system. The fill rate can update dynamically with changes in the monitored parameters, such that the system can float near an equilibrium point. Commitments for specific minimum service levels also can be met.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: January 12, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Tate Andrew Certain, James R. Hamilton
  • Patent number: 10884958
    Abstract: A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Rajat Agarwal, Bill Nale, Chong J. Zhao, James A. McCall, George Vergis
  • Patent number: 10872646
    Abstract: Apparatuses and methods for providing active an inactive clock signals are disclosed. An example apparatus includes an input clock buffer and a clock divider circuit. The input clock buffer includes a receiver circuit configured to receive first and second clock signals or first and second constant voltages. The receiver circuit is further configured to provide first and second output signals based on the complementary clock signals or the first and second constant voltages. The first and second clock signals are complementary and the second constant voltage is less than the first constant voltage. The clock divider circuit is configured to receive the first and second output signals and provide multiphase clock signals based on the first and second output signals from the input clock buffer.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hyun Yoo Lee
  • Patent number: 10868535
    Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: December 15, 2020
    Assignee: STC.UNM
    Inventors: James Plusquellic, James Aarestad
  • Patent number: 10867669
    Abstract: A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A memory array is configured to receive each of the plurality of serialized input signals. The memory array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Cheng Chen, Jack Liu
  • Patent number: 10854264
    Abstract: Various implementations described herein refer to an integrated circuit having a sense amplifier that operates with a clock signal, and the sense amplifier may be biased with a bias signal that affects duration of the clock signal. The integrated circuit may include a delay circuit coupled to the sense amplifier, and the delay circuit may turn-off the clock signal. The delay circuit may have a current-starved delay stage that receives an input signal having a falling edge and provides a current-starved delay signal biased by the bias signal that also biases the sense amplifier.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: December 1, 2020
    Assignee: Arm Limited
    Inventors: Surya Prakash Gupta, Piyush Jain, El Mehdi Boujamaa
  • Patent number: 10855290
    Abstract: Embodiments disclose a delay locked loop. The delay locked loop including a main delay circuit configured to generate initial clocks by delaying an internal clock, and sub-delay lines configured to generate phase clocks having a phase difference corresponding to a desired initial delay by respectively delaying the internal clock and the initial clocks. The phase difference among the phase clocks may be adjusted according to delay values of the sub-delay lines.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: December 1, 2020
    Assignees: SK hynix Inc., Korea University Research and Business Foundation
    Inventors: Chul Woo Kim, Hyun Su Park
  • Patent number: 10825495
    Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim
  • Patent number: 10796734
    Abstract: Systems, methods, and apparatuses for temperature-compensated operation of electronic devices are described. For example, an apparatus for performing voltage compensation on a sense amplifier based on temperature may include a sense amplifier control circuit coupled to the sense amplifier to provide a compensation pulse to the sense amplifier, wherein the sense amplifier operates in a voltage compensation phase during the compensation pulse. The apparatus may determine the compensation pulse responsive to a voltage compensation duration signal that is based on the operating temperature of the apparatus. The voltage compensation occurs when there is no activate command immediately before or immediately after so that compensation duration change do not happen during an activate command from the command decoder.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Boon Hor Lam, Karl L. Major, Jonathan Hawkins, Galaly Ahmad
  • Patent number: 10796739
    Abstract: A semiconductor device may include a first internal command generation circuit configured to advance a phase of a first external command in accordance with a delay time of an on die termination (ODT) path and a first latency and generate the first delay command; and a second internal command generation circuit configured to advance a phase of a second external command in accordance with a delay time of a clock path and a second latency and to generate a second delay command.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: October 6, 2020
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Suk Seo