Delay Patents (Class 365/194)
  • Patent number: 10929290
    Abstract: System, method, and machine readable medium implementing a mechanism for selecting and providing reconfigurable hardware resources in a rack architecture system are described herein. One embodiment of a system includes a plurality of nodes and a configuration manager. Each of the nodes further includes: a plurality of memory resources and a node manager. The node manager is to track the memory resources that are available in the node, determine different possible configurations of memory resources, and generate a performance estimate for each of the possible configurations. The configuration manager is to receive a request to select one or more nodes based on a set of performance requirements, receive from each node the different possible configurations of memory resources and the performance estimate for each of the possible configurations, and iterate through collected configurations and performance estimates to determine one or more node configurations best matching the set of performance requirements.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Murugasamy K. Nachimuthu, Mohan J. Kumar
  • Patent number: 10924114
    Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Suk Seo, Seung Wook Oh, Da In Im
  • Patent number: 10896713
    Abstract: Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 10892998
    Abstract: Customers of shared resources in a multi-tenant environment can have token buckets allocated that have an associated depth and fill rate, with each token enabling the customer to obtain an amount of work from a shared resource. A resource management system can monitor one or more system or output metrics, and can adjust a global fill rate based at least in part upon values of the monitored metrics. Such an approach can provide a fair distribution of work among the customers, while ensuring that the metrics stay within acceptable ranges and there are no drastic changes in performance levels of the system. The fill rate can update dynamically with changes in the monitored parameters, such that the system can float near an equilibrium point. Commitments for specific minimum service levels also can be met.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: January 12, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Tate Andrew Certain, James R. Hamilton
  • Patent number: 10884958
    Abstract: A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Rajat Agarwal, Bill Nale, Chong J. Zhao, James A. McCall, George Vergis
  • Patent number: 10872646
    Abstract: Apparatuses and methods for providing active an inactive clock signals are disclosed. An example apparatus includes an input clock buffer and a clock divider circuit. The input clock buffer includes a receiver circuit configured to receive first and second clock signals or first and second constant voltages. The receiver circuit is further configured to provide first and second output signals based on the complementary clock signals or the first and second constant voltages. The first and second clock signals are complementary and the second constant voltage is less than the first constant voltage. The clock divider circuit is configured to receive the first and second output signals and provide multiphase clock signals based on the first and second output signals from the input clock buffer.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hyun Yoo Lee
  • Patent number: 10867669
    Abstract: A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A memory array is configured to receive each of the plurality of serialized input signals. The memory array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Cheng Chen, Jack Liu
  • Patent number: 10868535
    Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: December 15, 2020
    Assignee: STC.UNM
    Inventors: James Plusquellic, James Aarestad
  • Patent number: 10855290
    Abstract: Embodiments disclose a delay locked loop. The delay locked loop including a main delay circuit configured to generate initial clocks by delaying an internal clock, and sub-delay lines configured to generate phase clocks having a phase difference corresponding to a desired initial delay by respectively delaying the internal clock and the initial clocks. The phase difference among the phase clocks may be adjusted according to delay values of the sub-delay lines.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: December 1, 2020
    Assignees: SK hynix Inc., Korea University Research and Business Foundation
    Inventors: Chul Woo Kim, Hyun Su Park
  • Patent number: 10854264
    Abstract: Various implementations described herein refer to an integrated circuit having a sense amplifier that operates with a clock signal, and the sense amplifier may be biased with a bias signal that affects duration of the clock signal. The integrated circuit may include a delay circuit coupled to the sense amplifier, and the delay circuit may turn-off the clock signal. The delay circuit may have a current-starved delay stage that receives an input signal having a falling edge and provides a current-starved delay signal biased by the bias signal that also biases the sense amplifier.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: December 1, 2020
    Assignee: Arm Limited
    Inventors: Surya Prakash Gupta, Piyush Jain, El Mehdi Boujamaa
  • Patent number: 10825495
    Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim
  • Patent number: 10796739
    Abstract: A semiconductor device may include a first internal command generation circuit configured to advance a phase of a first external command in accordance with a delay time of an on die termination (ODT) path and a first latency and generate the first delay command; and a second internal command generation circuit configured to advance a phase of a second external command in accordance with a delay time of a clock path and a second latency and to generate a second delay command.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: October 6, 2020
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Suk Seo
  • Patent number: 10796734
    Abstract: Systems, methods, and apparatuses for temperature-compensated operation of electronic devices are described. For example, an apparatus for performing voltage compensation on a sense amplifier based on temperature may include a sense amplifier control circuit coupled to the sense amplifier to provide a compensation pulse to the sense amplifier, wherein the sense amplifier operates in a voltage compensation phase during the compensation pulse. The apparatus may determine the compensation pulse responsive to a voltage compensation duration signal that is based on the operating temperature of the apparatus. The voltage compensation occurs when there is no activate command immediately before or immediately after so that compensation duration change do not happen during an activate command from the command decoder.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Boon Hor Lam, Karl L. Major, Jonathan Hawkins, Galaly Ahmad
  • Patent number: 10790273
    Abstract: Provided are integrated circuits including a plurality of standard cells aligned along a plurality of rows. The integrated circuit includes first standard cells aligned on the first row and including first conductive patterns to which a first supply voltage is applied in a conductive layer and second standard cells aligned on the second row which is adjacent to the first row in the conductive layer and including second conductive patterns to which the first supply voltage is applied in the conductive layer. A pitch between the first conductive patterns and the second conductive patterns may be less than a pitch provided by single-patterning.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-ho Do
  • Patent number: 10790000
    Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay (tRCD) are disclosed. In some examples, tRCD may be reduced by providing a non-zero offset voltage to a target wordline at an earlier time, such as during a threshold voltage compensation phase of a sense operation. Setting the wordline to a non-zero offset voltage at an earlier time may reduce a time for the wordline to reach an activation voltage, which may reduce tRCD. In other examples, protection against row hammer attacks during precharge phases may be improved by setting the wordline to the non-zero offset voltage.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Christopher Kawamura
  • Patent number: 10788993
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 29, 2020
    Assignee: Unity Semiconductor Corporation
    Inventor: Chang Hua Siau
  • Patent number: 10777237
    Abstract: There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. The semiconductor memory device may include an operation control signal generator configured to receive a request for performing a target operation from the controller configured to control the semiconductor memory device and to generate a synchronizing signal for performing the target operation. The semiconductor memory device may include a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Byoung In Joo
  • Patent number: 10762933
    Abstract: A semiconductor device includes a latch control circuit configured to generate a latch input signal, which is enabled in response to a latency signal, and configured to generate a latch output signal, which is enabled in response to an order control signal. The semiconductor device also includes a pipe latch circuit configured to latch input data in response to a pipe input signal and configured to output the latched input data as latch data in response to a pipe output signal. The semiconductor device additionally includes a data output circuit configured to latch the latch data in response to the latch input signal and configured to output the latched latch data as output data in response to the latch output signal, wherein the output data is outputted by performing an alignment operation for the latch data in response to the latch output signal.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 1, 2020
    Assignee: SK hynix Inc.
    Inventors: Hong Gyeom Kim, Dae Ho Ra, Byung Kuk Yoon, Min Sik Han
  • Patent number: 10763830
    Abstract: A temperature compensated current controlled oscillator (CCO) including a first current generator configured to produce a proportional to absolute temperature (PTAT) current based upon a trim signal, a second current generator configured to produce a complementary to absolute temperature (CTAT) current based upon a temperature measurement, and a ring oscillator configured to receive the PTAT current and the CTAT current and to produce a frequency signal based upon the PTAT current and the CTAT current.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: September 1, 2020
    Assignee: NXP B.V.
    Inventors: Siamak Delshadpour, Chiahung Su
  • Patent number: 10763901
    Abstract: A transmission device of the disclosure includes: a plurality of delay sections having changeable delay amounts; a driver section that includes a plurality of drivers and transmits a data signal indicating a sequence of symbols using the plurality of drivers, the plurality of drivers being provided to correspond to the plurality of delay sections and setting a voltage at a corresponding output terminal to a mutually different voltage on the basis of a signal delayed by a corresponding delay section of the plurality of delay sections; and a controller that sets the respective delay amounts of the plurality of delay sections on the basis of a transition of a symbol in the sequence of symbols.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: September 1, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hiroaki Hayashi, Masatsugu Sugano
  • Patent number: 10755764
    Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: August 25, 2020
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 10748584
    Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tsugio Takahashi, Zer Liang
  • Patent number: 10741239
    Abstract: An example apparatus includes a processing in memory (PIM) capable device having an array of memory cells and sensing circuitry coupled to the array. The PIM capable includes a row address strobe (RAS) component selectably coupled to the array. The RAS component is configured to select, retrieve a data value from, and input a data value to a specific row in the array. The PIM capable device also includes a RAS manager selectably coupled to the RAS component. The RAS manager is configured to coordinate timing of a sequence of compute sub-operations performed using the RAS component. The apparatus also includes a source external to the PIM capable device. The RAS manager is configured to receive instructions from the source to control timing of performance of a compute operation using the sensing circuitry.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Timothy P. Finkbeiner
  • Patent number: 10720206
    Abstract: A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A memory array is configured to receive each of the plurality of serialized input signals. The memory array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Cheng Chen, Jack Liu
  • Patent number: 10699758
    Abstract: A semiconductor system includes a second semiconductor device. The second semiconductor device configured to receive an external clock, first and second code signals, and input and output data. The second semiconductor device configured to adjust a delay amount depending on a combination of the first and second code signals, generate an internal clock by delaying the external clock according to the adjusted delay amount, and input and output data in synchronization with the internal clock. The second semiconductor device is adjusted in a driving force for driving the internal clock, depending on a voltage level of a node included in a path through which the internal clock is delayed.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventor: Kwan Dong Kim
  • Patent number: 10699762
    Abstract: A cycle control circuit may include a judgement pulse generation circuit, a detection signal generation circuit or a flag generation circuit. The judgement pulse generation circuit may be configured to set a predetermined value based on an initialization signal and a period signal, and to generate a judgment pulse. The detection signal generation circuit may be configured to generate a detection signal from a reference flag. The flag generation circuit may be configured to generate a reference flag based on a reference signal. A cycle of the reference signal may be maintained or adjusted based on the reference flag.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventor: Chang Hyun Kim
  • Patent number: 10685942
    Abstract: A package trace design technique provides at least partial cancelation of reflections. In one illustrative method of providing a high-bandwidth chip-to-chip link with a first die coupled to a second die via a first substrate trace, an intermediate trace, and a second substrate trace, the method includes: (a) determining a first propagation delay for an electrical signal to traverse the first substrate trace, the electrical signal having a predetermined symbol interval; (b) determining a second propagation delay for the electrical signal to traverse the second substrate trace; and (c) setting a length for at least one of the first and second substrate traces, the length yielding a difference between the first and second propagation delays, the difference having a magnitude equal to half the predetermined symbol interval.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 16, 2020
    Assignee: Credo Technology Group Limited
    Inventors: Xike Liu, Mengying Ma
  • Patent number: 10678725
    Abstract: A semiconductor apparatus may include an interface circuit. The interface circuit may sense level variations of a first signal and a second signal. The interface circuit may generate first and second output signals by variably delaying the first and second signals depending on a sensing result. The interface circuit may transmit the first and second output signals to first and second signal transmission lines which are adjacent to each other.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Jong Joo Shim, Hyung Soo Kim
  • Patent number: 10659215
    Abstract: Methods and apparatus relate to a 1-to-2 memory interface deserializer circuit that, in a training mode, independently positions even and odd strobes in respective even and odd data windows. In an illustrative example, the deserializer circuit may receive a data signal that encodes even and odd data streams on the rising (even) and falling (odd) edges of a strobe clock signal. During a training mode, the deserializer circuit may independently determine, for example, an optimal temporal delay for each of the even strobe and the odd strobe. Adjustable delay lines dedicated to each of the even and odd strobe signals may simultaneously detect valid data window edges to permit determination of a desired delay to optimally position the strobe signals. Various embodiments may advantageously reduce jitter associated with asymmetric strobe and/or data signals to achieve a predetermined specification (e.g., timing margins) within the corresponding data windows.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 19, 2020
    Assignee: XILINX, INC.
    Inventors: Xiaobao Wang, Arvind R. Bomdica, Balakrishna Jayadev, Richard W. Swanson
  • Patent number: 10623210
    Abstract: A transmission system of at least one electrical signal to be transmitted by a transmitting electronic device to at least a receiving electronic device, comprising: at least one signal line which connects the transmitting electronic device to the at least one receiving electronic device and which is suitable to transmit the respective electrical signal to be transmitted; a signal generation unit, that generates the electrical signal to be transmitted on each signal line; at least one noise compensation line; a noise compensation circuit that generates on each noise compensation line a noise compensation signal.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: April 14, 2020
    Assignee: MARELLI AUTOMOTIVE LIGHTING ITALY S.P.A.
    Inventors: Alessandro Brisotto, Giancarlo Codutti, Andrea Englaro, Matteo Iellina
  • Patent number: 10614872
    Abstract: A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Parthasarathy Gajapathy
  • Patent number: 10607673
    Abstract: A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a logic level combination corresponding to a first command or a second command. The semiconductor device may include a code synthesis circuit configured to add the period code to a previous synthesis code to generate a synthesis code. The semiconductor device may include a buffer control circuit configured to compare the synthesis code with a selection control code to generate a buffer inactivation signal for controlling input of a data strobe signal.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventors: Hak Song Kim, Min Su Park
  • Patent number: 10607684
    Abstract: A semiconductor device includes a delay time adjustment circuit and an address input circuit. The delay time adjustment circuit adjusts a point in time when charges are supplied to internal nodes according to a voltage level of a back-bias voltage in response to a test mode signal. The delay time adjustment circuit also delays an active signal by a first delay time varying according to amounts of charge of the internal nodes to generate a bank selection signal. The address input circuit is driven by the back-bias voltage. The address input circuit receives an address in response to the bank selection signal to generate an internal address. The address input circuit delays the address by a second delay time varying according to a voltage level of the back-bias voltage.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung Min Yang, Kyoung Youn Lee, Byeong Cheol Lee, Don Hyun Choi
  • Patent number: 10600497
    Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 24, 2020
    Assignee: Rambus Inc.
    Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
  • Patent number: 10600458
    Abstract: A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Ho Jeon, Han-Gi Jung, Hun-Dae Choi
  • Patent number: 10600457
    Abstract: A sampling circuit may include a first timing determination circuit, a second timing determination circuit, and a sampling data output circuit. The first timing determination circuit may determine a first timing of sampling data in response to a first sampling timing signal. The second timing determination circuit may determine a second timing of the sampling data in response to a second sampling timing signal. The sampling data output circuit may output the sampling data having effective data values of the data between the first timing and the second timing in response to outputs from the first and second timing determination circuits.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Bo Ram Kim, Dae Han Kwon
  • Patent number: 10594309
    Abstract: In a phase modulation method enable signals may be sequentially generating based on a clock signal to generate a sequence of enable signals, and a signal is delayed by delay values generated from delay cells based on the sequence of enable signals and digital bit values. A phase modulator may include a first delay circuit configured to: delay a clock signal based on a first delay value to generate a first delayed clock signal, and delay a carrier signal based on the first delayed clock signal to generate a first delayed carrier signal; and a second delay circuit configured to: delay the first delayed clock signal based on a second delay value to generate a second delayed clock signal, and delay the first delayed carrier signal based on the second delayed clock signal to generate a second delayed carrier signal.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: March 17, 2020
    Assignee: Apple Inc.
    Inventors: Abhishek Agrawal, Stefano Pellerano, Yanjie Wang, Peter Sagazio
  • Patent number: 10579417
    Abstract: The threads of a user mode process can access various different resources of a computing device, and such access can be serialized. To access a serialized resource, a thread acquires a lock for the resource. For each context switch in the computing device, a module of the operating system kernel checks for priority inversions, which is a situation in which a higher priority thread of the user mode process is waiting for (blocking on) a resource for which a lower priority thread has acquired a lock. In response to detecting such a priority inversion, the priority of the lower priority thread is boosted to allow the priority thread to execute and eventually release the lock that the higher priority thread is waiting for.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: March 3, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Yevgeniy M. Bak, Mehmet Iyigun, Christopher Peter Kleynhans, Syed A. Raza
  • Patent number: 10545680
    Abstract: A recording/reproduction apparatus comprising an output unit outputs a clock signal to each of a plurality of recording media, a communication unit transmits a write command and write data to each of the plurality of recording media to write the data in the recording medium and receives a response to the write command, that is transmitted from each of the plurality of recording media, in accordance with a timing signal obtained by delaying the clock signal, and a control unit controls the communication unit to execute relay recording of, if data is transmitted and written in a first recording medium of the plurality of recording media, continuing the write of the data by switching a transmission destination of the data from the first recording medium to a second recording medium of the plurality of recording media.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: January 28, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Noboru Omori
  • Patent number: 10534396
    Abstract: There is disclosed a synchronous digital circuit having a system clock and for processing a data signal, wherein the digital circuit comprises a data path, a hard macro having a macro input, a logic circuit in the data path upstream of the macro input and having a first part and a second part, the second part being immediately upstream of the macro input, a set-up timing error detector having an input, wherein the input is on the data path between the first part and the second part, and a timing correction unit, wherein the data transit time across the second part is equal to or less than one half of a clock period, and wherein the timing correction unit is configured to correct, in response to the set-up timing error detector detecting a set-up timing error, the detected set-up timing error before the data reaches the macro input.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 14, 2020
    Assignee: NXP USA, Inc.
    Inventors: Sebastien Fabrie, Juan Echeverri Escobar, Jose Pineda De Gyvez
  • Patent number: 10503201
    Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: December 10, 2019
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Abhijit M. Abhyankar, Kun-Yung Chang, Frank Lambrecht
  • Patent number: 10504581
    Abstract: A memory apparatus and an operating method thereof are provided. The memory apparatus includes a memory, a temperature sensor and a control circuit. The temperature sensor senses a temperature of the memory and generating a temperature sensing signal. The control circuit is coupled to the memory and the temperature sensor. The control circuit performs access operation on the memory and changes a frequency of the access operation with reference of a delay curve according to the temperature sensing signal.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 10, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Wen-Ming Lee, Chuan-Jen Chang
  • Patent number: 10490242
    Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Masoud Zamani, Bilal Zafar, Venkatasubramanian Narayanan
  • Patent number: 10475499
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may leverage non-volatile memory properties of a ferroelectric capacitor—e.g., that a ferroelectric capacitor may remain polarized at one of two states without a voltage applied across the ferroelectric capacitor—to activate a subset of sensing components corresponding to multiple memory cells with a common word line. For example, a first and second set of memory cells with a common word line may be selected for a read operation. A first set of sensing components corresponding to the first set of memory cells may be activated for the read operation, and a second set of sensing components that correspond to the second set of memory cells may be maintained in a deactivated state.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: November 12, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Christopher John Kawamura
  • Patent number: 10476490
    Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jaskirat Bindra, Kumar Lalgudi
  • Patent number: 10474215
    Abstract: A control apparatus includes functional modules and an arbitration unit. Each functional module includes a memory capable of transitioning, per a control signal, between a first power state and a second power state consuming lower power than the first power state. The arbitration unit performs control to cause a power state of the memory of one of the functional modules to make a transition. Each functional module receiving a request for power state transition of the memory makes an inquiry of whether the power state of the memory can transition to another state. In response to the inquiry, the arbitration unit issues a permission for transition of the power state of the memory of one of the functional modules. The functional modules that have received the permission from the arbitration unit control the control signal input to the memory, to make the transition of the power state of the memory.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: November 12, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masanori Ichikawa
  • Patent number: 10474217
    Abstract: A control apparatus for controlling a device having a power-saving mode includes a processing unit, a reset control unit configured to control reset of the processing unit, a power control unit configured to control supply of power to the processing unit, a memory configured to store reset instructions for causing the reset control unit to perform reset of the processing unit and power control instructions for causing the power control unit to cause to stop supply of power to the processing unit, and a memory control unit configured to perform a refresh operation of the memory, and the processing unit acquires the reset instructions and the power control instructions from the memory after performing processing to restrict the memory control unit from performing the refresh operation until the processing unit acquires the reset instructions and the power control instructions from the memory.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: November 12, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yasuo Hirouchi
  • Patent number: 10468080
    Abstract: A memory device includes a first strobe delay circuit delaying a first data strobe signal to generate a delayed first data strobe signal, a first write leveling circuit sampling a first delay clock in synchronization with the delayed first data strobe signal, a second strobe delay circuit delaying a second data strobe signal to generate a delayed second data strobe signal, a replica second strobe delay circuit delaying the first data strobe signal by a delay value obtained by replicating the second strobe delay circuit to generate a replica delayed second data strobe signal; and a second write leveling circuit sampling a second delay clock in synchronization with the delayed second data strobe signal in a first I/O mode, and sampling the second delay clock in synchronization with the replica delayed second data strobe signal in a second I/O mode.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 5, 2019
    Assignee: SK hynix Inc.
    Inventors: Dae-Ho Yun, Woong-Kyu Choi
  • Patent number: 10460802
    Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 29, 2019
    Assignee: Ovonyx Memory Technology, LLC
    Inventor: Hernan Castro
  • Patent number: 10460795
    Abstract: A semiconductor device includes a latch circuit receiving a first signal, generated in synchronization with a clock signal, from a pulse generation circuit, and generating a second signal; a first delay circuit receiving the second signal from the latch circuit, and generating a third signal by delaying the second signal; a second delay circuit receiving the third signal from the first delay circuit, and generating a fourth signal by delaying the third signal; and a logic circuit receiving the second and fourth signals from the latch and second delay circuits, respectively, and generating a word line control signal based on one of the second signal and the fourth signal. The latch circuit generates the second signal of a first level based on the first signal, and generates the second signal of a second level, which is different from the first level, based on the third signal.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichiro Ishii, Makoto Yabuuchi, Masao Morimoto