Abstract: A memory core characteristic screening method includes the following steps. A command signal transmitting step includes configuring a processing module to transmit a command signal to a memory device. A first internal operating step includes configuring the memory device to operate a first operation to one of a word line, a bit line pair and a column line after a first strobe signal delay time according to a first command. A second internal operating step includes configuring the memory device to operate a second operation to another one of the word line, the bit line pair and the column line after a second strobe signal delay time according to a second command. A memory core characteristic screening step includes screening a memory core characteristic by shorting a timing between the first strobe signal delay time and the second strobe signal delay time.

Abstract: An input output control device between a verification circuit and a semiconductor memory device includes: a first port that receives a read transaction for requesting reading of data in the semiconductor memory device from the verification circuit, and outputs a read response to the verification circuit; a second port that outputs the read transaction to the semiconductor memory device, and receives the read response output from the semiconductor memory device in response to the read transaction; and a buffer device that delays at least one of an output of the read transaction to the semiconductor memory device and an output of the read response to the verification circuit.

Abstract: A memory controller includes a register to store phase offset value. The phase offset value represents a phase relationship between a memory request signal component and a reference signal. The phase offset value is established through write and read back testing. Transmit circuitry applies the phase offset value in launching the memory request signal component from the IC memory controller to an IC memory device.

Abstract: Provided are a data transmission circuit, a data transmission method, and a storage device. The data transmission circuit includes a controllable delay module and a mode register data processing unit. The controllable delay module is configured to generate a delayed read command in response to a mode register read command. The mode register data processing unit is configured to read setting parameters from a mode register in response to the mode register read command, and to output the setting parameters in response to the delayed read command. Here, a time difference between a start moment of outputting of the setting parameters and a moment when the controllable delay module receives the mode register read command is a first preset threshold.

Abstract: Methods, systems, and devices for voltage detection for managed memory systems are described. In some cases, a memory system may include circuitry to monitor one or more supply voltages to the memory system or voltages generated by the memory system to determine whether a voltage rises above an operational range. In some cases, an overvoltage detector may include an undervoltage detector that has been tuned or manufactured to have a higher threshold than an undervoltage detector used to determine whether a voltage has fallen below the operational range. Accordingly, the memory system may monitor a voltage using an undervoltage detector having a threshold corresponding to a lower bound or lower operation point of the operational range of the monitored voltage and an overvoltage detectors having a threshold corresponding to the upper bound or upper operational point of the operational range.

Abstract: In a simulation apparatus for a cockpit system of a vehicle, a driving environment simulation unit performs simulation of a driving environment of the vehicle involving a driving behavior to acquire driving behavior data and generate a travel image as an image simulating scenery visible from the vehicle during travelling. A travel image display unit displays the travel image. A component display unit displays an image of a component generated based on the driving behavior data. A processing load calculation unit calculates a processing load of the simulation apparatus based on at least one of a time difference between acquisition of the driving behavior data and display of the image of the component corresponding to the driving behavior data and a time difference between acquisition of the driving behavior data and display of the travel image generated in response to the driving behavior data.

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

Abstract: A memory device including a first memory cell, a first tracking cell, a tracking bit line, a second tracking cell and a word line driver. The first memory cell is configured to receive a first word line signal. The first tracking cell is configured to emulate the first memory cell. The tracking bit line is configured to transmit a tracking bit line signal to the first tracking cell. The second tracking cell is configured to adjust the tracking bit line signal according to the first word line signal. The word line driver is configured to adjust the first word line signal according to the tracking bit line signal and a first distance between the second tracking cell and a common node on the tracking bit line.

Abstract: A clock distribution network includes a global clock tree and a local clock tree. When the clock distribution network is activated, the local clock tree is first activated, and the voltage levels of first and second output clock signals are set as a common mode voltage level. When the global clock tree is activated, the global clock tree generates first and second global clock signals from first and second input clock signals. The local clock tree generates the first and second output clock signals from the first and second global clock signals.

Abstract: A method and system to provide timebase synchronization for multiple processors in a multi-processor sensor system, where each processor operates according to a respective reference clock, and where the processors' respective reference clocks are off sync from each other. An example method includes simultaneously injecting a synchronization pulse respectively into the multiple processors. Further, the method includes recording for each processor, according to the processor's respective reference clock, a respective synchronization-pulse timestamp of the simultaneously injected synchronization pulse, comparing the respective synchronization-pulse timestamps recorded for the processors, and, based on the comparing, computing for each processor a respective time offset. Additionally, the method includes using the per-processor computed time offsets as a basis to provide a synchronized timebase across the processors.

Abstract: A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is “0”; and clamping the output end at a clamping voltage when the first signal is “1”.

Abstract: Described is an integrated circuit with a driving amplifier that transmits a signal over a link (e.g. a wire) by raising and lowering a voltage on the link. A reference oscillator provides an error measure for the rate at which the voltage transitions between voltages, the slew rate. Slew-rate calibration circuitry adjusts the driving amplifier responsive to the error measure.

Abstract: Various implementations described herein refer to a method for providing memory with one or more banks. The method may include coupling read-write column multiplexer circuitry to the memory via bitlines including coupling a write column multiplexer to the bitlines for write operations and coupling a read column multiplexer to the bitlines for read operations. The method may include performing concurrent read operations and write operations in the one or more banks of the memory with the write column multiplexer and the read column multiplexer via the bitlines.

Abstract: A semiconductor device includes: a memory cell array including a plurality of memory cells; a data input/output circuit suitable for outputting data provided from the memory cell array in response to a couple of data output control signals; and a data output control circuit suitable for generating a couple of latch read enable signals and a couple of data output control timing signals based on a couple of complementary read enable signals, an internal enable signal and warming-up cycle information indicating different warming-up cycles, and outputting, according to the couple of data output control timing signals, the couple of data output control signals using the couple of latch read enable signals, one or more pulses of each of which are masked according to the warming-up cycle information.

Abstract: A method for handling a read error on a block of a memory device is disclosed. In response to a read failure indicating that at least one error handling mechanism has handled the read error on the block and fails to read data stored in the block, a memory test is trigged to be performed on the block. The memory test is configured to determine whether the block malfunctions.

Abstract: A memory device includes a memory block including a first adjacent word line, a selected word line, and a second adjacent word line provided in a direction perpendicular to a substrate and an address decoding circuit. In a first setup period in which the selected word line is set up, the address decoding circuit is configured to apply a first pre-setup voltage to the first adjacent word line, apply a first setup voltage that is higher than the first pre-setup voltage to the first adjacent word line, apply a second pre-setup voltage to the second adjacent word line, and apply a second setup voltage that is higher than the second pre-setup voltage to the second adjacent word line. The first pre-setup voltage is higher than the second pre-setup voltage.

Abstract: A semiconductor memory device includes a memory cell storing data; a signal pad inputting write data to the memory cell and from which read data read from the memory cell is output to an external controller; a first control pad receiving a first timing control signal from the external controller; and a second control pad outputting a second timing control signal to the external controller. In a first time period after a data out command is received, dummy data are output from the signal pad while the second timing control signal from the second control pad is toggling in response to toggling of the first timing control signal input to the first control pad. In a second time period after the first time period, read data are output from the signal pad while the second timing control signal is toggling in response to toggling of the first timing control signal.

Abstract: A memory circuit includes: a memory configured to store a data unit and parity bits, the parity bits including data parity bits based on the data unit and write address parity bits based on a write address associated with the stored data unit; a write address port configured to receive the write address for the stored data unit; a first decoding circuit configured to determine when a data error exists based on the stored data unit and the data parity bits; a second decoding circuit configured to generate a decoded write address from a read address and the write address parity bits; and an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.

Abstract: Disclosed are a data writing circuit, a data writing method, and a memory. The data writing circuit includes: a delay generation circuit, configured to generate a sub-grab signal of each storage area based on an initial grab signal and data transmission delay of each storage area, and generate a grab enable signal based on all of the sub-grab signals. A time interval between the time that each storage area receives data transmitted by a global data line and the time of receiving a column selection signal meets a preset range. A read-write control circuit writes data on a data bus into the global data line based on the grab enable signal. The global data line transmits the data to the storage area by using a column decoding circuit based on the column selection signal, so as to optimize tCCD of DRAM.

Abstract: Systems, methods, and apparatus to select an enhanced write pulse for a write operation in a memory device. In one approach, stronger reset pulses are triggered when there is an increased risk of memory cell threshold voltage degradation. Memory cells read by a relatively higher number of read operations are recorded by a controller of a memory device by updating a lookup table with addresses of the memory cells read. For a new write operation, the controller determines if a reset on set write operation is to be performed. The controller also searches the lookup table to determine if an address for the target bits or codeword of the write operation are in the lookup table. If both conditions are satisfied, then the magnitude of the write pulse is increased for programming the memory cells.

Abstract: A nonvolatile memory device includes: a memory cell array including three or more planes; a first clock generator generating a first clock signal having a first period; a second clock generator generating a second clock signal having a second period that varies with the temperature; a plurality of clock switching controllers outputting one of the first and second clock signals as a reference clock signal; a control logic including a plurality of bitline shutoff generators, which output a plurality of bitline shutoff signals based on the reference clock signal; and a plurality of page buffers connecting bitlines of the planes and data latch nodes in accordance with the bitline shutoff signals.

Abstract: The present invention relates to a signal synchronization adjustment method and a signal synchronization adjustment circuit, for applying to data reading according to a reference clock signal between a memory controller and a dynamic random access memory in an electronic device. First, the memory controller triggers a command signal to the dynamic random access memory; then, the dynamic random access memory delays for a column selection signal latency time according to a first rising edge of the reference clock signal, and then triggers a column selection signal; after that, the dynamic random access memory delays for an internal data strobe signal latency time, and then triggers an internal data strobe signal; finally, the dynamic random access memory delays for an external data strobe signal latency time, and then triggers an external data strobe signal. The signal synchronization adjustment circuit is applied to the signal synchronization adjustment method.

Abstract: The present invention provides a frequency-halving latch circuit for deterministic field bus network data forwarding and application thereof. The frequency-halving latch circuit includes a data buffer equipped with two buffer units; a frequency-halving enable latch signal generation module for generating a first frequency-halving latch signal and a second frequency-halving latch signal with opposite levels, and selecting data buffer units of the data buffer based on the first frequency-halving latch signal, the second frequency-halving latch signal and a receiving enable signal; and a shift register including a first trigger and a second trigger which are initialized to opposite output states, the first trigger and the second trigger is connected to realize a shift operation, and data stored in the data buffer units is finally selected and read based on a low order in the shift register composed of the two triggers and a read enable signal.

Abstract: Delay elements and multiplexers are in programmable delay elements. Each programmable delay element has a chain of delay elements to produce successive delays of a clock of the programmable delay element. Each programmable delay element has a first multiplexer to select among an input clock and delay element outputs in the chain of delay elements to produce a skewed clock output of the programmable delay element. In at least a subset of the programmable delay elements, each programmable delay element has a second multiplexer to select among clocks that include a first clock, and a second clock that is from one of the delay elements of another programmable delay element to produce the clock of the programmable delay element.

Abstract: Provided is a memory interface device. A memory interface device, comprising: a DQS input buffer configured to receive input data strobe signals and output a first intermediate data strobe signal, the DQS input buffer providing a static offset; an offset control circuit configured to receive the first intermediate data strobe signal and output a second intermediate data strobe signal; and a duty adjustment buffer configured to receive the second intermediate data strobe signal and output a clean data strobe signal, wherein the offset control circuit provides a dynamic offset using the clean data strobe signal.

Abstract: Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.

Abstract: A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.

Abstract: A computing system includes host and a storge device. The host includes a host memory and a user interface. The storage device provides the host with a first request including device setting inquiry information, and sets a device configuration based on a first response to the device setting inquiry information received from the host. The host provides the storage device with the first response acquired from a user through the user interface in response to the first request. The device setting inquiry information includes at least one of information on allocation of a map buffer in the host memory, information on allocation of a write buffer in a buffer region of the storage device, or information on a power level of the storage device.

Abstract: Programming a plurality of non-volatile memory cells includes performing a soft erase process during the programming. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging.

Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

Abstract: A memory device comprising a plurality of memory cells situated in a first cell field, multiple first bit lines, each respectively connected to multiple memory cells of the first cell field to enable access to the memory cells via the bit line, and multiple sense amplifier pairs which respectively comprise a first and a second sense amplifier. Each first bit line is assigned to a sense amplifier pair, each first bit line being connected to a respective first semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the first sense amplifier of the sense amplifier pair, to which the bit line is assigned. Each first bit line is connected to a respective second semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the second sense amplifier of the sense amplifier pair, to which the bit line is assigned.

Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device. The block includes a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to concurrently program a remaining set of the plurality of wordlines of the block to a threshold voltage.

Abstract: The structure includes transistors in rows and columns and each having an electric field-based programmable threshold voltage at either a first threshold voltage (VT) or a second VT. The structure further includes first and second signal lines for the rows and columns, respectively. Each first signal line is connected to transistors in a row and each second signal line is connected to transistors in a column. When operated in a switch mode, the transistors may or may not become conductive depending upon their respective VTs. Conductive transistors form connected pairs of first and second signal lines and, thus, create signal paths. The structure can also include mode control circuitry to selectively operate the transistors in either a program mode to set a first VT or an erase mode to set a second VT and to concurrently operate the transistors in the switch mode.

Abstract: A system includes a first device, coupled to a link, which transmits a signal having a repeating pattern on one or more paths of the link. The system includes a second device coupled to the link and including one or more circuits and a time-to-digital converter (TDC). The second device is to receive at the one or more circuits the signal. The second device is to determine, by the TDC, a current duty cycle of the signal, the current duty cycle having a first duration associated with a first portion of the signal and a second duration associated with a second portion of the signal. The second device is further to determine the current duty cycle fails to satisfy a condition associated with a target duty cycle in response to determining the current duty cycle of the signal and adjust the current duty cycle to obtain an adjusted duty cycle.

Abstract: Methods and systems for an advanced initialization bus (AIB) are presented. In an aspect, an AIB master sends, to an AIB slave, a serial clock over a first signal line, and performs a read operation with the AIB slave. Performing the read operation comprises sending a read command to the AIB slave via a bus comprising at least one bidirectional input/output (I/O) channel, each I/O channel having its own respective signal line, sending a read address to the AIB slave via the bus, receiving a copy of the serial clock from the AIB slave over a second signal line, and latching read data provided by the AIB slave via the bus into a read buffer using the copy of the serial clock as a data strobe. Thus, the AIB master latches the read data provided by the AIB slave using a read strobe also provided by the AIB slave.

Abstract: Systems and techniques to offset conditions affecting propagation delay of a clock signal in a memory device. These include a device that includes a clock adjustment circuit, comprising a differential amplifier, an inverter coupled to a first output of the differential amplifier, and a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier. The swing oscillator driver includes a series of transistors, a signal path coupled to at least a first transistor of the series of transistors, wherein the signal path when in operation transmits a signal having a first voltage, and a strength control circuit coupled to the signal path, wherein the strength control circuit when in operation adjusts the first voltage of the signal to a second voltage.

Abstract: Mixed clock domain signaling and, more particularly, mixed clock domain signaling for light-emitting diode (LED) packages arranged for cascade communication is disclosed. Mixed clock domain signaling involves digital communication where time-positions of bit pulse edges in a communication channel are derived from multiple uncorrelated clock domains, including an original clock domain from a master controller and a local clock domain. In the context of LED displays, serial strings of LED packages are arranged as LED pixels to receive cascade communication signals, and the original clock domain is derived from a master controller and a local clock domain is derived at each LED package. By providing for the bit period to be maintained and correlated to the original clock domain throughout the repeated cascade communication, problems associated with multiple uncorrelated clock domains in the communication channel, such as sampling jitter, may be averted, thus avoiding loss of data integrity.

Abstract: A semiconductor device can be applied to a memory device. The semiconductor device of the disclosure includes a voltage sensor, a convertor and a command/address on-die-termination (CA_ODT) circuit. The voltage sensor receives a voltage setting command, and sense a voltage level of the voltage setting command to generate a sensing signal. The convertor generates a setting signal in response to the sensing signal. The CA_ODT circuit generates a power voltage for the memory device in response to the setting signal, wherein a voltage level of the power voltage corresponds to the voltage level of the voltage setting command.

Abstract: A device is provided. The device includes multiple transistors, a first sense circuit, and a precharge circuit. The transistors are coupled to a tracking bit line and configured to generate a first tracking signal. The first sense circuit is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge and a falling edge of the first sense tracking signal, a precharge signal for precharging data lines.

Abstract: A timing of an execution of a command in a memory device can be affected delay elements. The delay elements of a unit of delay elements can cause variable delays of the command paths. The delay elements can be activated based on settings stored in a fuse array of a memory device. The delay elements can be used to change a timing of current draw of the memory devices.

Abstract: A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.

Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

Abstract: A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.

Abstract: The present disclosure provides systems and methods for adjusting the playback speed of accessories based on the buffer level of the received content. The accessories may receive content from a host device at a certain speed. The incoming speed of the content may be different than the playback speed of the content. Therefore, a buffer level of the received content may be determined using a linear least square (“LLS”) fit of the buffer level, the average of the buffer level, or a phased locked loop (“PLL”) approach. Based on a difference between the buffer level and the playback speed, a speed adjustment may be determined. Instructions may be transmitted from a primary accessory to a secondary accessory to adjust the playback speed by a certain amount at a certain time. This may ensure that the accessories remain in sync. The accessories may then adjust their respective playback speeds.

Abstract: Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.

Abstract: Various implementations described herein are directed to a method. The method may receive an address to access data stored in memory. The method may enable a data access pipeline to perform memory access operations so as to access the data stored in the memory based on the address. The method may dynamically adjust the data access pipeline during the memory access operations so as to output the data based on the address.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory controller is disclosed. The IC memory controller includes a first controller command/address (C/A) interface to transmit first and second read commands for first and second read data to a first memory C/A interface of a first bank group of memory. A second command/address (C/A) interface transmits third and fourth read commands for third and fourth read data to a second memory C/A interface of a second bank group of memory. Receiver circuitry receives the first and second read data via a first data link interface and the third and fourth read data via the second data link interface. For a first operating mode, the first and second read data are received after respective first delays following transmission of the first and second read commands and at a first serialization ratio.

Abstract: Method and circuit for adaptive column-select line signal generation for a memory device are provided. The method comprises the following steps. A first signal is generated in response to a memory access command. A second signal is generated according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted. A column-select line signal is generated according to the first signal and the second signal.

Abstract: A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.