Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator and a control logic circuit for programming a selected memory cell of the memory cell array to a selected word line into a first program state by controlling the voltage generator and a verify operation on the memory cell array. The control logic circuit controls a first word line voltage applied to an adjacent word line not to be programmed in the verify operation to be different from a read voltage level of a read voltage applied in a read operation of the nonvolatile memory and controls a bit line voltage applied to a bit line in the read operation. The control logic circuit controls the voltage generator to apply a plurality of different and decreasing verify voltages to the selected word line in the verify operation.

Abstract: Systems and methods related to memory devices that may perform error check and correct (ECC) functionality. The systems and methods may employ ECC logic that may be shared between two or more banks. The ECC logic may be used to perform memory operations such as read, write, and masked-write operations, and may increase reliability of storage data.

Abstract: According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array by controlling the vo

Abstract: An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

Abstract: A liquid crystal panel driving circuit and a liquid crystal display device are provided. Every three sub-pixel unit columns are defined as a row cycle that comprises a first data line, a second data line, and a third data line coupled to a same data driving signal output line of the data driver via the switch unit. The switch unit is configured to control the first data line, the second data line, and the third data line to output data signals in different output orders.

Abstract: In non-volatile memories, bit lines and word lines commonly to driving and decoding circuitry on a single end. Techniques are presented for determining the time constant associated with charging the far end of such lines from the near end, at which the circuitry is connected. While driving a discharged line from the near end, the number of clock cycles for the current to drop from a first level to a second level can be used to estimate the time constant for the far end. Alternately, the line can be initially charged up, after which the current is monitored at the near end. The differences in time constants for different word lines can be used to vary the time used when accessing a selected word line.

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a first and second fin overlying a substrate, where the first and second fins intersect at a fin intersection. The first fin has a first fin left end. A tunnel dielectric and a floating gate are formed adjacent to the first fin with the tunnel dielectric between the floating gate and the first fin. An interpoly dielectric is formed adjacent to the floating gate, and a control gate is formed adjacent to the interpoly dielectric such that the interpoly dielectric is between the floating gate and the control gate. The control gate, interpoly dielectric, floating gate, and the tunnel dielectric are removed from over the first fin except for at a floating gate position between the first fin left end and the fin intersection.

Abstract: A semiconductor memory device includes a memory block configured to include memory cells coupled to word lines and a peripheral circuit configured to perform a first program operation, a program verifying operation and a second program verifying operation for memory cells coupled to a word line selected from the word lines, and supply program allowable voltages having different levels to selected bit lines of program allowable cells located between program inhibition cells in the first program operation and the second program operation.

Abstract: Integrated circuits with wireless communications circuitry having peak cancelling circuitry operable to perform crest factor reduction is provided. The peak cancelling circuitry may include a peak detection circuit, a delay circuit, and peak cancellation pulse generation circuitry. The peak cancellation pulse generation circuitry may include multiple pulse generation blocks coupled in a cascade configuration. Each pulse generation block may include a counter for providing memory address signals, a register for latching peak scaling factor information, a pulse memory block for storing a respective sub-pulse, and a multiplier for scaling the stored sub-pulse by the latched peak scaling factor. The pulse memory block may be implemented using single-port memory or dual-port memory.

Abstract: There are provided a memory element and a memory device with improved writing and erasing characteristics during operations at a low voltage and a low current. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, an ion source layer provided on the second electrode side, an intermediate layer provided between the resistance change layer and the ion source layer, and a barrier layer provided at least either between the ion source layer and the intermediate layer, or between the intermediate layer and the resistance change layer, and the barrier layer containing a transition metal or a nitride thereof.

Abstract: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips.

Abstract: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips.

Abstract: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.

Abstract: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit.

Abstract: A multilevel phase change memory cell may have a plurality of intermediate levels between a set and a reset or a crystalline and amorphous states. These intermediate levels between set and reset may be differentiated not only by programming current, but also by different programming pulse widths. As a result, the intermediate states may be positioned, on the programming current versus programming pulse width curve, in regions of common resistance with a relatively large range of programming current.

Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

Abstract: One embodiment of the invention relates to a method for conditioning resistive memory cells of a memory array with a number of reliable resistance ranges, where each reliable resistance range corresponds to a different data state. In the method, group of at least one resistive memory cell is accessed, which group includes at least one unreliable cell. At least one pulse is applied to the at least one unreliable cell to shift at least one resistance respectively associated with the at least one unreliable cell to the highest of the reliable resistance ranges. Other methods and systems are also disclosed.

Abstract: A semiconductor memory apparatus includes a write driver that receives a reset signal, a write enable signal, and a data signal, and transmits data, which is input from the data signal, to an input/output (IO) line when the write enable signal is applied, and an overdrive unit that is connected to the IO line of the write driver and outputs a voltage larger than a driving voltage of the write driver when the write driver outputs a high level.

Abstract: A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.

Abstract: A memory structure and data writing method thereof includes a power supply circuit and a bridge circuit. The bridge circuit is driven by the power supply circuit, and operate in a plurality of conduction modes. The memory structure only requires one set of power supply circuit and does not need to know the resistance of the bit line in advance, also the signal error is hardly occurred when the memory structure is switching between positive and negative.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: The present invention aims at providing a device and method for writing a line with a high degree of precision at high speed. Distance calculation means 311 calculates the start-to-end point distance L of a writing pattern (S502), and number-of-scan-clocks calculating means 312 calculates the number of scan clocks required to write the writing pattern based on the start-to-end point distance L and a unit distance corresponding to the minimum time resolution for a high-speed D/A converter 306 (S503). Count conversion means 605 separates the start-to-end point distance L into X and Y components to convert them in an equation using the number of scan clocks (S504). Based on the equation, variable rate calculating means 314 calculates an extinction ratio to determine the extinction ratio at a variable attenuator 307 (S505).

Abstract: A method for reading the magnetization orientation of a memory cell includes applying a magnetic field to the memory cell, observing any change in resistance of the memory cell as the magnetic field is applied, and determining the magnetization orientation based upon the observed change in resistance of the memory cell.

Abstract: A test structure for determining the resistance of a conducting junction between an active region of a selection transistor and a storage capacitor in a matrix-type cell array where the active regions of the selection transistors are in rows in a first direction and the storage capacitors are in rows in a second direction running perpendicular to the first direction. The conducting junctions between the active regions of the selection transistors and the storage capacitors are formed at overlapping areas of the mutually perpendicular rows each in a single edge region of the overlapping area in the first direction. The active regions of the selection transistors and/or the storage capacitors are connected by tunnel structures or bridge structures in the second direction in the region adjoining the junction to be measured between the active region of the selection transistor and the storage capacitor. This achieves a low-impedance connection to the junction to be measured.

Abstract: This invention generally relates to solution-based molecular shuttle devices. More particularly, this invention relates to solution-based molecular switches, molecular assemblies, and molecular memory devices and methods for producing the same. In some embodiments the devices are made from molecular chains constructed from molecular subunits which define binding positions and shuttles that are capable of moving along the chains.

Abstract: A cell array is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on a semiconductor substrate. Each of the memory cells has a charge accumulation layer formed via a first gate insulating film and a gate electrode formed on the charge accumulation layer via a second gate insulating film. A control circuit controls the sequence of writing and erasing the data into and from a memory cell selected in the memory cell. In writing the data into the memory cell, a first write operation is to apply a write pulse voltage with a first step-up voltage between the gate electrode and the semiconductor substrate. A second write operation is to apply a write pulse voltage with a second step-up voltage lower than the first step-up voltage.

Abstract: To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference &Dgr;V between data “0” and data “1” can be made smaller than an operational margin of a sense amplifier. This makes it possible to detect a deteriorated ferroelectric capacitor without conducting a cycling test.

Abstract: A virtual wire assembly is disclosed. The assembly comprises a substantially electrically-nonconductive substrate; and a plurality of hermetic feedthroughs each comprising a conductive region extending transversely through the substrate to form a conductive pathway with accessible surfaces at opposing ends thereof, wherein each conductive pathway is electrically isolated from other conductive pathways. In certain embodiments of this aspect of the invention, the substantially electrically-nonconductive substrate is a semiconductor device, and the conductive regions each are comprised of an n-type or a p-type doped semiconductor material. Also disclosed are implanted medical devices requiring electronic or other components to be retained in a hermetic enclosure, such as cochlear and other sensory or neural prosthetic devices.

Abstract: A method of forming a magnetic memory device (and a resulting structure) on a low-temperature substrate, includes forming the memory device on a transparent substrate coated with a decomposable material layer subject to rapid heating resulting in a predetermined high pressure, and transferring the memory device to the low-temperature substrate.

Abstract: In a semiconductor integrated circuit device equipped with a flash memory and an EEPROM which are nonvolatile memories, the invention provides a technique that makes it possible to restrict an EEPROM capacity to a minimum necessary amount and reduce a chip area. Data of a minimal size required for one application program and rewritten frequently is stored in the EEPROM, and the EEPROM is configured to have a capacity of about that minimal size. Data of the same size that are respectively handled by other applications and rewritten frequently are stored in the flash memory. With respect to an application that is actually used, its data stored in the flash memory is transferred to the EEPROM and used. Data transfer between the flash memory and the EEPROM is performed if necessary. Consequently, the EEPROM capacity can be reduced and chip area reduction can be achieved.

Abstract: The present invention provides a multifunctional flash memory drive mainly comprising a main body and an expansion slot for flash memory card; said flash memory drive is designed into a form similar to an U-disk, and the main body has a transmission interface similar to an USB or IEEE1394 plug at an appropriate position to connect to the external equipment end to access data; said expansion slot on the main body is designed to use with one or a plurality of external memory cards to expand the storage capacity; said main body has a circuit board electrically connected to said transmission interface and expansion slot; said circuit board has a main controller, which may play digital audio (MP3, WMV, etc.) and/or detect and determine the type of the memory cards inserted in said expansion slot and/or process signals transmitted between said transmission interface and said external equipment end. In that way, said flash memory drive achieves multi functions.

Abstract: First to third logic circuits and first to third static random access memories (SRAMs) are formed on one chip. Power to the first and third logic circuits and their SRAMs is shut off as required, while power to the second logic circuit and its SRAM is kept supplied. The third SRAM has the largest memory capacity. The average channel width of the first to third SRAM cell arrays is set at a half or less of that of the other circuit blocks, and the channel impurity concentration of the second and third SRAM cell arrays, which operate at low speed, is set higher than that of the first SRAM cell array, which operates at high speed, by additional ion implantation. By these settings, MOS transistors of low threshold voltage (Vt) are provided for the first SRAM cell array, while MOS transistors of high Vt are provided for the second and third SRAM cell arrays for leakage reduction.

Abstract: A memory agent may have a redrive circuit having a plurality of redrive paths, and a deskew circuit separate from the plurality of redrive paths. A deskew circuit may be integral with or separate from a redrive circuit having the plurality of redrive paths. A deskew circuit may be coupled between a redrive circuit and a memory device or interface.

Abstract: A memory agent may include a link interface having a plurality of bit lanes, wherein the memory agent is capable of utilizing more than one of the plurality of bit lanes to detect the presence of another memory agent coupled to the link interface.

Abstract: A circuit arrangement for setting a voltage supply for a read/write amplifier of an integrated memory has a first voltage generator circuit for generating a supply voltage for application to the read/write amplifier during an assessment and amplification operation and a second voltage generator circuit for generating a precharge voltage for precharging bit lines of the memory which are connected to the read/write amplifier. A temperature detector circuit, which is connected to the first voltage generator circuit, is used to detect a temperature of the memory and interacts with the first voltage generator circuit to set the supply voltage applied to the read/write amplifier in a manner depending on a temperature of the memory.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: A nonvolatile semiconductor memory device having a small layout area includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction, wherein each of the memory cells includes a source region, a drain region, a channel region between the source region and the drain region, a word gate and a select gate disposed to face the channel region, and a nonvolatile memory element formed between the word gate and the channel region, wherein the wordline-and-selectline-driver-section includes a plurality of unit wordline-and-selectline-driver-sections, and wherein each of the unit wordline-and-selectline driver sections drives the select gates and the word gates of the memory cells in each row at a single potential.

Abstract: An integrated memory contains a memory cell array, which has word lines and bit lines, and a read/write amplifier, which is connected to the bit lines for the assessing and amplifying data signals. A voltage generator circuit generates a voltage supply for application to the read/write amplifier. A potential difference is applied to the read/write amplifier using different supply potentials. The voltage generator circuit increases the potential difference applied to the read/write amplifier for a limited period of time during an assessment and amplification operation of the read/write amplifier. Charge-dependent control is implemented in the voltage generator circuit. An assessment and amplification operation can be carried out at a comparatively high switching speed and a low power consumption is possible.

Abstract: An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

Abstract: An internal data processing apparatus and method in a mobile station. A NOR flash memory is replaced with a NAND flash memory as a memory for storing internal data, and a modem is interfaced with the NAND flash memory.

Abstract: Unaligned accesses to memory are circumvented by an address exception handler mechanism, which decodes an exception-triggering instruction, and reads from or writes to, in a byte-by-byte manner, addressed portions of memory which are unaligned with an addressing scheme through which accesses to memory may be performed, and thereby give rise to unaligned memory access exceptions. The handler simulates the execution of the instruction with reference to an exception stack frame, to which the contents of all registers at the time of the unaligned address exception are saved. This allows the handler to controllably define values that are restored into registers during the processor's execution of a general exception vector. After handling the exception, program execution transitions to the next instruction that directly follows the exception-causing instruction.

Abstract: A ternary CAM memory device is disclosed which comprises a pair of complementary compare lines, a pair of complementary bit lines, and a unique four transistor two capacitor circuit.

Abstract: There are provided a semiconductor memory device incorporating an ECC which enables an efficient test with high accuracy by a simplified structure and can shorten the test time and a test method thereof. A semiconductor memory device has an ECC circuit capable of correcting, from an m-bit information code and an n-bit check code stored in an information storing part, an error of the information code to x bits, and a parallel test circuit for receiving an information code and a check code for test with the same bits stored in the information storing part and deciding a defect with the x+1 bits or more as being defective. The parallel test circuit decides a defect with the x+1 bits or more for one piece of position information as a defective chip.

Abstract: A circuit for controlling an AC-timing parameter of a semiconductor memory device and method thereof are provided. The AC-timing parameter control circuit includes a delay-time-defining portion, a comparing portion, and a controlling portion. The control circuit compares the pulse width or period of an input signal to one or more different reference-widths pulses, with the reference width(s) set by the delay-time-defining portion and the reference pulses generated by the comparing portion. The controlling portion indicates whether the input signal width or period was less than or greater than each o the reference-width pulses. The control circuit output signals can be used to tailor the operation of the device based on a direct comparison of an AC-timing parameter to one or more reference values.

Abstract: Method for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal, and a test device thereof. In the present invention a plurality of memory cells are formed in the memory area and at least one test device is formed in the scribe line region simultaneously. A first resistance and a second resistance are detected by the test device. Normal alignment of the bit line and the bar-type active area of the test device is determined according to the first resistance and the second resistance. Finally, whether the alignment of the bit line contacts and the active areas in memory areas is normal is determined according to whether the alignment of the bit line contact and bar-type active area of the test device is normal.

Abstract: A semiconductor storage device with high soft-error immunity is obtained. A semiconductor storage device has SRAM memory cells. NMOS transistors (Q1, Q4) are driver transistors, NMOS transistors (Q3, Q6) are access transistors, and PMOS transistors (Q2, Q5) are load transistors. An NMOS transistor (Q7) is a transistor for adding a resistance. The NMOS transistor (Q7) has its gate connected to a power supply (1). The NMOS transistor (Q7) has one of its source and drain connected to a storage node (ND1) and the other connected to the gates of the NMOS transistor (Q4) and the PMOS transistor (Q5). The resistance between the source and drain of the NMOS transistor (Q7) can be adjusted with the gate length, the gate width, the source/drain impurity concentration, etc., which is, for example, about several tens of kilohms (k&OHgr;).

Abstract: A new method of performing the write operation on the MRAM bit cell with improved switching selectivity and lower write current requirements is achieved utilizing oscillating word write currents at frequency near the ferromagnetic resonance frequency of the free layer, combined with the shift in said frequency due to the magnetic field produced by the current in the bit line. Operation is implemented in a conventional magnetic random access memory having a plurality of magnetoresisitive cells formed by an intersection of a grid of word and bit lines, wherein an individual cell within the grid can be selected and switched from one magnetic state to another by the magnetic fields produced by the currents in the word and bit lines.

Abstract: To provide an optoelectronic-device substrate used for a display panel for displaying an image with high quality and high contrast, a method for driving the substrate, a digitally-driven liquid-crystal display, an electronic apparatus, and a projector. In an optoelectronic-device substrate 100 having a memory-cell array including a plurality of memory cells 101 that is arranged in matrix form and digitally driven, each memory cell 101 has an analog switch SW1 for inverting the phase of data transmitted thereto, or data having an inverted phase is transmitted to the memory cell 101.

Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.