Abstract: To provide an optoelectronic-device substrate used for a display panel for displaying an image with high quality and high contrast, a method for driving the substrate, a digitally-driven liquid-crystal display, an electronic apparatus, and a projector. In an optoelectronic-device substrate 100 having a memory-cell array including a plurality of memory cells 101 that is arranged in matrix form and digitally driven, each memory cell 101 has an analog switch SW1 for inverting the phase of data transmitted thereto, or data having an inverted phase is transmitted to the memory cell 101.

Abstract: Disclosed herein is a magnetic head including a main magnetic pole and a return yoke. The magnetic head can suppress a side writing at an edge of the return yoke even if the soft magnetic layer of a disk is saturated. The magnetic head further includes a single-pole type head that is used as write head.

Abstract: A content addressable memory device includes a plurality of memory banks. A faulty memory bank, if present, is excluded from the memory capacity thereof so that the content addressable memory device is used with the memory capacity thereof reduced. The content addressable memory device includes a plurality of banks, each bank including a plurality of words for storing data, an excluded bank information memory for storing information concerning an excluded bank, a mapping circuit for mapping an enable signal designating a bank to a bank other than the excluded bank, based on the excluded bank information, and a demapping circuit for mapping, to bank addresses including the address of the excluded bank, a hit signal representing that a word storing data corresponding to input search data is present in its own bank.

Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.

Abstract: According to one embodiment, a memory cell is disclosed. The memory cell includes a first PMOS transistor, a first NMOS transistor coupled to the first PMOS transistor, a second PMOS transistor and a second NMOS transistor coupled to the first PMOS transistor. The first and second PMOS transistors receiving a bias control signal.

Abstract: A RAM memory circuit has at least one memory bank with a multiplicity of memory cells arranged like a matrix in rows and columns and is subdivided into q≧2 areas, each of which comprises p≧1 segments each comprising a plurality of columns. Each segment is assigned a bundle of master data lines, which branches from an area bus assigned to the relevant area and, for its part, branches via a switching network to the memory cells of the relevant segment. The area buses can be connected cyclically to a common data port. In order to allow a read operation the beginning of which overlaps the end of a preceding write operation, each master data line bundle has coupled to it a data latch for holding the data respectively appearing there, and an isolating switch is in each case provided between each master data line bundle and the assigned area bus.

Abstract: The multiple bit, vertical memory cell includes a vertical metal oxide semiconductor field effect transistor (MOSFET) extending horizontally outward from a substrate. The MOSFET has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. The gate insulator may be a composite of oxide-nitride-aluminum oxide. The MOSFET is operated with either the first source/drain region or the second source/drain region serving as the source region, depending on the voltages applied to these regions. A negative substrate bias is applied during programming and erasing operations to enhance hot carrier injection.

Abstract: A test structure for determining the resistance of a conducting junction between an active region of a selection transistor and a storage capacitor in a matrix-type cell array where the active regions of the selection transistors are in rows in a first direction and the storage capacitors are in rows in a second direction running perpendicular to the first direction. The conducting junctions between the active regions of the selection transistors and the storage capacitors are formed at overlapping areas of the mutually perpendicular rows each in a single edge region of the overlapping area in the first direction. The active regions of the selection transistors and/or the storage capacitors are connected by tunnel structures or bridge structures in the second direction in the region adjoining the junction to be measured between the active region of the selection transistor and the storage capacitor. This achieves a low-impedance connection to the junction to be measured.

Abstract: In a nonvolatile semiconductor memory device capable of the storage of multivalued data, fast writing can be realized with high reliability. In such a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages of data, writing of data having one threshold voltage that is the remotest to an erased state is performed prior to writing of the data having the other threshold voltages (write #1). Writing of the data having the other threshold voltages is then sequentially performed starting from the data having the nearer threshold voltage to the erased state. When writing each of the data having the other threshold voltages, writing of the data is simultaneously performed to a memory cell to which the data having the remoter threshold voltage from the erased state (write #2 and write #3).

Abstract: A magnetic recording medium for perpendicular magnetic recording system includes a nonmagnetic substrate and layers sequentially laminated on the substrate. The layers include a seed layer comprised of a metal or an alloy with a face centered cubic crystal structure, a nonmagnetic underlayer of a metal or an alloy with a hexagonal closest packed crystal structure, a magnetic layer having a granular structure including ferromagnetic crystalline grains with a hexagonal closest packed structure and nonmagnetic grain boundary region of mainly oxide surrounding the crystalline grains, a protective layer, and a liquid lubricant layer.

Abstract: The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor device uses a package substrate on which bonding leads which are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads are formed. The semiconductor device further includes an address output circuit and a data input/output circuit which are also served for memory access and a signal processing circuit having a data processing function.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor formed of the first electrode, the second electrode, and ferroelectric layer is within the range of 0.1P(+Vs)<P(−1/3Vs) when the applied voltage is changed from +Vs to −1/3Vs, and 0.1P(−Vs)>P(+1/3Vs) when the applied voltage is changed from −Vs to +1/3Vs.

Abstract: A disk device in which a precut portion of sub cam plate and a protruding portion of locking plate are made in a slanted shape and at the same time the sub cam plate is rotated by a pressure when the protruding portion is inserted into the precut portion.

Abstract: A RAM memory circuit and method for controlling the same includes memory cells disposed in a matrix of rows and columns each addressed for writing in/reading out a datum by activation of a word line assigned to a relevant row and connection of a sense amplifier assigned to a relevant column to a data path. A control device can be set by an immediate-write command, commanding the write operation, to initiate connection of the sense amplifiers selected by the column addresses provided to the data path at an instant ta+Tw, where ta is the instant of activation of the word line selected by a row address provided and Tw is less than a charging time Tc specific to the memory circuit and is necessary, starting from a word line activation, to transfer the datum stored in a memory cell of the relevant row to the respectively selected sense amplifier and amplify it there.

Abstract: A method of forming floating gate memory cells, and an array formed thereby, wherein each memory cell includes an electrical conductive floating gate having a folded structure over and adjacent to a semiconductor block on a semiconductor substrate. An electrical conductive control gate is formed having a portion disposed over and insulated from the floating gate. Spaced apart source and drain regions are formed self-aligned to source and drain lines with a channel region formed therebetween and along a top and sidewalls of the silicon block. An electrical conductive tunneling gate can be optionally provided over and insulated from the control gate by an insulating layer to form a tri-layer structure permitting both electron and hole charges tunneling through at similar tunneling rate.

Abstract: In each of the memory cell arrays in the memory banks, a memory cell row corresponding to each of the word lines extending in a column direction of each of the memory cell arrays store pixel data of each pixel block of first and second rows set in a horizontal way in a search area within a search frame of picture signal. The pixel data of a predetermined pixel block is selectively captured into each of the data buffer through the sense amplifiers and the switches. Selector sequentially extracts pixel data as candidate blocks based on the pixel data of two pixel blocks held in each of the data buffers. The matching circuit matches the pixel data as the extracted candidate blocks against the pixel data as the input reference block using the block-matching process to obtain a motion vector relative to the reference block.

Abstract: The invention relates to a method for testing non-volatile memory devices that have at least one parallel communication interface, and a conventional matrix of non-volatile memory cells with respective reading, changing and erasing circuits, wherein during the testing procedure, a reading mode is entered for reading a memory location upon the rise edge of a control signal producing a corresponding ATD signal. Advantageously in the invention, a subsequent reading step is started also upon the fall edge of the control signal.

Abstract: As a storage cell for surface mounting which reduces the mounting area, increases the reliability of soldering and realizes high-density mounting, provided is a storage cell for surface mounting having: a polar storage cell housing a component between a case and a top cover and sealed with an insulator; an anode terminal connected to an outer surface of the case; and a cathode terminal connected to an outer surface of the top cover. In this storage cell, the anode terminal is provided with an external connection connected to a printed wiring board, the cathode electrode is provided with a mounting-fixing portion connected to an external connection connected to the printed wiring board and the top cover, and a plated layer is formed on the external connections of the anode terminal and cathode terminal and on the mounting-fixing portion of the cathode terminal.

Abstract: In accordance with the present invention, a memory cell includes a pair of non-volatile devices and a pair of DRAM cells each associated with a different one of the non-volatile devices. Each DRAM cell further includes an MOS transistor a capacitor. The DRAM cells and their associated non-volatile devices operate differentially and when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the DRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.

Abstract: A member of supporting magnetic disc substrates is provided, comprising a ceramic sinter containing a ceramic component and at least one conductive component selected from a group consisting of iron, niobium, tin zinc, copper, nickel, cobalt, and chromium, wherein the ceramic sinter has conductive aggregates on its peripheral surface. In the member, the ceramic component may be forsterite and the conductive component is iron oxide, wherein the ceramic sinter comprises a main phase of 2MgO.SiO2 and a secondary phase of at least one of MgFe2O4, Fe3O4 and Fe2O3.

Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z., and multi-bit data in the memory cell is discriminated by the Z-address.

Abstract: A method for reducing imprint in a ferroelectric device which includes the steps of: applying a signal having a bipolar pulse shape for a predetermined time to the ferroelectric device; and decreasing the signal amplitude gradually in predetermined intervals of time and amplitude. Preferably, the bipolar shape signal is a sinusoidal wave, a square wave, or a sawtooth wave and the ferroelectric device is a capacitor of a memory cell in a computer. Also provided is an apparatus for reducing imprint in a ferroelectric device.

Abstract: A semiconductor memory device includes word lines, normal bit lines, a redundant bit line, and normal memory cells for storing data and each of which is coupled to one of the word lines and to one of the normal bit lines. The device also includes redundant memory cells each of which is coupled to one of the word lines and to the redundant bit line. The device further includes a coincidence circuit that receives a first address signal, indicating an address of one of the normal bit lines, and a second address signal, indicating an address of one of the normal bit lines to which a defective memory cell is coupled, and which selects the redundant bit line when the first address signal coincides with the second address signal.

Abstract: A semiconductor device includes: a memory having a memory space for recording data, the memory space including addresses; at least one first storage section for storing at least a portion of an address at which access to the memory space is requested and/or data which is requested to be written to the memory space; and an operation restriction circuit for at least partially restricting operations to be performed on the memory. The operation restriction circuit controls restriction on the operations to be performed on the memory based on at least a portion of the data and/or the address stored in the at least one first storage section.

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: The present invention provides thin film magneto-resistive readout apparatus for providing readout from magnetic memory devices such as magnetic tapes, the apparatus comprising a thin film magneto-resistive readout head element, a narrow pulse generator for applying sensing current to the readout head element in the form of trains of narrow pulses, and a signal averaging circuit connected to receive output signals from the readout head element for deriving an average output signal for the pulses in each train.