Accelerating Charge Or Discharge Patents (Class 365/204)
  • Patent number: 10269415
    Abstract: A semiconductor device includes a semiconductor substrate having an upper surface region and a lower surface region. The lower surface region is recessed relative to the upper surface region so a sidewall region of the semiconductor substrate extends from the lower surface region to the upper surface region. A gate electrode overlies the upper surface region of the semiconductor substrate and is spaced laterally apart from the sidewall region. An epitaxial source/drain region is disposed in the semiconductor substrate between the gate electrode and the sidewall region. A dummy gate electrode is spaced apart from the gate electrode by the epitaxial source/drain region and is disposed over the sidewall region. The dummy gate electrode has a non-planar lower surface having a first peripheral portion extending over the upper surface region, an intermediate portion extending downward along the sidewall region, and a second peripheral portion extending over the lower surface region.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9911473
    Abstract: In some embodiments, a memory device includes a memory bank, a global data line, a first tri-state unit, a latch, a second tri-state unit and a pre-charge unit. The first tri-state unit is configured between the memory bank and the global data line. The latch is configured to provide a state signal based on a data signal from the memory bank. The second tri-state unit is configured between the global data line and the latch. The pre-charge unit pre-charges the global data line to a first intermediate level or a second intermediate level depending on the state signal during the global data line is caused to be electrically isolated from the memory bank by the first tri-state unit and electrically isolated from the latch by the second tri-state unit.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: March 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sahil Preet Singh, Li-Wen Wang, Manish Arora
  • Patent number: 9240228
    Abstract: A static memory apparatus and a data reading method thereof are provided. The static memory apparatus includes a plurality of memory cells, a plurality of dummy memory cells, a sense amplifier, and a discharge current adjuster. The dummy memory cells respectively include a plurality discharge ends for discharging charges on a dummy bit line. The sense amplifier is enabled for a sensing and amplifying operation according to a signal on the dummy bit line, and the sense amplifier generates readout data accordingly. The discharge current adjuster adjusts at least one discharge current on at least one controlled discharge end according to an operating voltage of the memory cells.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: January 19, 2016
    Assignee: Faraday Technology Corp.
    Inventors: Biao Chen, Zhao-Yong Zhang, Hao Wu, Kun-Ti Lee
  • Patent number: 9152909
    Abstract: Devices which store data for a period of time. In one form, devices store data in which the data store is subject to periodic and/or relatively short power outages. In one example, a radio frequency identification (“RFID”) transponder, and more particularly, a RFID transponder that is used in orientation independent applications, is disclosed. Other applications are directed to devices used where a supply power is intermittent. In a first aspect of embodiments described herein, there is disclosed a method of and/or device that includes a memory adapted to store data, a supply of power adapted to provide supply power to the memory, a path of leakage, the leakage path serving, over time, to diminish the integrity of data stored in the memory, and a leakage attenuator adapted to selectively attenuate the rate of leakage.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: October 6, 2015
    Assignee: Sato Vicinity Pty Ltd
    Inventors: Stuart Colin Littlechild, Robert John Clarke, Gary Michael Forsey
  • Patent number: 9030900
    Abstract: A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of the bit line sense amplification unit with an overdriving voltage in an overdriving period and supply an internal voltage line with a voltage of the power line of the bit line sense amplification unit in a discharge driving period.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 12, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sin-Hyun Jin, Sang-Jin Byeon
  • Patent number: 9025404
    Abstract: A semiconductor device with reduced leakage current and a method of manufacturing these reduced leakage current semiconductor devices are disclosed. The reduced leakage current semiconductor devices may be used for both static circuits and dynamic circuits. The reduced leakage current semiconductor devices reduce leakage current in the device when the node is not transitioning which occurs more than 95% of the time.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: May 5, 2015
    Assignee: Cold Brick Semiconductor, Inc.
    Inventor: Gajendra Prasad Signh
  • Patent number: 9013938
    Abstract: Circuits, systems, and methods for discharging loads are provided. One circuit includes a node coupled to a voltage source, a capacitor, a source-follower device coupled between the node and the capacitor, and a current source coupled to the capacitor. The source-follower device is configured to switchably couple the capacitor to the node to discharge the voltage source and the current source is configured to discharge the capacitor. One system includes the above circuit coupled to a memory device such that the circuit is configured to discharge voltage from the memory device. A method includes discharging, via a capacitor coupled to the memory device, a high voltage from the memory device and discharging, via a current source coupled to the capacitor, the high voltage from the capacitor. The capacitor is configured to discharge the high voltage within a predetermined range of time.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: April 21, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Gary Moscaluk, John Tiede
  • Patent number: 9007865
    Abstract: According to some embodiments, an electronic circuit comprises a digital output which is held to a logic one after the power supply was removed, for a time duration in a narrow range. The electronic circuit comprises a first array of elements comprising capacitors and discharging devices (diodes or transistors). A time constant detector detects which elements has the discharging time closest to the target. A second array of elements also comprises capacitors and discharging devices, with discharging durations proportional to the discharging durations of the first array. A decoder charges the appropriate element from the second array. After the power is removed, this charged element starts to discharge. During the discharge duration, a comparator outputs a logic one, and a logic zero after the discharge is completed.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: April 14, 2015
    Inventor: Ion E. Opris
  • Patent number: 8995195
    Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: March 31, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Yacov Duzly, Alon Marcu, Yuval Kenan, Yan Li, Man Lung Mui, Seungpil Lee
  • Patent number: 8995214
    Abstract: According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp FET connected between a first data bus and a second data bus, a first precharge FET connected between the first data bus and first potential, a second precharge FET connected between the second data bus and the first potential, a first storage area connected to the first data bus, and a second storage area connected to the second data bus. The control circuit is configured to generate a precharge state in which the first data bus is precharged to the first potential and the second data bus is precharged to a second potential lower than the first potential, when the data is transferred from the second storage area to the first storage area.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiromitsu Komai
  • Patent number: 8971141
    Abstract: A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit uses one power supply level for the bit line driving path and a second supply level for a data latch of the sense amp. The latch's supply level is of a high level that used for driving the bit lines and can be provided by a charge pump. The sense amp need use only NMOS devices for its analog path. For balancing performance and current consumption, the sense amp also includes an additional latch to support a “hybrid lockout” sensing mode, where in a verify operation a read-lockout is used between different data states, but not between the low and high quick pass write (QPW) verifies.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: March 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Man Lung Mui, Yosuke Kato, Hao Thai Nguyen, Seungpil Lee
  • Patent number: 8971131
    Abstract: A circuit includes a first plurality of memory cells coupled with a first data line and a first data transfer circuit coupled with the first data line and a second data line. In a first operation mode of the circuit, the first data line is left floating and is caused to have a first logical value by a current in at least one memory cell of the first plurality of memory cells. In a second operation mode of the circuit, the first data line is configured to reflect data stored in a memory cell of the plurality of memory cells, and the second data line is configured to reflect the data on the first data line through the first data transfer circuit.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Bing Wang
  • Patent number: 8937840
    Abstract: A digital voltage boost circuit, optionally working in parallel with an analog voltage regulator, periodically injects a constant amount of current each cycle into the bit line of a high density memory array to eliminate the bias voltage reduction which would otherwise occur. This results in a much faster recovery time and reduces the semiconductor real estate required. A pulse generator in the boost circuit generates one or more current modulation signals which control corresponding current supply devices in a current source. The boost circuit drives a constant amount of current to the bias voltage node each memory cycle.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: James W. Dawson, Noam Jungmann, Elazar Kachir, Udi Nir, Donald W. Plass
  • Patent number: 8917567
    Abstract: A semiconductor device includes a global bit line and a local bit line, and a switch coupled therebetween. Upon performing a precharge operation, a precharge voltage is supplied to the global bit line with turning the switch ON, so that the local bit line receives the precharge voltage through the global bit line and the switch, and after a lapse of a predetermined time, a precharge voltage is further supplied to the local bit line without an intervention of the global bit line and the switch.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: December 23, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Shinichi Takayama, Kazuhiko Kajigaya
  • Patent number: 8908418
    Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Makoto Yabuuchi
  • Patent number: 8867297
    Abstract: A charge/discharge circuit is configured to directly charge a storage system using a power source under a power-on stage and to charge the storage system using power pre-stored in a capacitor under a power-off stage. With the aid of the charge/discharge circuit, an access speed of the storage system is prevented from being slowed down by attaching the large capacitance of the capacitor, and data accuracy of the storage system is prevented from being affected by sudden loss of power supply of the power source.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: October 21, 2014
    Assignee: Transcend Information, Inc.
    Inventor: Chia-Pin Lin
  • Patent number: 8861264
    Abstract: A pre-charge controlling method and device are provided. The pre-charge controlling method includes pre-charging a first global bit line with a first pre-charge voltage by using at least a first pre-charge circuit located between a plurality of sub arrays included in a memory cell array and pre-charging the first global bit line with a second pre-charge voltage by using a second pre-charge circuit located outside the memory cell array.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ick Hyun Song, Ki Whan Song, Jin-Young Kim
  • Patent number: 8804395
    Abstract: Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: August 12, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kyoichi Nagata
  • Patent number: 8797816
    Abstract: A semiconductor memory apparatus comprises bit line sense amplifier unit, and a pair of precharge elements coupled in series between a first bit line and a second bit line and having an asymmetrical contact resistance ratio.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: August 5, 2014
    Assignee: SK Hynix Inc.
    Inventor: Mi Hyeon Jo
  • Patent number: 8792287
    Abstract: A nonvolatile semiconductor memory quickly and precisely accumulates a desired amount of charges corresponding to data-to-be-written in a charge accumulating part of a memory cell. When charges are injected into the charge accumulating part of the memory cell by applying a writing voltage corresponding to the data-to-be-written to the drain or source region of the memory cell, the writing voltage is reduced on the basis of an increase in the amount of charges accumulated in the charge accumulating part.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: July 29, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventors: Katsuaki Matsui, Junya Ogawa
  • Patent number: 8767496
    Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David J. McElroy, Stephen L. Casper
  • Patent number: 8737162
    Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: May 27, 2014
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton
  • Patent number: 8724390
    Abstract: Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: May 13, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Shuo-Nan Hung, Ji-Yu Hung, Shih-Lin Huang, Fu-Tsang Wang
  • Patent number: 8724411
    Abstract: A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Young Kim, Ki Whan Song, Jae Hee Oh, Ji-Hyun Jeong
  • Patent number: 8711635
    Abstract: A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Futatsuyama, Toshiaki Edahiro, Norihiro Fujita, Fumitaka Arai, Tohru Maruyama, Masaki Kondo
  • Patent number: 8711642
    Abstract: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: April 29, 2014
    Assignee: Apple Inc.
    Inventor: Michael J. Cornwell
  • Patent number: 8705305
    Abstract: In at least one embodiment, a sense amplifier circuit includes a pair of bit lines, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the pair of bit lines and includes an NMOS transistor coupled between a power node and a corresponding one of the pair of bit lines. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the corresponding bit line and configured to maintain a voltage level of the corresponding bit line. The noise threshold control circuit is connected to the sense amplifier output and the pair of bit lines. The noise threshold control circuit comprises a half-Schmitt trigger circuit or a Schmitt trigger circuit.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Bharath Upputuri
  • Patent number: 8665659
    Abstract: A data transmission circuit includes an enable signal generation unit configured to receive a first enable signal and generate a second enable signal having a pulse width controlled according to a swing width of data inputted through a first data line, and a sense amplification unit configured to sense and amplify the data inputted through the first data line in response to the second enable signal, and transmit the amplified data to a second data line.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: March 4, 2014
    Assignee: SK Hynix Inc.
    Inventor: Min Chang
  • Patent number: 8638628
    Abstract: Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: January 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Simon J. Lovett
  • Patent number: 8599633
    Abstract: A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors, and is used to precharge bit lines of a bit line pair, wherein the NMOS transistor is controlled by a first control signal, and the two PMOS transistors are controlled by a second control signal. The control signal generator is used to generate the first and second control signals, wherein the first control signal is at a logic high level only when the second control signal is at a first logic low level, the first control signal is at a logic low level when the second control signal is at a second logic low or a first logic high level, and the second logic low level is higher than the first logic low level.
    Type: Grant
    Filed: May 6, 2012
    Date of Patent: December 3, 2013
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Ming-Sheng Tung
  • Patent number: 8565017
    Abstract: The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • Patent number: 8565036
    Abstract: A semiconductor memory device includes a plurality of word lines wired in a first direction, a plurality of bit lines wired in a direction crossing the first direction, a memory cell array including a plurality of DRAM cells provided corresponding to intersections between the word lines and the bit lines, a word line driver which drives the word lines, and a plurality of word line potential stabilization transistors connected to the respective word lines and disposed on an opposite side of the word line driver with the memory cell array sandwiched between the word line potential stabilization transistors and the word line driver, each word line potential stabilization transistor turning on when the word line adjacent to a relevant one of the word lines is selected, thereby connecting the relevant word line to a non-selected potential, and turning off when the relevant word line is selected.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: October 22, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Makoto Kitayama
  • Patent number: 8559256
    Abstract: A non-volatile memory device and a sensing method thereof are disclosed, which can sense multi-level data using resistance variation. The non-volatile memory device includes a cell array and a sensing unit. The cell array includes a plurality of unit cells where data is read out or written. The sensing unit compares a sensing voltage corresponding to data stored in the unit cell with a reference voltage, amplifies/outputs the compared result, measures a difference in discharge time where the sensing voltage is discharged in response to a resistance value of the unit cell during an activation period of a sensing enable signal after a bit line is precharged, and senses the data in response to the measured result.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: October 15, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dong Keun Kim
  • Patent number: 8553480
    Abstract: A memory array includes: at least one differential local bit line pair; at least one differential global bit line pair; at least a column selection signal, for charging the differential local bit line pair to a predetermined voltage; at least an enable signal for coupling the differential local bit line pair to the differential global bit line pair when a voltage of the differential local bit line pair reaches a specific value; and a local sense accelerator, coupled to the differential local bit line pair, for determining a voltage of the differential local bit line pair, and enabling an accelerator signal for latching one of the differential local bit line pair and pulling the other low when the voltage reaches the specific value.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: October 8, 2013
    Assignee: Nanya Technology Corp.
    Inventor: One-Gyun Na
  • Patent number: 8547754
    Abstract: A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify operation. The first load voltage is subsequently recharged by charge sharing from the second load voltage so that the charge pump is not initially necessary for recharging the first load voltage.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: October 1, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chang Wan Ha
  • Patent number: 8509012
    Abstract: A precharge signal generation circuit of a semiconductor memory apparatus may comprise a read/write precharge command generation section configured to delay a precharge command by a first delay time set in response to a control signal to generate one of a read precharge command and a write precharge command; and a read/write bank precharge address generation section configured to delay a bank column address strobe signal by a second delay time set in response to the precharge command delayed in the read/write precharge command generation section, and generate one of a read bank precharge address and a write bank precharge address.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: August 13, 2013
    Assignee: SK Hynix Inc.
    Inventor: Jae Bum Ko
  • Patent number: 8498169
    Abstract: A circuit includes a plurality of capacitors responsive to a plurality of latches that store a test code. A first bit line is coupled to a bit cell and coupled to a sense amplifier. A second bit line is coupled to the bit cell and coupled to the sense amplifier. A differential charge from a set of the plurality of capacitors is applied to the first bit line and to the second bit line. The set of the plurality of capacitors is determined based on the test code and the test code is independent of an output of the sense amplifier.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: July 30, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Hari M. Rao, Esin Terzioglu, Sei Seung Yoon
  • Patent number: 8473809
    Abstract: Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: June 25, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Jun Wan, Alex Mak, Tien-Chien Kuo, Yan Li, Jian Chen
  • Patent number: 8472271
    Abstract: Systems and methods for determining optimal memory device precharge voltages are provided herein. In addition, systems and methods for providing localized sense amplification and circuit assist circuitry are described herein. Embodiments provide for determining precharge multipliers that may be used to determine the optimal precharge voltage based on a precharge source voltage. According to embodiments, the precharge source voltage may be Vdd or Vcs. Optimizing the precharge voltage maximizes memory device performance and functional characteristics, including, but not limited to, stability, efficiency, power, writability, and reliability.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: James W. Dawson, Rajiv V. Joshi, Noam Jungmann, Elazar Kachir, Rouwaida N. Kanj, Ehud Nir, Donald W. Plass
  • Patent number: 8467257
    Abstract: A circuit is usable to generate a sense amplifier enable (SAE) signal for a static random access memory (SRAM) circuit. The circuit includes a first tracking bit line, a second tracking bit line, a tracking cell, and a control logic circuit. The second tracking bit line is electrically connected to the first tracking bit line. The tracking cell has a driving terminal and a non-driving terminal, where the non-driving terminal is connected to the second tracking bit line, and the driving terminal is connected to the first tracking bit line and configured to selectively charge or discharge a voltage on the first tracking bit line in response to a control signal. The control logic circuit is coupled to the first tracking bit line and configured to generate the SAE signal in response to the voltage level on the first tracking bit line.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: June 18, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jack Liu, Yi-Wei Lin
  • Patent number: 8456935
    Abstract: In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: June 4, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bradford L. Hunter, Shayan Zhang
  • Patent number: 8400858
    Abstract: A method for data storage includes providing at least first and second readout configurations for reading storage values from analog memory cells, such that the first readout configuration reads the storage values with a first sense time and the second readout configuration reads the storage values with a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout configurations is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout configuration.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: March 19, 2013
    Assignee: Apple Inc.
    Inventors: Avraham Meir, Naftali Sommer, Eyal Gurgi
  • Patent number: 8400856
    Abstract: A memory device includes a memory array including a plurality of memory cells, sensing circuitry coupled to at least a given bitline associated with a particular column of the memory cells of the memory array, and access time acceleration circuitry coupled to the bitline. The access time acceleration circuitry is configured to control an amount of time required by the sensing circuitry to access data stored in a given one of the memory cells in the particular column of memory cells, by providing in a current access cycle at least a selected one of a plurality of different supplemental charging and discharging paths for the bitline based at least in part on data accessed using the bitline in a previous access cycle.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: March 19, 2013
    Assignee: LSI Corporation
    Inventor: Manish Umedlal Patel
  • Patent number: 8363448
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a power supply circuit, an interconnection and a discharging circuit. The memory cell includes a variable resistance element whose resistance varies by application of a voltage. The power supply circuit outputs the voltage to be applied to the memory cell. The interconnection is formed between the power supply circuit and the memory cell and supplies the voltage output from the power supply circuit to the memory cell. The discharging circuit is connected to the interconnection. The discharging circuit discharges electric charge accumulated in the interconnection after a first operation of applying the voltage to the memory cell is ended and before a second operation of applying the voltage to the memory cell next is started.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: January 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takafumi Shimotori
  • Patent number: 8339882
    Abstract: A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention provides both reference voltage (VSS) precharged sub arrays and VCC precharged sub arrays on the same DRAM memory either with or without the novel charge sharing or charge recycling circuitry between these two different sub arrays as disclosed herein.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: December 25, 2012
    Assignee: ProMOS Technologies Pte. Ltd.
    Inventors: Michael C. Parris, Kim C. Hardee
  • Patent number: 8339885
    Abstract: Various embodiments of a data transfer circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the data transfer circuit may include a first data line, a second data line, a first transfer unit configured to amplify data on the first data line in response to a first control signal and transfer amplified data to the second data line, and a second transfer unit configured to electrically connect the first data line to the second data line in response to a second control signal.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: December 25, 2012
    Assignee: SK Hynix Inc.
    Inventor: Byeong Chan Choi
  • Patent number: 8331160
    Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: December 11, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Prashant S. Damle, Krishna Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda
  • Patent number: 8331180
    Abstract: A static random access memory (SRAM) includes an SRAM cell to store a bit of data. A word line accesses the SRAM cell, which, responsively, during a read, drives either a bit line true (BLT) or a bit line complement (BLC) low. Both BLT and BLC are precharged to a supply voltage, then, subsequently are discharged to a reference voltage, lower than the supply voltage, prior to the word line being activated. Because the bit lines are at a voltage lower than the supply voltage when the SRAM cell is activated, the SRAM cell stability is improved.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: December 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chad Allen Adams, Sharon Huertas Cesky, Elizabeth Lair Gerhard, Jeffrey Milton Scherer
  • Patent number: 8331159
    Abstract: A discharge circuit for a floating gate type MOS memory cell transistor disposed in a memory array region of a nonvolatile semiconductor memory device, the memory cell region being formed in P-well, the P-well being formed in an N-well, and the N-well being formed in a P-type semiconductor substrate, includes a word line discharge circuit providing a word line control voltage and a bulk discharge circuit providing a voltage to the P-well during a discharge operation. Constant current transistors and switching transistors in the word line discharge circuit and the bulk discharge circuit are simultaneously turned ON during at least a portion of the discharge operation.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: December 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yuichiro Nakagaki
  • Patent number: 8325555
    Abstract: A data storage device includes a data storage medium and a controller. The controller is configured to control at least one of a reading, erasing, and writing operation on the data storage medium. The controller includes an interface and a power management unit. The interface is configured to exchange at least one of a command, an address, and data with a host. The power management unit is configured to change the power mode of the interface into a power saving mode if: a command input from the host is not executed, data transfer is not actually executed in executing the command, or status information is not reported after the command is executed.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: December 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Min Jeong, Sang-Kyoo Jeong