Abstract: A content addressable memory system has rows and columns of CAM cells. Each CAM cell has a data memory, and comparison circuitry for comparing the data bit of the memory element with a compare data, and for driving a signal onto a match line when the data bit is not equal to the compare data. The comparison circuitry has a mismatch node with a pre-discharge device, and drives a match line drive device coupled to the match line. The mismatch node also couples to a first comparison device having source an output of the data memory and gate coupled to the compare data, and a second comparison device having source a second output of the data memory and gate coupled to compare data. Disclosed is a ternary implementation of the CAM cell also having a mask bit. Also disclosed is CAM timing such that the CAM cells operate without crowbar current.

Abstract: An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency.. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write is data drivers to provide for maximum write times without crossing current during input/output line equilibration periods.

Abstract: It is an object of the invention to provide a flash memory with a fast reading speed and good read disturb resistance. This flash memory comprises a memory cell block having FAMOS transistors arranged in a matrix form; a plurality of word lines connected to the control gates of transistors in the same row; a plurality of bit lines connected to the drains of transistors in the same column; a source line connected in common to the sources of all transistors; and a driver circuit for charging the source line. The driver circuit charges the source line and not the bit line when reading data. In addition, the driver circuit performs accelerated charging at the start of charging the source line and thereafter performs normal charging.

Abstract: In many DRAM (Dynamic Random Access Memory) architectures, a sense amplifier detects and amplifies a small voltage differential between complementary bitline pairs to read from/write to a DRAM memory cell. The access speed of the DRAM is dependent on the speed of the transition, due to this amplification, of the bitline pairs from an equalized, pre-charged voltage level to final (within a given sensing cycle) high and low levels. The transition speed of the bitline pairs can be increased by providing a higher overdrive voltage to the sense amplifier. As DRAM technologies are scaled successively smaller, the overdrive voltage must be controlled to avoid compromising the reliability of the DRAM. Accordingly, the present invention relates to a DRAM circuit which provides a transiently higher overdrive voltage only during sensing. The overdrive is provided by a pre-charged capacitive source utilizing the circuit's natural capacitance.

Abstract: A limited swing driver with a pass transistor coupled between a memory cell and an associated bitline; an inverter, its output coupled to the gate of the pass transistor, and its input coupled with the memory cell. A memory node is formed at the juncture of the inverter input and the memory cell forming a memory node. The driver also includes a discharge transistor coupled between the memory node and ground. The discharge transistor is driven by an input on the discharge transistor gate. It is preferred that the discharge transistor being programmed to produce a limited swing voltage at the memory node. It is desirable that the limited swing voltage be less than about 350 mV, and it is preferable that the limited swing voltage be between about 300 mV and about 200 mV.

Abstract: A memory device can read data stored in memory cells using a differential voltage sensing technique. The memory includes a differential voltage sensing circuit having two input nodes. The nodes of the sensing circuit are pre-charged prior to reading the memory cell. The nodes are pre-charged by charge sharing multiple bit lines. In one embodiment, local bit lines having a first charge are coupled to global bit lines having a second charge to provide a desired pre-charge level. The local and global bit lines can have equal capacitance values. The voltages of the bit lines prior to charge sharing can be any selected value, but in one embodiment the local bit lines are discharged to ground and the global bit lines are charged to Vcc.

Abstract: A K way cache memory having improved operational speed and reduced power consumption is provided. The cache memory includes M cache memory units, but only activates one of the units at a given time. Moreover, only one match line is activated corresponding to a way having a tag address that matches an externally provided tag address.

Abstract: A semiconductor memory device having input/output sense amplifiers capable of varying gains using a column address and block selection signals. The input/output sense amplifiers can compensate for reduction of transfer rate according to distance between a selected memory block or sub memory block and the sense amplifiers. A semiconductor memory device of the present invention includes: a plurality of sub memory blocks divided by a column address in a memory block; a plurality of data input/output line pairs coupled to the sub memory blocks, for transmitting data in a selected sub memory block; and a plurality of input/output sense amplifiers for sensing and amplifying data from the data input/output line pairs, wherein each of the input/output sense amplifiers has a variable gain characteristic depending on distance between the selected sub memory block and the input/output sense amplifiers so as to minimize a difference in delay characteristic according to position of the selected sub memory block.

Abstract: A semiconductor memory device includes a plurality of bit lines; a plurality of virtual GND lines; and a plurality of memory cell transistors arranged in an array. The plurality of bit lines includes a selected bit line directly connected to a memory cell transistor to be read among the plurality of memory cell transistors and a non-selected bit line. The plurality of virtual GND lines includes a selected virtual GND line directly connected to the memory cell transistor to be read and a non-selected virtual GND line. The non-selected bit lines include a charge non-selected bit line to be charged and a non-selected dummy bit line to be grounded. The non-selected virtual GND lines include a charge non-selected virtual GND line to be charged. The non-selected dummy bit line is connected between the selected virtual GND line and one of the charge non-selected bit line and the charge non-selected virtual GND line.

Abstract: A method for addressing redundant columns in a nonvolatile memory, which receives, at inputs, selection addresses and comprises a plurality of redundant columns, each including a respective bit line and a plurality of memory cells connected to the bit line. The addressing method comprises the steps of: detecting a transition in the selection addresses; starting charging of all the bit lines upon detection of the transition in the addresses; then detecting whether one of the redundant columns is addressed; should one of the redundant columns be found to be addressed, proceeding with charging of the bit line of the redundant column addressed and interrupting charging of the bit lines of the redundant columns not addressed; and should none of the redundant columns be found to be addressed, interrupting charging of all the bit lines.

Abstract: The circuit generally comprises a bit line, a complementary bit line, a memory cell and a read circuit. The memory cell may be configured to (i) discharge the bit line in response to a memory sense period and (ii) charge the complementary bit line in response to said memory sense period. The read circuit may be configured to (i) precharge the bit line prior to the memory sense period, (ii) discharge the complementary bit line prior to the memory sense period, and (iii) detect when the bit line and the complementary bit line achieve a predetermined voltage separation in response to the memory sense period. The circuit may be used in asynchronous memories.

Abstract: A memory device includes first, second, and third discharging units, which are connected to a negative voltage node, for discharging the negative voltage to a ground voltage through three steps which are sequentially conductive. The first discharging unit discharges the negative voltage in response to a first signal and a second signal. It does so when the negative voltage is a first voltage level. The second discharging unit discharges the negative voltage in response to the second signal and a third signal. It does so when the negative voltage is a second voltage level. The third discharging unit discharges the negative voltage in response to a fourth signal and a fifth signal. It does so when the negative voltage is a third voltage level.

Abstract: According to the first embodiment of the present invention, a pre-charge device is connected to the middle of each complementary bit line. Thus, once activated, the pre-charge device only drives a load equal to half of the RC impedance of the entire bit lines during the pre-charging operation. According to the second embodiment of the present invention, a first pre-charge device is connected to one end of each complementary bit lines and a second pre-charge device is connected approximately to the middle of each complementary bit lines. Once both devices are activated, each device drives a load equal to half of the RC impedance of the entire bit lines, thus reducing the pre-charge time of the bit lines.

Abstract: Disclosed herein is a nonvolatile semiconductor memory device which comprises a memory cell array, page buffers and Y-pass gate circuit. Each page buffer according to the present invention contains its latch which has a first current driving capacity during a sensing period of a read operation and a second current driving capacity during a data output period of the read operation. Similar adjustable current drive capacity is provided during a program operation of the memory device. Preferably, such additional current drive capacity is provided via dual parallel pull-up transistors provided within a data latch circuit corresponding with each bit line of the memory device. Provision of the second parallel transistor and associated gating eliminates the need for one of the prior art circuit inverters in the latch, thereby reducing layout space over-all within the page buffer circuit region of the device.

Abstract: A pulse generator circuit provides a capacitor, a constant current source circuit for charging the capacitor at a constant current in response to an input signal, and a differential amplifier circuit for comparing a charge voltage in the capacitor with a predetermined reference voltage Vref, thereby outputting a pulse signal.

Abstract: An input and output line equalizing circuit for connection to a pair of input and output lines of a memory device. The equalizing circuit includes an equalization control circuit providing at an output a precharge signal, and an equalizing unit connected to the input and output lines. The equalizing unit responding to receipt of a precharge signal from the equalization control circuit to maintain the pair of input and output lines at the same voltage level. The equalizing control circuit includes a first transmission gate and a second transmission gate.

Abstract: A CAM array includes non-volatile ternary CAM cells that use access transistors to easily read from and write to the non-volatile transistors. Each ternary CAM cell includes a pair of storage elements that are used to store a data bit value, and an access element that is used during CAM array operation. During a comparison operation, when the applied data value matches the stored value, the storage elements de-couple the match line from a discharging bit line (i.e., a high voltage on the match line remains high). Conversely, when the applied data value does not match the stored value, the storage elements couple the match line to a discharging bit line, thereby discharging the match line.

Abstract: A semiconductor memory device feeds back a signal made by detecting a data sensing when reading a memory chip, precharges a local data bus within a short time, performs a high-speed operation, and enhances a burst characteristic and AC characteristic responsive to the burst characteristic. The semiconductor memory device detects a sensing moment of a data generated from a local data bus in case of a read operation by using a data bus sense-amplifier unit. At this time, the detection signal precharges a local data bus and its related signals until the next data is generated.

Abstract: A dynamic, data-precharged, variable-entry-length content addressable memory circuit architecture. A match at a particular data bit is found employing precharge/conditional discharge domino logic. Two bits stored at each entry location, data bit and valid bit. The valid bit determines whether the corresponding data bit takes part in the match determination. This allows for full flexibility in the matching function including variable-entry-length access. The precharge is data driven. This eliminates clock signal routing to the memory array, reducing crosstalk between clock and data lines and reducing routing congestion. The circuit employs a mix of low threshold voltage and high threshold voltage transistors. The selection of which transistors have low threshold voltage and which have high threshold voltage enables additional speed via low threshold voltage transistors while maintaining low quiescent current via high threshold voltage transistors.

Abstract: A memory integrated circuit (100) includes an array (102) of core cells (202) addressable by a plurality of word lines (120) and a plurality of drain lines (122). Address circuitry selects one or more word lines and one or more drain lines. Sensing circuit (110) senses a data state of one or more selected core cells of the array of core sells. Drain line charging circuitry charges one or more drain lines prior to sensing this data state. The drain line charging circuitry includes a rapid charging circuit (230) for precharging the one or more drain lines to the predetermined voltage during a precharge period, and a final charging circuit (214) for charging the one or more drain lines to a final charge voltage for sensing the data state.

Abstract: A memory device. The memory device includes an array of memory cells that are coupled to a number of word lines and a number of digit lines. The memory device further includes an addressing circuit that is coupled to the array. The addressing circuit selects a memory cell based on a received address signal. An input/output device is coupled to the digit lines of the array. The input/output device includes an input for receiving a control signal. A control circuit is coupled to the input of the input/output device. The control circuit produces a control signal with a first voltage level when reading data from the array and produces a control signal with a second voltage level when writing data to the array. Thus, the control signal causes the input/output device to provide acceptable drive current during a read operation such that the input/output device does not disturb the data on the digit lines.

Abstract: A semiconductor memory device includes a pair of data lines, a precharging and equalizing circuit, a setting circuit and a data write circuit. The precharging and equalizing circuit is provided between the data lines to equally precharge the data lines to a first voltage in response to a precharge and equalize signal. The setting circuit is provided between the data lines to set one of the precharged data lines to a second voltage in response to data signals. The second voltage is lower than the first voltage. Also, a data Is written to a memory cell based on the second voltage of the one precharged data line and the first voltage of the other precharged data line. The data write circuit supplies the data signals to the setting circuit based on the data.

Abstract: An acceleration circuit for fast programming and fast chip erase of a non-volatile memory array (46) comprises an acceleration input (2) coupled to a triggering circuit (4) which is capable of generating fast program and fast chip erase commands. In an embodiment, the triggering circuit (4) comprises a high voltage detector (6), which is coupled to the acceleration input (2), and a logic circuit (8), which is coupled to the high voltage detector (6) and has a plurality of command write inputs (10). In a further embodiment, the acceleration voltage is reduced by a regulator (52) to generate a regulated voltage, which is supplied to the memory cells (72a, 72b, 74a, 74b, . . . ) in fast program and fast chip erase modes.

Abstract: A semiconductor memory, for example of the ROM type, has columns of memory cells with a bitline for each column connected to the cells of the column. The bitlines are connected via multiplexers to the input of a sense amplifier. Before column selection, the bitlines are held uncharged. When a column is selected, its bitline is connected to a charging voltage by a pull up transistor.

Abstract: A method and apparatus are provided for increasing the density and performance of a Content Addressable Memory (CAM). According to one embodiment, the CAM includes a comparison circuit, an enable circuit, and a bias circuit. The comparison circuit compares a stored bit to an input bit and outputs an inverted result of the comparison. The enable circuit receives as inputs the inverted result of the comparison and an enable input and produces an enabled comparison result. The bias circuit receives the enabled comparison result as its only input and discharges a pull-down line based upon the enabled comparison result.

Abstract: Rows of a CAM array are partitioned into a plurality of row segments, with each row segment having a number of CAM cells coupled to a corresponding match line segment. Each CAM cell includes a discharge circuit connected between the cell and ground potential. The discharge circuits connected to CAM cells in a row segment each include a control terminal coupled to receive a control signal indicative of the logical state of the match line segment of the preceding row segment. During compare operations, all match line segments are pre-charged toward a supply voltage. If there is a match in a first row segment, the first match line segment remains charged and, in response thereto, the discharge circuits within a subsequent row segment are turned on to allow the subsequent match line segments to indicate match conditions in the subsequent row segment.

Abstract: Rows of a CAM array are partitioned into a plurality of row segments, with each row segment having a number of CAM cells coupled to a corresponding match line segment. Each CAM cell includes a discharge circuit connected between the cell and ground potential. The discharge circuits connected to CAM cells in a row segment each include a control terminal coupled to receive a control signal indicative of the logical state of the match line segment of the preceding row segment. During compare operations, all match line segments are pre-charged toward a supply voltage. If there is a match in a first row segment, the first match line segment remains charged and, in response thereto, the discharge circuits within a subsequent row segment are turned on to allow the subsequent match line segments to indicate match conditions in the subsequent row segment.

Abstract: The semiconductor memory device has a normal operation mode and a self-refresh mode, and includes a VBB generation circuit generating a first substrate voltage when an internal power supply voltage is larger than a predetermined value and a second substrate voltage of an absolute value smaller than that of the first substrate voltage when VCC is smaller than the predetermined value, a bit line equivalent voltage generation circuit outputting voltage VCC/2 produced by resistive dividing when internal power supply voltage is lower than the predetermined value in self-refresh mode, a 4KE signal generation circuit generating a signal for performing a 4K operation in the self-refresh mode when internal power supply voltage is lower than the predetermined value and a refresh address generation circuit.

Abstract: A data transfer circuit for read data operations in a memory circuit employs a two-stage bit switch. True and compliment bit lines from a memory cell array are coupled to gates of a pair of transistors in a first stage bit switch. The data from the bit lines is thus transferred to a pair of read data nodes without a DC connection, so charge-sharing is avoided. Also, this allows the data to be extracted without a full logic-level swing of the bit lines, so faster operation is provided. The data from the data nodes is transferred to a pair of data lines through a second-stage bit switch activated by a timing input. The differential voltage on the bit lines is enhanced by a sense amplifier, and, also, the use of the first-stage bit switch allows the bit lines to be precharged to only half the logic level, speeding up operation; this sense amplifier is activated before the timing input for the second-stage bit switch.

Abstract: A configuration for crosstalk attenuation in substantially mutually parallel word lines of DRAM circuits, includes a decoder provided at a first end of a word line, and a holding transistor. A pull-down device is provided as a "noise killer" at a second end of the word line, which opposite the first end. The pull-down device pulls down the potential of the word line in a standby and hold mode in the event of an active adjacent word line.

Abstract: A keeper circuit (14) is included in a memory arrangement comprising a column of memory cells (20) connected by a bit line pair (16,18). The keeper circuit (14) comprises two keeper transistors. One keeper transistor (86) is connected to control current from a supply voltage source to one bit line (16) and the other keeper transistor (88) is connected to control current from the supply voltage source to the other bit line (18) of the bit line pair. Current through each keeper transistor (86, 88) is controlled by the charge state of the opposite bit line. A low charge state on one bit line causes the keeper transistor associated with the opposite bit line to conduct and maintain the charge level of the opposite bit line.

Abstract: Disclosed herein is a semiconductor memory device which comprises a decoding block, an OR gate and first and second precharge circuits. The decoding block generates section word line select signals and column select signals in response to a block select signal and row and column pre-decoder signals. And, the OR gate mixes the section word line select signals to generate a precharge signal. This forces the first precharge circuit to be activated or inactivated in synchronization with the section word line select signals. Furthermore, the second precharge circuit is activated or inactivated in synchronization with the column select signals. According to the precharge scheme of the present invention, there is prevented the period of the inactivation (activation) of the top and bottom precharge signals from being overlapped with the period of the activation (inactivation) of the section word line. As a result, the semiconductor memory device has an improved access speed.

Abstract: A method and associated circuitry are disclosed for applying the high column voltage needed to erase and program (write) a flash EEPROM memory. Low voltage CMOS transistors are used for both the read column precharge path and the write/erase data transfer path. This reduces precharge time, increasing the frequency at which the flash memory can be read. This also eliminates the lengthening of precharge time that occurs as the characteristics of high voltage transistors degrade with age. The present invention provides the additional advantage of eliminating the need to use less reliable high voltage transistors in certain off-pitch circuits needed for write and erase functions, thus increasing overall chip reliability.

Abstract: The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through a switching device is also disclosed.

Abstract: A semiconductor memory device has a plurality of memory blocks. The semiconductor memory device pre-charges a memory block when a block address signal applied to the memory block is identical with a previous block address signal previously applied, and activates the memory block when the block address signal is not identical with the previous block address signal. As a result, a pre-charge operation of a previous block and an activation operation of a present block are simultaneously performed so that the operation speed of an entire system becomes high-speed.

Abstract: A page mode flash memory or floating gate memory device, including a page buffer based upon low current bit latches, and additional capabilities for parallel read and parallel program verify operations. The present device includes bit latch circuitry and/or method steps that facilitate such parallel operations and avoid data conflicts. Circuitry for separate read signals can serve to isolate the operations. Additionally, circuitry tied to the data verification signal can also be used. A diode type device can be used to isolate signal conditions that might indicate the cell does not need to be programmed. Bit-by-bit precharging of the bit lines can also be employed in order to save precharging power. Additionally, the large capacitance of the dataline might be used to delay discharging a particular dataline, and thereby allow a latch enabling signal to go high, thus eliminating the need for further isolation circuitry, or the like.

Abstract: A memory device that includes a row decoder, a set of word line, and one or more word line pull-down drivers. The row decoder includes decoding circuitry and a set of word line drivers. The decoding circuitry is configured to receive address information and generate a set of word line control signals. The word line drivers couple to the decoding circuitry and are responsive to the word line control signals. Each word line driver is configured to provide pull-up drive capability, and can further be configured to provide pull-down drive capability. Each word line couples to at least one word line driver. The word line pull-down driver(s) couples to the word lines, with each word line pull-down driver being configured to provide pull-down drive capability. One or more word line pull-down drivers can be distributed (i.e., uniformly) along the length of each word line. The word lines can also be implemented using a hierarchical word line architecture that includes a set of main word lines (i.e.

Abstract: An approach to rapidly pre-charging bit lines (104a and 104b) after a write operation to a memory cell (128) is disclosed. Following a write operation, a Y-select signal (Yj) and its inverse (/Yj) are maintained in an active state for a given period of time, keeping the transistors within a column selecting circuit (102) turned on. Pre-charging circuits (106 and 108) are also turned on. Consequently, the bit lines (104a and 104b) are pre-charged by the bit line pre-charging circuit (106), and by the pre-charging circuit (108) by way of a read bus (124) and the column selecting circuit (102). Furthermore, a write amplifier (112) is also activated, resulting in the bit lines (104a and 104b) being further pre-charged by way of a write bus (126) and the column selecting circuit (102).

Abstract: A semiconductor memory circuit reduces a current consumed by sense amplifiers, prevents erroneous operation, and can operate at high speed. The semiconductor memory circuit has a plurality of memory blocks each comprising a decoder, a plurality of memory cells, a plurality of sense amplifiers for amplifying potential changes in bit lines, a data latch for latching outputs from the sense amplifiers, a plurality of nMOS transistors for discharging the bit lines, an NAND gate for generating a sense amplifier de-energizing signal RD, and a reference voltage generator. In response to a memory block selecting signal CS, the NAND gate generates the sense amplifier de-energizing signal RD, which is applied to energize the nMOS transistors to discharge the bit lines of a memory block which is not selected.

Abstract: A nonvolatile memory semiconductor memory device is disclosed which incorporates fuse-cells in which data for setting a mode and redundancy data are stored. The nonvolatile memory semiconductor memory device incorporates a fuse-cell circuit including fuse-cells, a fuse-cell controlling circuit for reading data stored in the fuse-cell, a voltage boosting circuit for generating a boosted voltage and a voltage converting circuit which uses a reference voltage to convert the boosted voltage into read voltage for use when data is read from the fuse-cell. The reference voltage is generated by using a threshold voltage of a reference cell having the same structure as that of the fuse-cell.

Abstract: A dynamic logic circuit is provided. The dynamic logic circuit includes at least one bitline. At least one repeater circuit is inserted into each bitline. The bitline repeater circuit includes an inverter and at least one transistor. The inverter is activated by the bitline starting to discharge and the activated inverter turns on the bitline repeater circuit transistor which discharges the bitline. The dynamic logic circuit including the bitline repeater circuit provides improved performance and decreased power consumption.

Abstract: A combined precharging and homogenizing circuit for a semiconductor memory configuration made up of a memory cell array having a multiplicity of bit line pairs. The combined precharging and homogenizing circuit containing a first and a second field-effect precharging transistor and a homogenizing transistor connected in series between the two precharging transistors. Gates of the two precharging transistors and of the homogenizing transistor are connected together to form a common gate. Sources of the precharging transistors are connected together to form a common source. A drain of the first precharging transistor and a drain of the homogenizing transistor are connected together to form a common drain and the source of the homogenizing transistor and the drain of the second precharging transistor are connected together to form a common source/drain. In the combined precharging and homogenizing circuit, the invention provides that the common gate is angled and is configured rotated through about 45.degree.

Abstract: When the data read out line is in the non-selective state, the data select line is at the "L" level, and therefore, the NMOS transistor is turned on, and to the data read out line, the capacity of the condenser is added. Therefore, the potential rising of the data read out line because of the influence of the coupling capacity just after the data select line has become at the "H" level, is small. After that, the memory cell data is transmitted to the data read out line, but at this time, the NMOS transistor becomes in the off state, and therefore, the capacity of the data read out line is reduced, so that the read out speed of the data may not be affected. Consequently, the signal interference because of the coupling capacity can be reduced.

Abstract: A semiconductor nonvolatile memory device where the source line is selected and the channel portions of NAND strings adjacent in the row direction are charged up to the programming prohibit potential, the programming prohibit potential charged in the channel portion of the NAND strings is discharged to the bit lines according to the content of data to be programmed, and then the programming voltage is supplied to the selected word line and page programming is carried out together for memory transistors connected to the selected word lines. By this, the memory is suited for operation by a single power supply at a low voltage, enables easy layout of the data latch circuits for every bit line, and in addition performs a data programming operation with a good disturb tolerance.

Abstract: A method and apparatus for reading or strobing antifuse circuits in a memory device is described. A read signal, also called a strobe signal, is generated from a circuit which includes a model antifuse similar to antifuses employed in the antifuse circuits. The read signal is a single pulse having a duration determined by an amount of time needed to charge the model antifuse such that the read signal is long enough to be applied to properly read antifuse circuits in the memory device. A reset pulse may be generated having a duration determined by the amount of time needed to charge the model antifuse, and the reset pulse may be applied to initialize registers in the memory device and to generate the read signal.

Abstract: The invention relates to word line drivers found in embedded dynamic random access memories (DRAM) of application specific integrated circuits (ASICs). The invention is a method of programming the time at which the boosted voltage interval begins, and the period during which the boosted voltage is maintained. The result is the ability to apply the boosted voltage only when needed, thus minimizing the danger to the oxide integrity. The method comprises initiating an active row cycle in response to a leading edge of a row activation signal, initiating a precharge cycle in response to a trailing edge of the row activation signal, the precharge cycle comprising a broad line boost interval initiated by the falling edge of the row activation signal and having a predetermined duration controlled by a programmable delay circuit.

Abstract: A row decoder for controlling a plurality of selectable word-lines has one control line per block of N word-lines, K select lines, at least one disable line and one word-line driver per word-line. Each control line is activatable during a charge period and during an initial portion of a discharge period. Each select line is selectably high during the charge period. The disable line is active during the discharge period. Each driver includes an access transistor and a discharge transistor. The access transistor is located at one end of its word-line and the discharge transistor is connected at the other end. The access transistor is controlled by one control line and is connected between one select line and the word-line. The discharge transistor is controlled by one disable signal and is connected between the word-line and a ground supply.

Abstract: This invention is a method for boosting the voltage level of a wordline in a DRAM having bitlines, sense amplifiers, isolation devices, bitline loads, an X decoder device and a Y select device. In the preferred method, when the wordline level reaches VDD, the decoder is disabled causing the wordline to stay at the VDD level. The sensing amplifier is also caused to be isolated so as to allow the wordline voltage to track the bitline voltage through capacitive coupling across the access MOSFET of the memory cell being read or written to. As a result, the wordline voltage is increased to a supervoltage as the bitline voltage increases. After the supervoltage is reached on the wordline, the sensing amplifier is connected causing feedback from the amplifier to drive the wordline voltage toward the VDD level and the disabled bit toward GND during this time. At the end of the wordline clock signal, the voltage is at GND and each of the bitlines are returned to their neutral mid-voltage level.

Abstract: A memory device includes first, second, and third discharging units, which are connected to a negative voltage node, for discharging the negative voltage to a ground voltage through three steps which are sequentially conductive. The first discharging unit discharges the negative voltage in response to a first signal and a second signal. It does so when the negative voltage is a first voltage level. The second discharging unit discharges the negative voltage in response to the second signal and a third signal. It does so when the negative voltage is a second voltage level. The third discharging unit discharges the negative voltage in response to a fourth signal and a fifth signal. It does so when the negative voltage is a third voltage level.

Abstract: There is provided a method of controlling data transmission lines of a semiconductor memory device which has a first pair of data transmission lines to which a sense amplifier and memory cells are connected, and a second pair of data transmission lines to which a read circuit and a write circuit are connected at an end of the second pair of the data transmission lines, which is connected to the first pair of data transmission lines via a column gate. The method includes a) shortcircuiting the second pair of data transmission lines for a first period when a read operation is carried out, and b) shortcircuiting the second pair of data transmission lines for a second period when a write operation is carried out, the second period being shorter than the first period.