Compensate Signal Patents (Class 365/210.11)
  • Patent number: 11437084
    Abstract: The present disclosure relates to a method of forming a memory structure. The method includes depositing a ferroelectric random access memory (FeRAM) stack over a substrate. The FeRAM stack has a ferroelectric layer and one or more conductive layers over the ferroelectric layer. The FeRAM stack is patterned to define an FeRAM device stack. A sidewall spacer is formed along a first side of the FeRAM device stack, and a select gate is formed along a side of the sidewall spacer that faces away from the FeRAM device stack. A source region is formed within the substrate and along a second side of the FeRAM device stack, and a drain region is formed within the substrate. The drain region is separated from the FeRAM device stack by the select gate.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Wen-Ting Chu, Yong-Shiuan Tsair
  • Patent number: 11120847
    Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit line, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: September 14, 2021
    Inventors: Christopher Kawamura, Tae H. Kim
  • Patent number: 10998018
    Abstract: Provided are apparatus and methods for compensating fabrication process variation of on-chip component(s) in shared memory bank. The method includes tracking a flip voltage level and tracking a discharge leakage current to disconnect a keeper circuit from the local read bit-line. The method includes controlling a read current and the discharge leakage current based on determining at least one of fast transistor and slow transistor associated with the at least one the keeper circuit and a bit-cell.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shubham Ranjan, Parvinder Kumar Rana, Janardhan Achanta, Manish Chandra Joshi
  • Patent number: 10796770
    Abstract: A sensing circuit, a sensing method and a memory device are provided. The sensing method is applied to the memory device having the sensing circuit. The sensing circuit includes a compensation source and a sensing module. The compensation source is capable of providing a compensating current to a first node during a read cycle. The sensing module is coupled to the first node. A cell of the memory device is coupled to the first node. The cell is capable of generating a cell current during the read cycle, and the sensing module determines that the cell is in a first storing state or a second storing state in response to a relationship between the compensating current and the cell current.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Chun-Hsiung Hung
  • Patent number: 9607683
    Abstract: In some embodiments, a semiconductor device includes an SRAM cell, an emulator and a suppressing device. The SRAM cell, enabled by a word line, includes a first inverter formed by a first PMOS transistor and a first NMOS transistor and stores a first data at an output of the first inverter. The emulator is configured to emulate the first inverter operating in a condition that the PMOS transistor is weaker than the first NMOS transistor in driving strength. The suppressing device is configured to, in response to a voltage at an output of the emulator, selectively suppress a voltage level of the word line.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: March 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hidehiro Fujiwara, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 9111626
    Abstract: A memory system includes: a bit counter and a regression analyzer. The bit counter is configured to generate a plurality of count values based on data read from selected memory cells using a plurality of different read voltages, each of the plurality of count values being indicative of a number of memory cells of a memory device having threshold voltages between pairs of the plurality of different read voltages. The regression analyzer is configured to determine read voltage for the selected memory cells based on the plurality of count values using regression analysis.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: August 18, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwanghoon Kim, Junjin Kong, Changkyu Seol, Hong Rak Son
  • Patent number: 8908459
    Abstract: A circuit includes an input/output (IO) circuit, a first node configured to have a first voltage level, a second node configured to have a second voltage level, a third node, and a switching circuit. The IO circuit has a set of transistors, and the third node is coupled to bulks of the set of transistors. The switching circuit is configured to couple the first node to the third node when the IO circuit is operated in an active mode; and couple the second node to the third node when the IO circuit is operated in an inactive mode. The first voltage level causes the set of transistors to have a first threshold voltage, the second voltage level causes the set of transistors to have a second threshold voltage, and an absolute value of the second threshold voltage is greater than that of the first threshold voltage.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Dariusz Kowalczyk
  • Patent number: 8854902
    Abstract: A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics International N.V.
    Inventor: Nishu Kohli
  • Patent number: 8837197
    Abstract: A circuit for generating a write signal includes a pre-emphasis signal generator that receives location information of a to-be-programmed memory cell and generates a pre-emphasis signal depending on the location information of the to-be-programmed memory cell, and a write driver that generates a program signal corresponding to data to be programmed in the to-be-programmed memory cell. A write signal is generated by combining the program signal with the pre-emphasis signal supplied from the pre-emphasis signal generator, and the write signal output to the to-be-programmed memory cell.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hoon Oh, Young-Don Choi, Ick-Hyun Song
  • Publication number: 20140241049
    Abstract: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.
    Type: Application
    Filed: February 25, 2013
    Publication date: August 28, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Daniele Vimercati, Riccardo Muzzetto
  • Patent number: 8817554
    Abstract: Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: August 26, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 8797809
    Abstract: A nonvolatile memory device includes: a driving voltage generation unit configured to generate a driving voltage of a core bias line included in a memory cell current path; a comparison unit configured to compare a voltage level of the core bias line with a predetermined limit level in response to a virtual negative read signal; and a compensation driving unit configured to compensation-drive the core bias line in response to an output signal of the comparison unit.
    Type: Grant
    Filed: December 26, 2011
    Date of Patent: August 5, 2014
    Assignee: SK Hynix Inc.
    Inventor: Sung-Hoon Ahn
  • Patent number: 8787070
    Abstract: Included are reference cells each including a variable resistance element which reversibly changes between a predetermined low resistance state LR and a predetermined high resistance state HR according to an application of an electric signal, a comparator which compares resistance values of the reference cells, a pulse generation circuit which generates an electric signal for setting the reference cells to LR or HR, and a control circuit which controls operations where application of the generated electric signal to one of the reference cells corresponding to a comparison result of the comparator and application of a new electric signal generated by the pulse generation circuit to one of the reference cells corresponding to a new comparison result of the comparator are repeated, and then one of the reference cells corresponding to a final comparison result of the comparator is connected to an output terminal.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: July 22, 2014
    Assignee: Panasonic Corporation
    Inventor: Kazuhiko Shimakawa
  • Patent number: 8780613
    Abstract: A method for reading a memory element within a crossbar array includes switching a column line connected to a target memory element of the crossbar array to connected to an input of a current mirror; applying an error voltage to unselected rows of the crossbar array; applying a sense voltage to a row line connected to the target memory element; and outputting a current with said current mirror.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: July 15, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Frederick Perner
  • Patent number: 8767496
    Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David J. McElroy, Stephen L. Casper
  • Patent number: 8693275
    Abstract: A memory arrangement including a memory block and a controller. The memory block comprises a plurality of memory cells, wherein each memory cell operable to store one of a plurality of different levels of charge. The controller is configured to write (i) a first reference signal threshold into a first memory cell and (ii) a second reference signal threshold into a second memory cell. The first reference signal threshold corresponds to a first level of charge of the plurality of different levels of charge, and the second reference signal threshold corresponds to a second level of charge of the plurality of different levels of charge. Each of the first level of charge and the second level of charge is used to calibrate a read back of any of the one of the plurality of different levels of charge stored among the plurality of memory cells in the memory block.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: April 8, 2014
    Assignee: Marvell International Ltd.
    Inventors: Aditya Ramamoorthy, Gregory Burd, Xueshi Yang
  • Patent number: 8654595
    Abstract: A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-Kyung Kim, Hong-Sun Hwang, Chul-Woo Park, Sang-Beom Kang, Hyung-Rok Oh
  • Patent number: 8654566
    Abstract: The semiconductor device includes a memory cell including a first transistor including a first channel formation region, a first gate electrode, and first source and drain regions; a second transistor including a second channel formation region provided so as to overlap with at least part of either of the first source region or the first drain region, a second source electrode, a second drain electrode electrically connected to the first gate electrode, and a second gate electrode; and an insulating layer provided between the first transistor and the second transistor. In a period during which the second transistor needs in an off state, at least when a positive potential is supplied to the first source region or the first drain region, a negative potential is supplied to the second gate electrode.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: February 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shuhei Nagatsuka, Takanori Matsuzaki, Hiroki Inoue, Kiyoshi Kato
  • Patent number: 8605521
    Abstract: Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: December 10, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 8593898
    Abstract: An electronic device includes a functional unit and a current compensation unit. The functional unit operates based on a power supplied by an external host through power supply lines and generates a control signal based on an amount of power consumption of the functional unit. The current compensation unit compensates a change in a power supply current based on the control signal, where the power supply current is a current flowing through the power supply lines.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: November 26, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Seung-Won Lee, Sung-Hee Cho
  • Patent number: 8570785
    Abstract: A method for reading a memory element within a crossbar array includes switching a column line connected to a target memory element of the crossbar array to connected to an input of a current mirror; applying an error voltage to unselected rows of the crossbar array; applying a sense voltage to a row line connected to the target memory element; and measuring an output current of the current mirror.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: October 29, 2013
    Assignee: Hewlett-Packard Development Company
    Inventor: Frederick Perner
  • Patent number: 8565038
    Abstract: In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: October 22, 2013
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Hieu Van Tran
  • Patent number: 8559250
    Abstract: Provided is a semiconductor memory device including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to each row of the memory cells, a plurality of bit line pairs arranged corresponding to each column of the memory cells, a column selector that selects any of the plurality of bit line pairs based on a column selection signal and connects the selected bit line pair to a data line pair, a precharge circuit that precharges the data line pair, a sense amplifier that amplifies a potential difference of the data line pair, and a control circuit that controls current for driving the sense amplifier based on potentials of the data line pair after a lapse of a specified period from start of amplification of the potential difference of the precharged data line pair by the sense amplifier.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: October 15, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hidetoshi Ikeda, Koichi Takeda
  • Patent number: 8561001
    Abstract: Systems and methods are disclosed for testing dies in a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: October 15, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Sandeep Kumar Goel
  • Patent number: 8559220
    Abstract: The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is formed on or in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: October 15, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 8531903
    Abstract: A memory arrangement including a memory block and a controller. The memory block comprises a plurality of memory cells, wherein each memory cell operable to store one of a plurality of different levels of charge. The controller is configured to write (i) a first reference signal threshold into a first memory cell and (ii) a second reference signal threshold into a second memory cell. The first reference signal threshold corresponds to a first level of charge of the plurality of different levels of charge, and the second reference signal threshold corresponds to a second level of charge of the plurality of different levels of charge. Each of the first level of charge and the second level of charge is used to calibrate a read back of any of the one of the plurality of different levels of charge stored among the plurality of memory cells in the memory block.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: September 10, 2013
    Assignee: Marvell International Ltd.
    Inventors: Aditya Ramamoorthy, Gregory Burd, Xueshi Yang
  • Patent number: 8509019
    Abstract: A voltage generation circuit for providing a read or verification voltage of a nonvolatile memory device includes a first voltage generation unit configured to output a first voltage using a first reference voltage, a bouncing compensation unit configured to change the first voltage using a first control signal, the first voltage, and a voltage of a global source line when a read or verification operation is performed on the nonvolatile memory device, and to output a changed first voltage as a second voltage, a second reference voltage generation unit configured to generate a second reference voltage, and an amplification unit configured to amplify a difference between the second voltage and the second reference voltage according to a set resistance ratio and to output a result of the amplification as a third voltage.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yu Jong Noh
  • Patent number: 8472274
    Abstract: In one implementation, a method for performing memory operations includes receiving, at a memory device, a request to read data from one or more non-volatile memory cells; and retrieving stored temperature information associated with the non-volatile memory cells, wherein the temperature information is associated with a temperature at approximately at a time when the data was written to the non-volatile memory cells. The method can further include reading, by the memory device, the data from the non-volatile memory cells. The method can also include processing the read data based on, at least, the retrieved temperature information; and providing the processed data.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: June 25, 2013
    Assignee: Apple Inc.
    Inventors: Anthony Fai, Nicholas Seroff, Nir Jacob Wakrat
  • Patent number: 8379478
    Abstract: The present invention relates to a system and method for adjusting timing of memory access operations to a memory block. In one embodiment, a controller may be in communication with a memory block. The controller may be adapted to adjust timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block. The delay may correspond to a predecoder delay or a global decoder delay. The clock pulse may be a read clock pulse or a write clock pulse. In one embodiment, the controller may be adapted to adjust timing of a read clock pulse differently from a write clock pulse.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 19, 2013
    Assignee: Broadcom Corporation
    Inventors: Ali Anvar, Gil I. Winograd, Esin Terzioglu
  • Patent number: 8374017
    Abstract: A semiconductor storage device includes: a plurality of memory cell arrays, each having a memory cell arranged therein, the memory cell including a ferroelectric capacitor and a transistor; a dummy capacitor operative to provide a reference potential corresponding to a potential read from the memory cell; a sense amplifier circuit including an amplifier circuit to compare and amplify potentials between a pair of bit lines; a reference potential correction capacitor connected to the pair of bit lines together with the dummy capacitor; and a control circuit configured to output a correction signal based on shift information to correct the reference potential, the shift information being retained in at least one of the plurality of memory cell arrays. The reference potential correction capacitor shifts the reference potential by changing the amount of accumulated electric charges according to the correction signal.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: February 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryousuke Takizawa, Daisaburo Takashima
  • Patent number: 8363501
    Abstract: A memory arrangement including a memory block and a controller. The memory block comprises a plurality of memory cells, wherein each memory cell operable to store one of a plurality of different levels of charge. The controller is configured to write (i) a first reference signal threshold into a first memory cell and (ii) a second reference signal threshold into a second memory cell. The first reference signal threshold corresponds to a first level of charge of the plurality of different levels of charge, and the second reference signal threshold corresponds to a second level of charge of the plurality of different levels of charge. Each of the first level of charge and the second level of charge is used to calibrate a read back of any of the one of the plurality of different levels of charge stored among the plurality of memory cells in the memory block.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: January 29, 2013
    Assignee: Marvell International Ltd.
    Inventors: Aditya Ramamoorthy, Gregory Burd, Xueshi Yang
  • Patent number: 8339852
    Abstract: A non-volatile memory device includes a sensing circuit that is configured to detect a charge of a common source line and a voltage controller that is configured to vary a level of a voltage being inputted to a word line in response to a result of the detection of the sensing circuit.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: December 25, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyu Hee Lim
  • Patent number: 8320211
    Abstract: A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: November 27, 2012
    Assignee: National Tsing Hua University
    Inventors: Meng-Fan Chang, Yu-Fan Lin, Shin-Jang Shen, Yu-Der Chih
  • Patent number: 8289752
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: October 16, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • Patent number: 8274819
    Abstract: An array of SMT MRAM cells has a read reference circuit that provides a reference current that is the sum of a minimum current through a reference SMT MRAM cell programmed with a maximum resistance and a maximum current through an reference SMT MRAM cell programmed with a minimum resistance. The reference current forms an average reference voltage at the reference input of a sense amplifier for reading a data state from selected SMT MRAM cells of the array such that the reference SMT MRAM cells will not be disturbed during a read operation. The read reference circuit compensates for current mismatching in the reference current caused by a second order non matching effect.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: September 25, 2012
    Assignee: MagIC Technologies
    Inventor: Hsu Kai Yang
  • Patent number: 8248856
    Abstract: The read channel of a solid state non-volatile memory may be configured to compensate for shifts in the threshold voltages of memory cells of the memory. A log of write time information and write temperature information from one or more write operations is stored in a data unit header. The read channel configuration, which may include reference voltages used for the read operation, is determined using the write time information and the write temperature information. Memory cells of the data unit are read using the configured read channel. A historical profile spanning multiple write operations may also be developed and used to configure the read channel.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: August 21, 2012
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Kevin Gomez
  • Patent number: 8238176
    Abstract: An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: August 7, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Chang-Ki Kwon
  • Patent number: 8228709
    Abstract: Disclosed is a resistance variable memory device including a memory cell connected with a bit line, a sense amplifier circuit sensing a voltage level on the bit line, and a pseudo-replica providing the sense amplifier circuit with a control signal that compensates for a drop in the sensing capacity of the sense amplifier circuit in relation to process, voltage and temperature (PVT) variations.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Youngdon Choi
  • Patent number: 8223529
    Abstract: A resistive memory device includes a resistive memory cell array, an output circuit and an input circuit. The resistive memory cell array includes a plurality of memory cells that are coupled to bitlines. The output circuit generates a sensing output signal during a write operation by sensing a bitline voltage, and generates output data during a read operation by sensing the bitline voltage. The input circuit controls the bitline voltage based on input data for the write operation, and limits the bitline voltage in response to the sensing output signal during the write operation. The memory cells are protected by effectually limiting bitline voltage.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: July 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jung Kim, Yeong-Taek Lee, Chul-Woo Park, Sang-Beom Kang
  • Patent number: 8159869
    Abstract: A circuit for generating a reference voltage includes at least one reference cell, a reference cell write driver, a reference cell sense amplifier, and a voltage compensation unit. The reference cell is a variable resistance memory cell. The reference cell write driver writes data to the reference cell. The reference cell sense amplifier reads out the data stored in the reference cell on the basis of a predetermined reference voltage. A voltage compensation unit outputs a compensation reference voltage by controlling the reference voltage in accordance with the output value of the sense amplifier.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: April 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hae Chan Park, Se Ho Lee, Soo Gil Kim
  • Patent number: 8154928
    Abstract: Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: April 10, 2012
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Hieu Van Tran
  • Patent number: 8125819
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: February 28, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • Patent number: 8116160
    Abstract: A nonvolatile memory device is operated by programming sample data in the memory device for verification using verify voltage levels derived from an ideal verify voltage Vv associated with a particular temperature range, performing read verify operations on the sample data using the verify voltage Vv associated with the temperature range; and determining a temperature compensation parameter Nc based on results of the read verify operations.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: February 14, 2012
    Assignee: Samsung Eelctronics Co., Ltd.
    Inventor: Sangwon Hwang
  • Patent number: 8064262
    Abstract: A semiconductor device in accordance with one embodiment of the invention can include a first data storage region including a non-volatile main data storage region. Additionally, the semiconductor device can include a second data storage region including a non-volatile reference region wherein an erasing operation and a writing operation are performed on both the first data storage region and the second data storage region. Moreover, the semiconductor device can also include a control unit coupled to the first and second data storage regions which determines a stress condition corresponding to the first data storage region based on a stress information related to the second data storage region.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: November 22, 2011
    Assignee: Spansion LLC
    Inventor: Minoru Yamashita
  • Patent number: 8040725
    Abstract: A flash memory device includes a cell array and a read voltage adjuster. The cell array includes a first field having first memory cells and a second field having second memory cells. The read voltage adjuster determines a read voltage for reading first data from the first memory cells of the first field with reference to second data read from the memory cells of the second field.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Ku Kang
  • Patent number: 8031526
    Abstract: A memory integrated circuit (IC) includes an input that receives data for programming a target cell to a state. The memory IC further includes a programming module that determines a programming value for programming the target cell to the state based on the state and states of C cells that are adjacent to the target cell. The target cell and the C cells each store K bits per cell, where C and K are integers greater than or equal to 1.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: October 4, 2011
    Assignee: Marvell International Ltd.
    Inventors: Zining Wu, Xueshi Yang, Pantas Sutardja
  • Patent number: 8009458
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: August 30, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • Patent number: 8000133
    Abstract: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: August 16, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hideto Hidaka
  • Patent number: 7995413
    Abstract: A memory device is a provided that includes memory cells situated at the intersection of lines and columns, and a dummy path including a first dummy column having two bit lines to which there are connected dummy memory cells, and a circuit adapted to select at least one of the dummy memory cells to discharge one of the dummy bit lines. The dummy path also includes at least one second dummy column adapted to generate a dummy leakage current (representing a leakage current of a column of the memory device selected in read mode), and a circuit adapted to copy the dummy leakage current to the one dummy bit line, so that the discharge of the one dummy bit line also depends on the dummy leakage current.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: August 9, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Franck Genevaux, Alban Forichon
  • Patent number: 7978503
    Abstract: A dummy memory cell for detection of write completion timing is provided as a replica of a memory cell. When assisting a write operation by power supply control and substrate potential control of the memory cell, the timing of ending the write assist operation is determined by a voltage control circuit based on information about the dummy memory cell. For example, the voltage control circuit performs, in a data write operation in the memory cell, the write assist operation of decreasing the voltage of a source power supply allocated to P-channel MOS load transistors using a pull-down transistor. Thereafter, at the time when completion of the data write operation in the dummy memory cell is detected, the voltage control circuit ends the write assist operation and restores the voltage of the source power supply to the original level using a pull-up transistor.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: July 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Tsuyoshi Koike, Hidenari Kanehara