Reference Or Dummy Element Patents (Class 365/210.1)
  • Patent number: 11087813
    Abstract: A control circuit capable of generating a reliable reference potential while suppressing increase in power consumption and cost. A control circuit causes write processing to be performed individually for a first reference element set to a first resistance state in generating a reference potential used for reading data from a memory element, and a second reference element different from the first reference element, the second reference element being set to a second resistance state different from the first resistance state in generating the reference potential.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: August 10, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hiroyuki Tezuka
  • Patent number: 11081168
    Abstract: A non-volatile memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines extended in a row direction, and a plurality of bit lines extended in a column direction. Each of the memory cells is coupled to one of the word lines and one of the bit lines. The memory device further includes a word-line control circuit coupled to and configured to control the word lines, a first bit-line control circuit configured to control the bit lines and sense the memory cells in a digital mode, and a second bit-line control circuit configured to bias the bit lines and sense the memory cells in an analog mode. The first bit-line control circuit is coupled to a first end of each of the bit lines. The second bit-line control circuit is coupled to a second end of each of the bit lines.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: August 3, 2021
    Assignee: Hefei Reliance Memory Limited
    Inventors: Liang Zhao, Zhichao Lu
  • Patent number: 10964720
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog Eun
  • Patent number: 10878866
    Abstract: According to one embodiment, there is provided a semiconductor storage device including a bit cell, a dummy cell, a word line, a dummy word line, a word line driver, a dummy word line driver, a first modulation circuit, and a second modulation circuit. The word line is electrically connected to the bit cell. The dummy word line is electrically connected to the dummy cell. The word line driver is electrically connected to the word line. The dummy word line driver is electrically connected to the dummy word line. The first modulation circuit is electrically connected to the word line driver. The second modulation circuit is electrically connected to the dummy word line driver.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: December 29, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Guseul Baek
  • Patent number: 10714174
    Abstract: A resistive memory device includes: a normal cell array suitable for including a plurality of memory cells and generating a cell current according to a resistance state of a memory cell selected based on an input address; a reference cell array suitable for including a plurality of sub-arrays each including a predetermined number of memory cells, and generating a reference current according to a combination of resistance states of memory cells of a sub-array, the sub-array being selected based on a reference selection signal; a sense amplifier circuit suitable for sensing and amplifying a signal indicative of data of the selected memory cell based on the cell current and the reference current during a read operation; and a reference cell selector suitable for generating the reference selection signal, the sub-array in the reference cell array corresponding to a position of the selected memory cell in the normal cell array.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: July 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Jae-Yeon Lee
  • Patent number: 10699783
    Abstract: Techniques are provided for sensing a signal associated with a memory cell capable of storing one of three or more logic states. To sense the memory cell (e.g., to sense the signal associated with the memory cell), a first sense component may compare the signal with a first reference value. A reference selector may select a second reference value based on the comparison of the signal with the first reference value. A second sense component may compare the signal with the second reference value. The logic state of the memory cell may be determined based on the results of the first comparison and the second comparison.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Micron Technology
    Inventors: George B. Raad, John F. Schreck
  • Patent number: 10665307
    Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
  • Patent number: 10629254
    Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Hun Kwak, Hee-Woong Kang, Jun-Ho Seo, Hee-Won Lee
  • Patent number: 10410980
    Abstract: According to one embodiment, a semiconductor chip is described including a semiconductor chip body and a semiconductor chip circuit on the body and including a first circuit path coupled to a first and a second node and including at least two gate-insulator-semiconductor structures and a second circuit path coupled to the first and the second node and including at least two gate-insulator-semiconductor structures. The first and the second circuit path are connected to set the first and the second node to complementary logic states. In each of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured as field effect transistor. In at least one of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured to connect the circuit path to the semiconductor body.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 10, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kuenemund, Mayk Roehrich
  • Patent number: 10255976
    Abstract: A sensing circuit includes a first sensing terminal, a second sensing terminal, a second grounding terminal, and a second grounding terminal. The first sensing terminal is connected to a source electrode of a transistor of a memory macro through a bit line. The second sensing terminal is electrically connected to a drain electrode of the transistor of the memory marco through a resistive memory device to a source line, and is not continuously connected to the grounding voltage. The first grounding terminal is used as a reference voltage of a voltage of the first sensing terminal. The second grounding terminal is used as a reference voltage of a voltage of the second sensing terminal. The sensing circuit outputs a sensing signal according to a voltage difference between the first sensing terminal and the second sensing terminal.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: April 9, 2019
    Assignee: INSTON INC.
    Inventors: Albert Lee, Hochul Lee, Kang-Lung Wang
  • Patent number: 10249377
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, a sense amplifier, a word line, and a row decoder. A write operation repeats a program loop including a program operation, first and second verify operations. The row decoder applies a first read voltage to the word line in the first and second verify operations. When the write operation is not suspended, the sense amplifier senses a voltage of the bit line for a first sense period in the first verify operation. When the write operation is suspended, the sense amplifier senses the voltage of the bit line for a second sense period shorter than the first sense period in the initial first verify operation after a resumption of the write operation.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: April 2, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hayao Kasai, Osamu Nagao, Mitsuaki Honma, Yoshikazu Harada, Akio Sugahara
  • Patent number: 10199100
    Abstract: A sensing circuit includes a first sensing terminal, a second sensing terminal, a second grounding terminal, and a second grounding terminal. The first sensing terminal is connected to a source electrode of a transistor of a memory macro through a bit line. The second sensing terminal is electrically connected to a drain electrode of the transistor of the memory marco through a resistive memory device to a source line, and is not continuously connected to the grounding voltage. The first grounding terminal is used as a reference voltage of a voltage of the first sensing terminal. The second grounding terminal is used as a reference voltage of a voltage of the second sensing terminal. The sensing circuit outputs a sensing signal according to a voltage difference between the first sensing terminal and the second sensing terminal.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: February 5, 2019
    Assignee: INSTON INC.
    Inventors: Albert Lee, Hochul Lee, Kang-Lung Wang
  • Patent number: 9978431
    Abstract: A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wun-Ki Jung, Min-Ho Kwon, Kwi-Sung Yoo, Won-Ho Choi, Dong-Hun Lee, Seog-Heon Ham
  • Patent number: 9805810
    Abstract: A memory device includes a memory array with memory cells arranged in rows and columns and with word lines and bit lines. A dummy structure includes a dummy row of dummy cells and a dummy word line. A first pre-charging stage biases a word line of the memory array. An output stage includes a plurality of sense amplifiers. Each sense amplifier generates a corresponding output signal representing a datum stored in a corresponding memory cell pre-charged by the first pre-charging stage. A second pre-charging stage biases the dummy word line simultaneously with the word line biased by the first pre-charging stage. The output stage includes an enable stage, which detects a state of complete pre-charging of an intermediate dummy cell.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: October 31, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giovanni Campardo, Salvatore Polizzi
  • Patent number: 9741435
    Abstract: A sense amplifier circuit includes a sampling capacitor coupled to the input of an inverting amplifier. The output of the inverting amplifier is coupled to a transistor that includes a current terminal. The memory read operation includes two phases. During a first phase, a terminal of the capacitor is coupled to a first cell. During a second phase, the terminal of the capacitor is coupled a second cell.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 22, 2017
    Assignee: NXP USA, INC.
    Inventors: Jon Scott Choy, Michael A. Sadd, Michael Garrett Neaves
  • Patent number: 9608041
    Abstract: A semiconductor memory device comprising a bit line extending in a first direction, a vertical gate cell including a gate oxide layer and a gate metal layer that are formed in a pillar shape, a lower electrode and a data storage material layer formed on the vertical gate cell, and an interconnection layer formed on the data storage material layer.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: March 28, 2017
    Assignee: SK Hynix Inc.
    Inventors: Nam Kyun Park, Kang Sik Choi
  • Patent number: 9601200
    Abstract: A ternary content addressable memory (TCAM) structure may activate individual groups of subarrays in the TCAM structure, during a non-search mode, at configurable intervals of time. The activating causes the TCAM structure to select locations and sequences in which subarrays of the TCAM structure are activated or deactivated. When activating, the TCAM structure is configured to perform a dummy search within the particular subarray. The activating reduces a change in current during transition between a search mode and the non-search mode.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: March 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Michael T. Fragano, Thomas M. Maffitt
  • Patent number: 9576621
    Abstract: A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: February 21, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anand Seshadri, Dharin Shah, Parvinder Rana, Wah Kit Loh
  • Patent number: 9548087
    Abstract: Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: January 17, 2017
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Samar Saha
  • Patent number: 9390779
    Abstract: A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 12, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Seong-Ook Jung, Taehui Na, Jisu Kim, Seung H. Kang, Jung Pill Kim
  • Patent number: 9373364
    Abstract: Deterioration of holding characteristics due to fluctuations in power supply voltage VDD is prevented. During writing or reading in one of memory circuits, a pair of bit lines in the other memory circuit is controlled to a dummy-bit-line voltage ranging from a ground voltage to ½×VDD. In a subsequent precharge period, a pair of bit lines in one of the memory circuits and the pair of bit lines in the other memory circuit are coupled to a reference voltage generating circuit.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: June 21, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyuki Takahashi
  • Patent number: 9245589
    Abstract: A nonvolatile semiconductor device which can be driven at low voltage is provided. A nonvolatile semiconductor device with low power consumption is provided. A Schmitt trigger NAND circuit and a Schmitt trigger inverter are included. Data is held in a period when the supply of power supply voltage is continued, and a potential corresponding to the data is stored at a node electrically connected to a capacitor before a period when the supply of power supply voltage is stopped. By utilizing a change in channel resistance of a transistor whose gate is connected to the node, the data is restored in response to the restart of the supply of power supply voltage.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: January 26, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Munehiro Kozuma
  • Patent number: 9208893
    Abstract: Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate transistor in a non-conductive state is measured by periodically clocking a counter following initiation of a read cycle; a latch stores the counter contents upon the cell under test making a transition due to leakage of the floating-gate transistor. Logic for testing a group of cells in parallel is disclosed. In some embodiments, the read margin of a cell in which the floating-gate transistor is set to a conductive state is measured by repeatedly reading the cell, with the output developing a voltage corresponding to the duty cycle of the output of the read circuit.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: December 8, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: David Alexander Grant
  • Patent number: 9196657
    Abstract: An electronic device comprising a semiconductor memory unit that includes a first vertical electrode; a first variable resistance layer surrounding the first vertical electrode; a second vertical electrode surrounding the first variable resistance; a second variable resistance layer surrounding the second vertical electrode; and a plurality of horizontal electrodes contacted with an outer side of the second variable resistance layer, wherein the plurality of horizontal electrodes are spaced apart from each other in a vertical direction.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: November 24, 2015
    Assignee: SK HYNIX INC.
    Inventor: Kwang-Hee Cho
  • Patent number: 9170287
    Abstract: The present invention discloses a 3D-IC differential sensing and charge sharing scheme which includes a plurality of TSVs including a first TSV and a second TSV. A tracking circuit is coupled to the first TSV. A sensing circuit is coupled to the second TSV and the tracking circuit. A plurality of equaling circuits are provided and wherein each of equaling circuit is configured and electrically connected between adjacent two equaling circuits. A clamping circuit is coupled to the first TSV.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: October 27, 2015
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chang Meng-fan, Huang Tsung-hsien
  • Patent number: 9171606
    Abstract: Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are disconnected from the bit lines and the dummy cells are connected to the bit lines, and subsequently the bit lines are equalized by the equalizing circuit. When accessing a selected memory cell, the equalizing circuit is inactivated, a corresponding dummy cell is disconnected from the bit line, and subsequently the selected memory cell is connected to the bit line. Thereafter, the sense amplifier is activated so that potentials of the bit lines are amplified respectively.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: October 27, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 9142292
    Abstract: Provided is a method for reading data from a variable resistance nonvolatile storage element, where the operation for reading data is less susceptible to a fluctuation phenomenon of resistance values in reading the data. The method includes: detecting a current value Iread that flows through the nonvolatile storage element that can be in a low resistance state RL and a high resistance state RH, with application of a fixed voltage; and determining that (i) the nonvolatile storage element is in a high resistance state when the current value Iread detected in the detecting is smaller than a current reference level Iref, and (ii) the nonvolatile storage element is in a low resistance state when the current value Iread detected in the detecting is larger than the reference level Iref, the current reference level Iref being defined by (IRL+IRH)/2<Iref<IRL.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 22, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yoshihiko Kanzawa, Takeshi Takagi
  • Patent number: 9111595
    Abstract: A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao Hsu, Ming-Chien Tsai, Chen-Lin Yang
  • Patent number: 9099191
    Abstract: A sensing method of a current sensing amplifier is provided used for determining a storing state of a cell of a non-volatile memory device during a read cycle. After a sensing node and a reference node are adjusted to a constant voltage, the sensing node and the reference node are maintained in a floating state. Then, the sensing node is connected with a data line to receive a cell current from the cell, and the reference node is connected with a reference current source to receive a reference current from the reference current source. When a reference voltage of the reference node reaches a preset voltage, the storing state of the cell is determined according to a relationship between a sensing voltage of the sensing node and the preset voltage.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: August 4, 2015
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Yu-Hsiung Tsai, Yuan-Tai Lin, Chi-Yi Shao
  • Patent number: 9099201
    Abstract: A memory array includes a memory segment having at least one memory bank. The at least one memory bank includes an array of memory cells, and wherein at least two first read tracking cells are disposed in a read tracking column of the at least one memory bank. The memory array further includes a read tracking circuit coupled to the at least two first read tracking cells. Outputs of the at least two first read tracking cells are connected to a tracking bit connection line (TBCL). A tracking circuit connected to the TBCL is configured to output a tracking-cells output signal to generate a global tracking result signal to a memory control circuitry. The memory control circuitry is configured to reset a memory clock based on the global tracking result signal.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: August 4, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Derek C. Tao, Bing Wang, Kuoyuan (Peter) Hsu, Jacklyn Victoria Chang, Young Suk Kim
  • Patent number: 9047936
    Abstract: A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises at least one dummy memory cell, a feedback-based controller having inputs coupled to respective internal nodes of the dummy memory cell, and write signal generation circuitry coupled to the feedback-based controller and configured to provide one or more write signals for controlling writing of data to portions of the memory array. The feedback-based controller generates a reset signal for application to a reset input of the write signal generation circuitry at least in part as a function of a logic level transition delay of a selected one of the first and second internal nodes of the dummy memory cell.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: June 2, 2015
    Assignee: LSI CORPORATION
    Inventors: Vikash, Kamal Chandwani, Rahul Sahu
  • Patent number: 9042187
    Abstract: Methods, memories and systems may include charging a sense node to a logic high voltage level, and supplying charge to a bit line and to a reference bit line for a precharge period that is based, at least in part, on a time for a voltage of the reference bit line to reach a reference voltage. A memory cell that is coupled to the bit line may be selected after the precharge period, and a clamp voltage may be set based, at least in part, on the voltage of the reference bit line. If a voltage level of the bit line is less than the clamp voltage level during a sense period, charge may be drained from the sense node, and a state of the memory cell may be determined based, at least in part, on a voltage level of the sense node near an end of the sense period.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventor: Chang Wan Ha
  • Patent number: 9042148
    Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: May 26, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
  • Patent number: 9042150
    Abstract: An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: May 26, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Michael Achter, Evrim Binboga, Harry Kuo
  • Patent number: 9030861
    Abstract: An operating method of a variable resistance memory device including a pre-read step which may include the steps of: reading a first reference cell using a first reference voltage; reading a second reference cell using a second reference voltage; and setting a third reference voltage based on the first and second reference voltages; and a main read step of reading a selected memory cell using the third reference voltage.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 12, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sun Hyuck Yon
  • Patent number: 9030863
    Abstract: An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 12, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Chirag Gulati, Rakesh Kumar Sinha, Ritu Chaba, Sei Seung Yoon
  • Patent number: 9025403
    Abstract: A high-voltage word-line driver circuit for a memory device uses cascode devices to prevent any single transistor of the driver circuit from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Gregory J. Fredeman, Abraham Mathews, Donald W. Plass, Kenneth J. Reyer
  • Patent number: 9025402
    Abstract: A semiconductor memory apparatus may include a memory bank, row decoders, and an intersection region circuit. The row decoder may be configured to select a dummy block and a plurality of sub blocks based on row address signals, a bank select signal, and a dummy delayed bank select signal. The intersection region circuit may delay the bank select signal and may generate a delayed bank select signal and a dummy delayed bank select signal.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventor: Doo Chan Lee
  • Patent number: 9019753
    Abstract: A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells. The write tracking control circuit further includes a first delay circuit between the input node and the first transistor, the first delay circuit configured to introduce a first delay time, wherein a gate of the first transistor is connected to the first delay circuit. The write tracking control circuit further includes a second delay circuit between the input node and the second transistor, the second delay circuit configured to introduce a second delay time different from the first delay time, wherein a gate of the second transistor is connected to the second delay circuit.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: April 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bing Wang, Kuoyuan (Peter) Hsu, Derek C. Tao
  • Patent number: 9001573
    Abstract: Methods and apparatus for programming memory cells in a memory array are disclosed. A most recent programming time is determined, the most recent programming time being a time when a most recent programming operation was applied to a reference memory cell in the memory array. A programming signal is then applied to a target memory cell in the memory array, the programming signal having a programming parameter which depends at least in part on the most recent programming time.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: April 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Massimo Ferro
  • Patent number: 9001563
    Abstract: In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Yoshiya Takewaki
  • Patent number: 8995215
    Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Spansion LLC
    Inventors: Akira Ogawa, Masaru Yano
  • Publication number: 20150078110
    Abstract: A read time tracking mechanism (RTTM) for ensuring sufficient read time is provided. The read time tracking mechanism includes a read tracking circuit, which includes a tracking bit line (TBL) tracking circuit with one or more tracking cells, and a tracking word line (TWL). The RTTM also includes a sense amplifier enable (SAE) timing device configured to change the logic threshold of tracking WL (TWL) to delay the timing of signal change of TWL when necessary to ensure sufficient read time. The read time tracking mechanism is used to provide sufficient read time for memory arrays with various configurations, prepared under various process conditions, and operated under various voltages, and temperatures.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hyun-Sung HONG, Atul KATOCH
  • Patent number: 8982651
    Abstract: A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: March 17, 2015
    Assignee: STMicroelectronics International N.V.
    Inventors: Anuj Grover, Gangaikondan Subramani Visweswaran
  • Patent number: 8976614
    Abstract: A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yong Zhang, Derek C. Tao, Dongsik Jeong, Young Suk Kim, Kuoyuan (Peter) Hsu
  • Publication number: 20150063048
    Abstract: A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Lin, Hung-Chang Yu, Yue-Der Chih
  • Patent number: 8964494
    Abstract: A memory with extra digit lines in full size end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group of four digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. A repair method can be performed on memories including the end arrays with folded digit sense amplifiers. A row in a core array including a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Michael S. Lane, Michael A. Shore
  • Patent number: 8958258
    Abstract: A semiconductor device includes a plurality of memory mats, each of which includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells that are arranged at intersections of the word lines and the bit lines, and a plurality of dummy word lines, each of which is sandwiched between two corresponding ones of the word lines; a main dummy word line to which the dummy word lines included in the memory mats are commonly electrically connected; and a dummy-word-line control circuit that detects an electric potential of the main dummy word line when a test signal is activated, and outputs an error signal when the electric potential exceeds a predetermined threshold value. According to the present invention, because an electric potential of each of the dummy word lines is directly detected, an address of the word line, which has a short circuit with the dummy word line, can be reliably detected in a short time.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: February 17, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Sadayuki Okuma
  • Publication number: 20150036444
    Abstract: A sense amplifier comprises a sense amplifying unit configured to be connected to a bitline and a complimentary bitline of a memory device, to sense a voltage change of the bitline in response to first and second control signals, and to control voltages of a sensing bitline and a complimentary sensing bitline based on the sensed voltage change. It further comprises a first isolation switch configured to connect the bitline with the sensing bitline in response to an isolation signal, a second isolation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the isolation signal, a first offset cancellation switch configured to connect the bitline with the sensing bitline in response to an offset cancellation signal, and a second offset cancellation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the offset cancellation signal.
    Type: Application
    Filed: April 29, 2014
    Publication date: February 5, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: YOUNGHUN SEO
  • Publication number: 20150036421
    Abstract: Disclosed is a current sense amplifier suitable for a nonvolatile memory device such as a magnetic random access memory. In the current sense amplifier, a reference memory cell for sensing is implemented by a memory cell equal to a normal memory cell without fabricating different reference memory cells. The current sense amplifier is formed of first and second cross coupled differential amplifiers being covalent bonded. The current sense amplifier compares a current flowing to a sensing node of a memory cell directly with currents flowing to reference sensing nodes.
    Type: Application
    Filed: June 23, 2014
    Publication date: February 5, 2015
    Inventors: Chankyung KIM, Dong-Seok KANG, Yunsang LEE, Soo-Ho CHA