Abstract: An integrated chip has an array of memory cells disposed over a semiconductor substrate and a driver circuit. The driver circuit provides the array with a read voltage that varies in relation to an approximate temperature of the memory array to ameliorate temperature dependencies in read currents. The driver circuit may vary the read voltage in an inverse relationship with temperature. The read voltage may be varied continuous or stepwise and the driver circuit may use a table lookup. Optionally, the driver circuit measures a current and modulates the read voltage until the current is within a target range. The memory cells may be multi-level phase change memory cells that include a plurality phase change element disposed between a bottom electrode and a top electrode. Modulating the read voltage to reduce temperature-dependent current variations is particularly useful for multi-level cells.

Abstract: A semiconductor device includes a magnetic tunnel junction structure on a lower electrode, an intermediate electrode on the magnetic tunnel junction structure, and an upper electrode on the intermediate electrode, wherein the intermediate electrode includes a lower portion and an upper portion having a side surface profile different from that of the lower portion.

Abstract: A magnetic field sensing system includes one or more magnetoresistive random access memory (MRAM) cells, and may be configured to determine one or more of a presence, a magnitude, and a polarity of an external magnetic field incident upon an MRAM cell. In some examples, a control module of the system controls a write current source, or another device, to provide a write current through a write line associated with the MRAM cell to induce a magnetic field proximate to the MRAM cell. The magnetic field may be less than a magnetic switching threshold of the MRAM cell. After initiating the provision of the write current through the write line, the control module may determine a magnetic state of the MRAM cell, and determine a presence of an external magnetic field incident upon the MRAM cell based at least in part on the magnetic state of the MRAM cell.

Abstract: An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.

Abstract: A magnetoresistive memory cell includes an MTJ device and a select transistor. The select transistor includes a first conduction-type semiconductor layer, a gate electrode formed by disposing a gate insulating layer on top of the semiconductor layer, and first and second diffusion regions formed in the semiconductor layer to be spaced apart from each other and to have a second conduction type. A part of the semiconductor layer between the first and second diffusion regions is formed as an electrically floating body region. By using a high-performance select transistor with a floating body effect, high integration of a magnetoresistive memory device may be achieved.

Abstract: Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation.

Abstract: A semiconductor memory device includes a plurality of memory cells configured to correspond to each of a plurality of word lines for storing data; a plurality of reference memory cells configured to include first and second magnetic memory devices, whose lower electrodes are commonly connected to each other, to generate a reference current corresponding to each of the memory cells; and a sense amplification unit configured to sense and amplify the reference current and a data current corresponding to a memory cell connected to an activated word line among the word lines.

Abstract: Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation.

Abstract: According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.

Abstract: A magnetoresistive element includes a free layer a pinned layer; a nonmagnetic layer interposed between the free layer and the pinned layer; and two magnetic layers arranged adjacent to the free layer on an opposite side to the pinned layer. The free layer includes: a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer interposed between the first magnetic layer and the second magnetic layer. Magnetization of the first magnetic layer and magnetization of the second magnetic layer are antiferromagnetically coupled. One of the two magnetic layers is in contact with one end of the free layer in a long-axis direction, and the other of the two magnetic layers is in contact with the other end of the free layer in the long-axis direction.

Abstract: A magnetic memory element (10) for use in a cross-point type memory is provided with a spin valve structure having a free layer (5), a nonmagnetic layer (4), and a pinned layer (3). The magnetic memory element is also provided with another nonmagnetic layer (6) on one surface of the free layer (5), and furthermore, a magnetic change layer (7) whose magnetic characteristics change depending on temperature so as to sandwich the nonmagnetic layer (6) with the free layer (5). In the magnetic change layer (7), the magnetization intensity increases depending on temperature.

Abstract: A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage. A magnetic field is applied through the free magnetic layer the forming a magnetic field modified magnetic tunnel junction data cell, the magnetic field rotates the magnetization orientation of the free magnetic layer without switching a resistance state of the magnetic tunnel junction data cell.

Abstract: A memory device that includes at least one memory cell, the memory cell includes: a magnetic tunnel junction (MTJ); and a transistor, wherein the transistor is operatively coupled to the MTJ; a bit line; a source line; and a word line, wherein the memory cell is operatively coupled between the bit line and the source line, and the word line is operatively coupled to the transistor; a temperature sensor; and control circuitry, wherein the temperature sensor is operatively coupled to the control circuitry and the control circuitry and temperature sensor are configured to control a current across the memory cell.

Abstract: An apparatus and methods for a non-volatile magnetic random access memory (MRAM) device that includes a word line, a bit line, and a magnetic thin film memory element located at an intersection of the word and bit lines. The magnetic thin film memory element includes an alloy of a rare earth element and a transition metal element. The word line is operable to heat the magnetic thin film memory element when a heating current is applied. Heating of the magnetic thin film memory element to a predetermined temperature reduces its coercivity, which allows switching of the magnetic state upon application of a magnetic field. The magnetic state of the thin film element can be determined in accordance with principles of the Hall effect.

Abstract: A semiconductor integrated circuit device includes a plurality of memory cells storing data; a write current line arranged near the memory cells or electrically connected to the memory cells; a first constant current generating circuit providing an output current having a temperature dependence; a second constant current generating circuit providing an output current having a temperature dependence different from that of the output current of the first constant current generating circuit; a mixing circuit mixing the output currents of the constant current generating circuits together to provide a composite current at a variable mixing rate; and a write current electrically connected to the write current line and writing data into the memory cell by passing a write circuit through the write current line based on the composite current provided by the mixing circuit.

Abstract: An array of magnetoresistive memory elements includes a magnetic field sensor for measuring an external magnetic field in the vicinity of the magnetoresistive memory elements. The sensor provides input to enable/disable circuitry that functions to temporarily disable any programming operation when the measured external magnetic field exceeds a threshold value.

Abstract: A magnetic memory element is written to by heating the memory element and applying at least one magnetic field to the memory element.

Abstract: In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.

Abstract: An integrated circuit includes operational circuitry; a sensor configured to sense an environmental parameter; and adjustment circuitry coupled to the sensor and to the operational circuitry and configured to affect the operational circuitry to at least partially counteract the effects of the environmental parameter. A method of testing an integrated circuit includes supporting a sensor in the integrated circuit and using the sensor to sense environmental data.

Abstract: The invention includes a stacked magnetic memory structure. The magnetic memory structure includes a stacked magnetic memory structure. The first layer includes a first plurality of magnetic tunnel junctions. A second layer is formed adjacent to the first layer. The second layer includes a second plurality of magnetic tunnel junctions. The stacked magnetic memory structure further includes a common first group conductor connected to each of the first plurality of magnetic tunnel junctions and the second plurality of magnetic tunnel junctions.

Abstract: The invention relates to a magnetic memory with write inhibit selection and the writing method for same. Each memory element of the invention comprises a magnetic tunnel junction (70) consisting of: a magnetic layer, known as the trapped layer (71), having hard magnetisation; a magnetic layer, known as the free layer (73), the magnetisation of which may be reversed; and an insulating layer (72) which is disposed between the free layer (73) and the trapped layer (71) and which is in contact with both of said layers. The free layer (73) is made from an amorphous or nanocrystalline alloy based on rare earth and a transition metal, the magnetic order of said alloy being of the ferrimagnetic type. The selected operating temperature of the inventive memory is close to the compensation temperature of the alloy.

Abstract: A memory cell array is constructed by two-dimensionally arranging a plurality of memory cells each composed of a magnetoresistive element, in a row and column directions. Write word lines are provided along the row direction of the memory cell array. Write bit lines are provided along the column direction of the memory cell array. To write data, a pulse-like write current is applied to an appropriate word and bit lines to generate magnetic fields in the column and row directions. A combined magnetic field of the magnetic fields in the column and row directions is applied to a memory cell to write data. A control circuit controls the pulse width of the pulse-like write current applied to the word and bit lines so that the pulse width has a predetermined temperature dependence.

Abstract: This invention provides a controlled temperature, thermal-assisted magnetic memory device. In a particular embodiment, there is an array of SVM cells, each characterized by an alterable orientation of magnetization and including a material wherein the coercivity is decreased upon an increase in temperature. In addition, at least one reference SVM (RSVM) cell substantially similar to and in close proximity to the SVM cells of the array is provided. A provided feedback control temperature controller receives a feedback voltage from the reference SVM cell, corresponding to temperature, and adjusts power applied to the RSVM cell and SVM cell. An associated method of use is further provided.

Abstract: An integrated circuit includes operational circuitry; a sensor configured to sense an environmental parameter; and adjustment circuitry coupled to the sensor and to the operational circuitry and configured to affect the operational circuitry to at least partially counteract the effects of the environmental parameter. A method of testing an integrated circuit includes supporting a sensor in the integrated circuit and using the sensor to sense environmental data.

Abstract: A magnetic memory having a calibration system is disclosed. One embodiment of the magnetic memory includes a sense amplifier and a calibration system configured to monitor at least one operating parameter of the magnetic memory and calibrate the sense amplifier if a measured parameter corresponding to the at least one operating parameter is within a range.

Abstract: A method for reading the magnetization orientation of a memory cell includes applying a magnetic field to the memory cell, observing any change in resistance of the memory cell as the magnetic field is applied, and determining the magnetization orientation based upon the observed change in resistance of the memory cell.

Abstract: A method and system for programming a magnetic memory including a plurality of magnetic elements is disclosed. The method and system include sensing a temperature of the magnetic memory and providing an indication of the temperature of the magnetic memory. The method and system also include providing a current that is based on the indication of temperature of the magnetic memory. The current is temperature dependent and can be used in programming at least a portion of the magnetic elements without the addition of a separately generated current. In addition, the method and system include carrying for at least a portion of the plurality of magnetic elements. The temperature is preferably sensed by at least one temperature sensor, while the current is preferably provided by a current source coupled with the temperature sensor(s).

Abstract: A temperature compensated RRAM sensing circuit to improve the RRAM readability against temperature variations is disclosed. The circuit comprises a temperature dependent element to control the response of a temperature compensated circuit to generate a temperature dependent signal to compensate for the temperature variations of the resistance states of the memory resistors. The temperature dependent element can control the sensing signal supplied to the memory resistor so that the resistance states of the memory resistor are compensated against temperature variations. The temperature dependent element can control the reference signal supplied to the comparison circuit so that the output signal provided by the comparison circuit is compensated against temperature variations. The temperature dependent element is preferably made of the same material and process as the memory resistors.

Abstract: Device and method for memory cell isolation. The memory cell includes a resistive component, such as a magnetic random access memory (MRAM) cell, and an isolation component, such as a four-layer diode. The memory cell may be included in a memory array. The method includes rapidly applying a forward bias across the isolation element to activate the isolation element.

Abstract: A reference voltage generating circuit of a non-volatile ferroelectric memory device includes a temperature compensating control circuit that increases and outputs a level of a signal to a reference capacitor node according to an increase in temperature when a reference control signal is at a high level, a plurality of ferroelectric capacitors connected in parallel, each of first electrodes of the plurality of ferroelectric capacitors are commonly connected to a ground voltage terminal and each of second electrodes of the plurality of ferroelectric capacitors are commonly connected to the reference capacitor node, and a plurality of switching blocks controlled by a reference wordline signal, each having drain terminals commonly connected to the reference capacitor node, source terminals connected to a corresponding bitline.

Abstract: Power-saving reading of magnetic memory devices. In one arrangement, a method includes pulsing a voltage on the array, and obtaining a voltage value indicative of a memory state of the target memory cell from the voltage pulse using a sensing circuit that is electrically connected to the target memory cell. In another arrangement, a method includes pulsing an array voltage on a plurality of row and column conductors of the array, connecting a sensing circuit to a conductor that is electrically coupled to the target memory cell, the sensing circuit including a sense element, and determining the voltage drop across the sense element of the sensing circuit during the voltage pulse, the voltage drop being indicative of a memory state of the target memory cell.

Abstract: A magnetic memory device includes first and second ferromagnetic layers. Each ferromagnetic layer has a magnetization that can be oriented in either of two directions. The first ferromagnetic layer has a higher coercivity than the second ferromagnetic layer. The magnetic memory device further includes a structure for forming a closed flux path with the second ferromagnetic layer.

Abstract: This invention provides a probe based magnetic memory storage device. In a particular embodiment, magnetic memory cells are provided in an array. Each cell provides a magnetic data layer and a conductor. At least one movable probe having a tip characterized by a conductor and a soft reference layer is also provided. In addition, an intermediate layer joined to either the movable probe or each memory cell is provided. The movable probe may be placed in contact with a given memory cell, the probe and cell thereby forming a tunnel junction memory cell with the intermediate layer serving as the tunnel junction. The magnetic field provided by the probe conductor may be combined with a field provided by the cell conductor to produce a switching field to alter the orientation of the data layer. The memory cells may include a material wherein the coercivity is decreased upon an increase in temperature. The probe may also include a heat generator.

Abstract: A temperature compensated RRAM sensing circuit to improve the RRAM readability against temperature variations is disclosed. The circuit comprises a temperature dependent element to control the response of a temperature compensated circuit to generate a temperature dependent signal to compensate for the temperature variations of the resistance states of the memory resistors. The temperature dependent element can control the sensing signal supplied to the memory resistor so that the resistance states of the memory resistor are compensated against temperature variations. The temperature dependent element can control the reference signal supplied to the comparison circuit so that the output signal provided by the comparison circuit is compensated against temperature variations. The temperature dependent element is preferably made of the same material and process as the memory resistors.

Abstract: A dummy cell (reference electric potential generating circuit) DC has a paraelectric capacitor DCC1 and a ferro-electric capacitor DCC2. One end of the paraelectric capacitor DCC1 and one end of the ferro-electric capacitor DCC2 are commonly connected to a node N1. A dummy plate electric potential DPL1 is supplied to the other end of the paraelectric capacitor DCC1, and a dummy plate electric potential DPL2 is supplied to the other end of the ferro-electric capacitor DCC2. When data of a memory cell MC is read at a bit line (selective bit line) BL1, a reference electric potential is supplied to a bit line (reference bit line) BL2 from the dummy cell DC.

Abstract: A magnetic memory device which comprises a magnetic memory cell that includes a magnetic material switchable between two resistive states on the application of a magnetic field. The device also comprises a wire that is connected to the magnetic memory cell and has a conductive connecting link and a conductive word or bit line which are electrically connected to each other. The connecting link is disposed between the word or bit line and the magnetic memory cell and has a thermal resistance that is larger than that of the word or bit line so as to provide a barrier for heat conduction from the magnetic memory cell to the word or bit line.

Abstract: A mechanism of making a low standby current caused by power off compatible with a fast return operation from a standby caused by an interrupt is realized. An information processing device has a first area that includes a central processing unit and peripheral circuit modules, a second area having information holding circuits for holding values of registers contained in the peripheral circuit modules, and a first power switch for controlling supply of a current to the first area. When the information processing device operates in a first mode, an operating current is supplied to the first area and the second area. When the information processing device operates in a second mode, the first power switch is controlled so that the supply of the current to the first area can be shut off, and the supply of the current to the second area is continued.

Abstract: A magnetoresistive random access memory (MRAM) cell, comprising a magnetic tunnel junction having frustrated magnetic reservoirs disposed oppositely along two edges of a free magnetic layer of the junction and magnetized in the same direction that is substantially orthogonal to a free magnetic layer.

Abstract: The invention includes an adjustable offset differential amplifier. The adjustable offset differential amplifier includes a first differential transistor receiving a first differential input, and a second differential transistor receiving a second differential input. A differential amplifier output includes an amplitude proportional to a difference between the first differential input and the second differential input. The first differential transistor includes a plurality of sub first differential transistors. Each sub first differential transistor includes an adjustable back gate bias. Control circuitry can be connected to the adjustable back gate bias of each of the sub first differential transistors for reducing offset errors of the differential amplifier output.

Abstract: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.

Abstract: Nonvolatile memory cells are arranged at crossing points of bit-lines and word-lines. A mode signal indicates whether the nonvolatile memory cells are to be used as a RAM or as a ROM. When the nonvolatile memory cells are to be used as RAM, current is allowed to flow through the bit-lines in one specific direction, current is allowed to flow through the word-lines and the direction of the current flowing through the word-lines is adjusted to write data in the nonvolatile memory cells. When the nonvolatile memory cells are to be used as ROM, no current is allowed to flow through the bit-lines or the word-lines so that data can not be written in the nonvolatile memory cells.

Abstract: A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.

Abstract: An MRAM storage device includes temperature dependent current sources that adjust their outputs as temperature varies. Temperature dependent current sources include one or more diodes connected to a transistor. As temperature varies so does the voltage drop across the diodes. In addition, the MRAM data storage device includes at least one digit line, at least one bit line, and at least one MRAM cell disposed proximate to a junction of a digit line and a bit line. Each end of each digit line is connected to temperature dependent current sources and current sinks. One end of each bit line is connected to a temperature dependent current source while the other end of each bit line is connected to a current sink. Two logic signals R and D are used to activate a write operation and determine the direction of the write current in the digit line.

Abstract: To simplify a method for manufacturing a memory device having a multiplicity of MRAM cells in a crossing area of conductor elements, a method for manufacturing a semiconductor circuit system, in particular, a memory device or the like, having a plurality of memory cells includes the step of structuring each of the memory elements simultaneously with the structuring of the first and second conductor elements.

Abstract: A magnetic memory element is written to by heating the memory element and applying at least one magnetic field to the memory element. The memory element is heated via heating lines which can be formed in a single path or plurality of paths. Each path has one end tied to a reference potential, and the other end coupled to a current source via a transistor.

Abstract: A memory device includes a memory array having a substrate, an array of memory cells disposed over the substrate, row conductors coupled to the memory cells, and column conductors coupled to the memory cells. The memory device also includes current sources that generate variable write currents in response to temperature changes in the memory array. The variable write currents are generated to accommodate the change in coercivities of the memory cells as the temperature of the array changes. A current source can include a temperature sensor that provides a continuous, immediate output to the current sensor to ensure accurate adjustment of a write current generated by the current source. There is no need to halt operation of the memory device to calibrate the current source. In addition, the current source provides an accurate adjustment to the write current because the temperature used by the temperature sensor to generate the output may be taken contemporaneously with generation of the write current.

Abstract: A magnetic memory cell having read conductor that is wholly clad with a high magnetic permeability soft magnetic material for a pinned-on-the-fly soft ferromagnetic reference layer is disclosed. The magnetic memory cell includes a ferromagnetic data layer, an intermediate layer formed on the ferromagnetic data layer, and a soft ferromagnetic reference layer formed on the intermediate layer. The soft ferromagnetic reference layer includes a read conductor and a ferromagnetic cladding that completely surrounds the read conductor to form a cladded read conductor. The soft ferromagnetic reference layer has a non-pinned orientation of magnetization. When an externally supplied read current flows through the read conductor, the read conductor generates a magnetic field that does not saturate the ferromagnetic cladding and is substantially contained within the ferromagnetic cladding and is operative to dynamically pin the orientation of magnetization in a desired direction.

Abstract: A magnetic memory of the random access type (MRAM) contains a memory cell array formed of a multiplicity of memory cells. The memory cells are disposed in the form of a matrix at the points of intersection of word lines and sense lines and the logical data contents of which are defined by a magnetic state. The magnetic memory further contains an addressing circuit allocated to the word lines. The address circuit applies a read voltage to the word line of one or more selected memory cells, the data contents of which are to be read out. An evaluation circuit is provided that is allocated to the sense lines and receives and evaluates a sense signal corresponding to the data contents of the selected memory cell or memory cells. The evaluation circuit has a comparator circuit receiving a reference signal supplied by a reference element that is compared with the sense signal of the memory cell or memory cells to be read out.

Abstract: A method of toroid writing and reading of information, consisting in that from toroid-like patterns made from a magnetic material the structures are organized, comprising information and reference patterns, having a closed magnetic flux of the appropriate twisting direction. When writing the alternative information, on changes the twisting direction of the closed magnetic flux in appropriate information patterns by exposing them to the coordinated in the time and magnitude action of mutually intersecting biasing and magnetic reversal alternating magnetic fields, and when reading the information, one acts on the information and the reference patterns by an alternative biasing magnetic field, afterwards detects the output signals and on the character of their responses determines the value of the information unit written into the information pattern.

Abstract: A large bit size core memory which maximizes usable flux includes at least one array of low drive toroidal magnetic memory cores, a sense-inhibit conductor pair passing through the array in a given direction to inductively couple all cores in the array, a plurality of perpendicular drive conductors, each passing through the array perpendicular to the sense-inhibit conductor pair and inductively coupling a portion of the cores in the array, a plurality of parallel drive conductors, each passing through the array parallel to the sense-inhibit conductor pair and inductively coupling a portion of the cores in the array, and driving and switching circuitry coupled to drive selected a core during a read portion of a memory cycle with a current which rapidly increases to approximately provide the coercive force MMF to the core and then increases relatively slowly toward the full drive current.