Abstract: A memory system includes a nonvolatile semiconductor memory, a controller that controls the nonvolatile semiconductor memory, and a temperature sensor that acquires an operating temperature of at least one of the nonvolatile semiconductor memory and the controller. The controller calculates a temperature parameter based on operating temperatures acquired by the temperature sensor over a period of time, and switches between a plurality of operation settings in which electric power consumptions of the memory system vary, based on the temperature parameter.

Abstract: A method is described. The method includes performing the following on a flash memory chip: measuring a temperature of the flash memory chip; and, changing a program step size voltage of the flash memory chip because the temperature of the flash memory chip has changed.

Abstract: A read-disturb-based physical storage read temperature information identification system includes a global read temperature identification subsystem coupled to at least one storage device. Each at least one storage device reads valid data and obsolete data from at least one physical block in that storage device and, based on the reading of the valid data and the obsolete data, generates read disturb information associated with each row provided by the at least one physical block in that storage device. Each at least one storage devices then uses the read disturb information associated with each row provided by the at least one physical block in that storage device to generate a local logical storage element read temperature map for that storage device that it provides to the global read temperature identification subsystem.

Abstract: An electronic device includes: a power supply to supply a first power and a second power; a first solid state drive (SSD) backplane and a second SSD backplane to receive the first power from the power supply, each of the first solid state drive (SSD) backplane and the second SSD backplane including two or more SSDs; and a baseboard to receive the second power from the power supply, to independently power on and power off the first SSD backplane and the second SSD backplane, and to access the SSDs of an SSD backplane that is in a power-on state from among the first SSD backplane and the second SSD backplane. In response to an increase in temperature of an SSD backplane that is in a power-off state, at least one SSD of the SSD backplane that is in the power-off state may be powered on.

Abstract: A request for an estimated temperature of a memory sub-system including multiple components can be received. A set of component temperature values based on temperature measurements at the components can be identified. A subset of the component temperature values can be generated by removing one or more of the component temperature values from the set of component temperature values based on one or more criteria. The estimated temperature value that estimates the temperature of the memory sub-system can be generated using the subset of the component temperature values.

Abstract: A method for generating a crash-consistent backup of a source volume includes designating certain blocks of an operating source volume to be copied to a target volume, copying the designated blocks from the source volume to the target volume; initiating a time-based tracking process and detecting writes to blocks of the source volume. Using the time-based tracking process to maintain a time-ordered list of blocks that are written to during the copying of blocks to the target volume and to determine when the blocks on the target volume are in a sane state that permits a crash-consistent backup. After the designated blocks are copied, using the time-ordered list to continue copying blocks to the target volume. After the time-tracking process determines the blocks on the target volume are crash consistent (i.e., in a sane state), a snapshot can be transferred to a backup volume and time-tagged as a crash-consistent backup.

Abstract: A method for operating non-volatile storage disclosed herein. The method comprises performing an operation on a set of non-volatile storage elements. The operation on the set of non-volatile storage elements includes providing temperature compensation based on an operation temperature of the set of non-volatile storage elements. The providing temperature compensation includes determining if the operation temperature is outside a temperature range where constant compensation is valid and applying the temperature compensation based on the determination.

Abstract: A memory device and method of operation are described. The memory device may include memory cells of a first type that each store a single bit of information and memory cells of a second type that each store multiple bits of information. The memory cells of the first type may be more robust to extreme operating conditions than the second type but may have one or more drawbacks (e.g., lower density). The memory device may identify data to be written, and in response, may identify a temperature of the memory device. If the temperature is within a nominal operating range associated with a low risk of memory errors, the memory device may write the data to the memory cells of the second type. If the temperature is outside the nominal operating range, the memory device may write the data to the memory cells of the first type.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: A storage device including: a peripheral circuit configured to perform a plurality of internal operations corresponding to a plurality of internal operation commands input from the memory controller, a temperature information controller configured to generate a first temperature code corresponding to an internal temperature at a time at which an internal operation corresponding to a first internal operation command among the plurality of internal operation commands is performed and temperature code generation information representing information that the first temperature code has been generated during a set period and a operation controller configured to control the peripheral circuit to perform an internal operation corresponding to a second internal operation command input after the first internal operation command among the plurality of internal operation commands is input, based on the first temperature code and the temperature code generation information, in response to the second internal operation com

Abstract: A nonvolatile memory includes a memory array, a sensor for measuring a temperature, an interface through which a write command is to be received, and a control circuit. The control circuit is configured to write information of the temperature measured by the sensor in a data storing area of the memory array in which user data associated with the write command is not capable of being written into, when writing the user data in the memory array in response to the received write command.

Abstract: A semiconductor device includes a load element, a switching element, and a processor. The load element controls a temperature of the semiconductor device with an electric current supplied to the load element. The switching element switches between supply of an electric current to the load element and a cut-off of the supply. The processor controls the switching element. The processor controls the electric current to be supplied to the load element through the switching element so that the semiconductor device has a series of temperatures represented by a specific temperature profile.

Abstract: Disclosed herein is a memory controller controlling data transfer between a host system and a flash memory. The memory controller is configured to limit a data transfer rate in a second period following a first period to a predetermined rate lower than a maximum rate when the data transfer rate in a first period satisfies a predetermined condition.

Abstract: Systems, methods, and apparatuses for temperature-compensated operation of electronic devices are described. For example, an apparatus for performing voltage compensation on a sense amplifier based on temperature may include a sense amplifier control circuit coupled to the sense amplifier to provide a compensation pulse to the sense amplifier, wherein the sense amplifier operates in a voltage compensation phase during the compensation pulse. The apparatus may determine the compensation pulse responsive to a voltage compensation duration signal that is based on the operating temperature of the apparatus. The voltage compensation occurs when there is no activate command immediately before or immediately after so that compensation duration change do not happen during an activate command from the command decoder.

Abstract: Aspects of a storage device including a memory and controller are provided which allow for erase voltages applied during erase operations to be adaptively changed at elevated temperatures to reduce erase time and prevent erase failures. In response to detecting a lower temperature of the memory, the controller applies a first erase voltage to cells in a block of a die, and in response to detecting a higher temperature of the memory, the controller applies a second erase voltage larger than the first erase voltage to the cells in the block of the die. The controller may apply the different erase voltages depending on whether the temperature of the die falls within respective temperature ranges or meets a respective temperature threshold, which may change for different dies. As a result, successful erase operations at higher temperatures may be achieved.

Abstract: A write voltage generator is connected with a magnetoresistive random access memory. The write voltage generator provides a write voltage during a write operation. A storage state of a selected memory cell in a write path of the magnetoresistive random access memory is changed in response to the write voltage. The write voltage generator includes a temperature compensation circuit and a process corner compensation circuit. The temperature compensation circuit generates a transition voltage according to an ambient temperature. The transition voltage decreases with the increasing ambient temperature. The process corner compensation circuit receives the transition voltage and generates the write voltage.

Abstract: The present invention is directed to a nonvolatile memory device including a plurality of memory slices, each memory slice including one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes a first input node through which a reference current passes; a second input node through which a read current from the memory sectors passes; a sense amplifier configured to compare input voltages and having first and second input terminals; a reference resistor connected to the first input node at one end and the first input terminal at the other end; a variable current source connected to the reference resistor at one end and ground at the other end; and a second current source connected to the second input node at one end and ground at the other end.

Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

Abstract: A highly reliable STT-MRAM structure and an implementation method thereof are provided. The STT-MRAM structure includes: a memory block array, including a plurality of memory blocks; on-chip in-situ temperature sensors, for detecting an instantaneous temperature of each memory block; and a controller, which outputs a reading or writing operation signal based on the instantaneous temperature of each memory block detected by the on-chip in-situ temperature sensors, so as to modulate respective voltages and/or frequencies of reading and writing operations of each memory block. When the instantaneous temperature is too high, the voltages and/or frequencies of the reading and writing operations would be decreased, to the contrary when the instantaneous temperature is too low, the voltages and/or frequencies of the reading and writing operations would be increased, which expands a reliable working temperature range and lengthens a lifetime of the STT-MRAM structure.

Abstract: A semiconductor memory device includes: a temperature sensor configured to sense an internal temperature of the semiconductor memory device and generate a temperature signal; and a temperature code storage unit configured to receive the temperature signal in response to a temperature code write control signal that is generated when an operation corresponding to a specific command is performed, generate an operating temperature code corresponding to the temperature signal, compare the operating temperature code with a previously stored temperature code, store a larger temperature code of the operating temperature code and the previously stored temperature code as a maximum temperature code, and output the maximum temperature code to an external source in response to a temperature code read control signal.

Abstract: A memory system may include a memory device comprising a plurality of memory blocks and a controller suitable for controlling an operation of the memory device. The controller may perform a fake operation on a predetermined memory block not used to store data when a temperature of the memory device is in a low temperature range.

Abstract: A memory controller includes a sensor poller and a proportional integral controller (PIC) coupled to the sensor poller. The sensor poller is to obtain a temperature and a power of a memory module (MM) operated by the controller, and the PIC is to: dynamically set at least one bandwidth limit for the MM, based, at least in part, on a relationship between a temperature of the MM, a power of the MM and a bandwidth of the MM. The dynamically set bandwidth limit defines the power of the MM at which the MM operates for a predetermined temperature limit. A system includes a memory controller and a dual in-line memory module (DIMM) operated by it.

Abstract: A method for performing refresh management in a memory device, the memory device and controller thereof are provided. The method may include: monitoring a temperature of the memory device, wherein the temperature is detected through a temperature sensor; updating a recorded highest temperature and a recorded lowest temperature according to said temperature; checking whether a difference between the recorded highest temperature and the recorded lowest temperature is greater than a predetermined temperature threshold; and when the difference is greater than the predetermined temperature threshold, triggering refresh of the memory device.

Abstract: A mobile data storage device (102) may be housed in a mobile computing device (142) without an active cooling feature. The mobile data storage device (102) can have at least a controller (122) configured to delay command execution in response to a predicted mobile data storage device (102) temperature. The controller (122) can insert a plurality of delays into a command queue to prevent the mobile data storage device (102) from reaching the predicted mobile data storage device (102) temperature.

Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.

Abstract: Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a page of a memory or a codeword of the memory: obtaining at least three read values of the page or codeword; and processing the at least three read values to determine read parameters comprising: (i) a log likelihood ratio, and/or (ii) a center read reference voltage, wherein the determination is based on a signal count of a number of bits falling in particular regions of multiple regions of the memory and wherein the determined read parameters are used for a decoding of the page or codeword following the decoding failure and/or a subsequent read operation following a successful decoding of the page or codeword.

Abstract: A memory device including: a memory cell array including a memory cell, the memory cell configured to store first data based on a first write current; a write driver configured to output the first write current based on a control value; and a current controller including a replica memory cell, the current controller configured to generate the control value based on a state of second data which is stored in the replica memory cell, wherein an intensity of the first write current is adjusted based on the control value.

Abstract: A NAND flash controlling method includes the steps of: configuring a temperature-sensing unit to detect the flash temperatures and a source block to store source data; configuring a main control unit to receive the flash temperatures for calculating a temperature difference, to generate a data-transmitting signal if the current temperature is abnormal and the temperature difference is too large; configuring a control unit to read and transmit the source data; configuring a data-buffering unit to receive and store the source data; configuring an error-correcting unit to receive a source error-correcting code and a source bit-error rate to re-calculate an updated error-correcting code; configuring a flash-buffering unit to receive the updated error-correcting code and the source data; and, configuring the control unit to utilize the updated error-correcting code to write the source data into the destination block from the flash-buffering unit. In addition, a NAND flash controlling system is also provided.

Abstract: An information handling system includes a memory module having a volatile memory, a non-volatile memory, and a save controller configured to execute a save operation that transfers at least all modified information of the volatile memory to the nonvolatile memory. A processor of the information handling system is configured to access the volatile memory of the first memory module. A management controller of the information handling system is configured to, during boot operation of the information handling system send a signal to the first memory module to initiate the save operation of the first memory module, to monitor a first thermal indicator at a location proximate to first memory module during the save operation of the first memory module, and determines a configuration of the information handling system during normal operation based upon whether the thermal indicator exceeds a first threshold.

Abstract: Embodiments of information handling systems (IHSs) and methods are provided herein to dynamically detect and recover from thermally induced memory failures. Some embodiments include receiving an interrupt corresponding to a memory failure, detecting a current temperature of one or more memory components, and performing a series of memory tests on a specific block of memory within the memory components if the current temperature exceeds a maximum operating temperature specified for the memory components. Some embodiments include storing original contents of the specific block of memory within another memory component of the IHS, performing a first memory test on the specific block of memory at the current temperature, subsequently performing a second memory test on the specific block of memory at a temperature significantly lower than the current temperature, and determining that the memory failure is a thermally induced memory failure if the first memory test fails and the second memory test passes.

Abstract: According to one embodiment, a memory system includes a first nonvolatile memory, and a controller. The controller executes, to the first memory, a program operation first and a first read operation next. The program operation is an operation including (i) acquiring a first temperature, (ii) storing the first temperature, and (iii) controlling the access circuit to set a threshold voltage of a memory cell transistor at a value corresponding to first data. The first read operation is an operation for (i) acquiring a second temperature, (ii) computing a difference between the second and the first temperature, (iii) acquiring a first determination voltage, (iv) correcting the first determination voltage according to the difference, and (v) controlling the first memory to acquire second data corresponding to the threshold voltage on the basis of a comparison between the threshold voltage of the memory cell transistor and the corrected first determination voltage.

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory over a wide range of operating temperatures are described. The amount of shifting in the threshold voltages of memory cell transistors over temperature may depend on the location of the memory cell transistors within a NAND string. To compensate for these variations, the threshold voltages of memory cell transistors in the middle of the NAND string or associated with a range of word lines between the ends of the NAND string may be adjusted by increasing the word line voltages biasing memory cell transistors on the drain-side of the selected word line when the read temperature is greater than a first threshold temperature and/or decreasing the word line voltages biasing memory cell transistors on the source-side of the selected word line when the read temperature is less than a second threshold temperature.

Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.

Abstract: A dynamic random access memory (DRAM) and an operation method thereof are provided. The DRAM includes a temperature sensor, a dynamic memory cell array, a control circuit, a plurality of power supply circuits and a power control circuit. The temperature sensor senses an operating temperature of the DRAM. The control circuit is coupled to a dynamic memory cell array, and accesses and manages the dynamic memory cell array. The power supply circuits powers the dynamic memory cell array and the control circuit. The power control circuit controls power outputs of the power supply circuits. When the DRAM enters the self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state according to the operating temperature of the DRAM.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for selective temperature compensation. An apparatus includes a compensation circuit that applies temperature compensation to an operation based on a temperature detected by a temperature sensor. An apparatus includes a command circuit that receives a lock command. An apparatus includes a lock circuit that locks a temperature compensation applied to an operation in response to receiving a lock command such that the temperature compensation is based on a fixed temperature.

Abstract: According to one embodiment, a semiconductor memory device includes a memory string including a first select transistor, a first transistor adjacent to the first select transistor, and a memory cell transistor, a first select gate line, a first interconnect, a word line, a row decoder, a temperature sensor, and a control circuit. In the erase operation, the control circuit selects a first mode for applying a first voltage to the first interconnect when a temperature measured by the temperature sensor is equal to or higher than a first temperature, and selects a second mode for applying a second voltage to the first interconnect when the temperature measured is less than the first temperature.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to associate a first value of a memory access parameter with a first group indicator. The controller is configured to perform an update operation to determine a second value of the memory access parameter based on first data read from the memory and to generate a first updated value of the memory access parameter. The first updated parameter is associated with the first group indicator and is based on the first value and the second value.

Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.

Abstract: The present disclosure provides a pump circuit comprising a temperature-sensing module, an oscillating module and a pumping module. The temperature-sensing module is configured to measure a temperature of a dynamic random access memory (DRAM). The oscillating module is coupled to the temperature-sensing module and is configured to generate a clock signal based on the temperature of the DRAM. The pumping module is coupled to the oscillating module and is configured to generate a pump voltage and a pump current to drive the DRAM, wherein the pump current is generated based on an oscillating frequency of the clock signal. When the temperature of the DRAM changes, the oscillating frequency of the clock signal changes based on the temperature of the DRAM, and the pump current correspondingly changes based on the oscillating frequency of the clock signal.

Abstract: A power monitoring system which is communicatively coupled to power sensors in one or more rack computer systems, where the power sensors generate data indicating electrical power consumption by mass storage devices in the racks, can determine an operating temperature of the mass storage devices based on the power data and adjust one or more components which support computing operations in the racks to manage the operating temperatures. Operating temperature can be determined based on a predetermined relationship between electrical power consumption of one or more mass storage devices and the operating temperature of the mass storage devices. Component adjustment can include adjusting an operating state of one or more components. Such operating state adjustment can include adjusting the cooling induced by a cooling system, adjusting data migration to and from mass storage devices, and adjusting operation activity on mass storage devices.

Abstract: A storage device may include a nonvolatile memory including a plurality of memory blocks and a memory controller configured to determine a comparison between an idle current value of the nonvolatile memory and a reference current value and to adjust, based on the comparison, a start temperature at which the storage device begins operating speed control of the storage device.

Abstract: A memory module may be provided. The memory module may include a thermocouple and a temperature sensor. The thermocouple may be coupled to at least one contact point among a plurality of contact points formed on a region, on which a memory device may be configured to be mounted. The temperature sensor may be coupled to the thermocouple, and may be configured to generate temperature information.

Abstract: A semiconductor memory device includes a first circuit configured to process data received from and transmitted to an external controller, a second circuit configured to execute calibration on the first circuit, and a control circuit configured to control the second circuit to execute the calibration on the first circuit in response to a calibration command received from the external controller. In response to a first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit. In response to a second calibration command that is received after the first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit if a first condition is met and to not execute the calibration on the first circuit if the first condition is not met.

Abstract: A storage system and method for die-based data retention recycling are provided. In one embodiment, a storage system comprises a controller and a plurality of memory dies. Each of the plurality of memory dies comprises its own temperature sensor, wherein at least one of the memory dies is characterized by a relatively lower endurance than at least one other of the memory dies, and wherein the at least one of the memory dies with the relatively lower endurance is positioned farther away from the controller than the at least one other of the memory dies.

Abstract: A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.

Abstract: Embodiments of the present disclosure provide a method and device for automatically executing an operation of a mobile terminal, and a mobile terminal. The method for automatically executing an operation of a mobile terminal includes: acquiring current moving/stationary situation information, an internal temperature and a current environment temperature of the mobile terminal, herein the current moving/stationary situation information of the mobile terminal includes information indicating that the mobile terminal is stationary at current or the mobile terminal is moving at current; determining a current state of the mobile terminal according to the current moving/stationary situation information, the internal temperature and the current environment temperature; and executing a preset operation according to the current state.

Abstract: An integrated circuit device has at least one environment-hardened die and at least one less-environment-hardened die. Environment-hardened circuitry on the environment-hardened die is more resistant to the degradation when exposed to a predetermined environmental condition than the less-environment-hardened circuitry on the environment-hardened die. The dice are combined using a 3D or 2.5D integrated circuit technology. This is very useful for testing circuits at adverse environmental conditions (e.g. high temperature), or for providing circuits to operate at such conditions.

Abstract: A data center includes: a structure provided with an intake port at one side thereof and an exhaust port at the other side thereof; a rack disposed in the structure; an air blower configured to introduce outside air into the structure through the intake port to circulate the outside air from one side to the other side of the rack; a circulation passage configured to make a first space between the one side of the rack and the intake port and a second space between the other side of the rack and the exhaust port communicate with each other; a circulation amount control equipment disposed within the circulation passage; and an air circulation amount control device configured to control the circulation amount control equipment and an operation state of the electronic equipment such that the amount of the air which circulates the circulation passage is adjusted.

Abstract: In a method for operating a NAND flash memory system, a temperature sensing device detects a decrease in temperature of the NAND flash memory system below a first threshold temperature level, and a clock control unit adjusts an operating condition for a memory access operation in response to detecting the decrease in the temperature below the first threshold temperature level.

Abstract: A semiconductor apparatus includes a control block that generates a first control signal, a second control signal, and a heating enable signal in response to an enable signal and a heating control signal, a temperature measurement block that generates a temperature code corresponding to temperature in response to the first and second control signals, a heater that generates heat while the heating enable signal is being enabled, a code latch block that stores the temperature code in response to the first and second control signals, and outputs a first code and a second code, a control code generation circuit that generates a signal by performing an operation on the first and second codes, and generates a control code by comparing the signal with a preset code, and a reference voltage generation circuit configured to change a voltage level of a reference voltage in response to the control code.