Temperature Compensation Patents (Class 365/211)
  • Patent number: 10373669
    Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 6, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yu Nakanishi
  • Patent number: 10325644
    Abstract: The present disclosure provides a pump circuit comprising a temperature-sensing module, an oscillating module and a pumping module. The temperature-sensing module is configured to measure a temperature of a dynamic random access memory (DRAM). The oscillating module is coupled to the temperature-sensing module and is configured to generate a clock signal based on the temperature of the DRAM. The pumping module is coupled to the oscillating module and is configured to generate a pump voltage and a pump current to drive the DRAM, wherein the pump current is generated based on an oscillating frequency of the clock signal. When the temperature of the DRAM changes, the oscillating frequency of the clock signal changes based on the temperature of the DRAM, and the pump current correspondingly changes based on the oscillating frequency of the clock signal.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 18, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ting-Shuo Hsu
  • Patent number: 10216212
    Abstract: A power monitoring system which is communicatively coupled to power sensors in one or more rack computer systems, where the power sensors generate data indicating electrical power consumption by mass storage devices in the racks, can determine an operating temperature of the mass storage devices based on the power data and adjust one or more components which support computing operations in the racks to manage the operating temperatures. Operating temperature can be determined based on a predetermined relationship between electrical power consumption of one or more mass storage devices and the operating temperature of the mass storage devices. Component adjustment can include adjusting an operating state of one or more components. Such operating state adjustment can include adjusting the cooling induced by a cooling system, adjusting data migration to and from mass storage devices, and adjusting operation activity on mass storage devices.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: February 26, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: Felipe Enrique Ortega Gutierrez
  • Patent number: 10175667
    Abstract: A storage device may include a nonvolatile memory including a plurality of memory blocks and a memory controller configured to determine a comparison between an idle current value of the nonvolatile memory and a reference current value and to adjust, based on the comparison, a start temperature at which the storage device begins operating speed control of the storage device.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwangkyu Bang, Heeyoub Kang, HyoJae Bang, Kitaek Lee
  • Patent number: 10163464
    Abstract: A memory module may be provided. The memory module may include a thermocouple and a temperature sensor. The thermocouple may be coupled to at least one contact point among a plurality of contact points formed on a region, on which a memory device may be configured to be mounted. The temperature sensor may be coupled to the thermocouple, and may be configured to generate temperature information.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: December 25, 2018
    Assignee: SK hynix Inc.
    Inventor: Hyun Ju Yoon
  • Patent number: 10121549
    Abstract: A semiconductor memory device includes a first circuit configured to process data received from and transmitted to an external controller, a second circuit configured to execute calibration on the first circuit, and a control circuit configured to control the second circuit to execute the calibration on the first circuit in response to a calibration command received from the external controller. In response to a first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit. In response to a second calibration command that is received after the first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit if a first condition is met and to not execute the calibration on the first circuit if the first condition is not met.
    Type: Grant
    Filed: February 26, 2017
    Date of Patent: November 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kosuke Yanagidaira
  • Patent number: 10115437
    Abstract: A storage system and method for die-based data retention recycling are provided. In one embodiment, a storage system comprises a controller and a plurality of memory dies. Each of the plurality of memory dies comprises its own temperature sensor, wherein at least one of the memory dies is characterized by a relatively lower endurance than at least one other of the memory dies, and wherein the at least one of the memory dies with the relatively lower endurance is positioned farther away from the controller than the at least one other of the memory dies.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: October 30, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jingfeng Yuan, James M. Higgins, Jeff Whaley
  • Patent number: 10090039
    Abstract: A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: October 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suyeon Doo, Taeyoung Oh, Namjong Kim, Chulsung Park
  • Patent number: 10063685
    Abstract: Embodiments of the present disclosure provide a method and device for automatically executing an operation of a mobile terminal, and a mobile terminal. The method for automatically executing an operation of a mobile terminal includes: acquiring current moving/stationary situation information, an internal temperature and a current environment temperature of the mobile terminal, herein the current moving/stationary situation information of the mobile terminal includes information indicating that the mobile terminal is stationary at current or the mobile terminal is moving at current; determining a current state of the mobile terminal according to the current moving/stationary situation information, the internal temperature and the current environment temperature; and executing a preset operation according to the current state.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: August 28, 2018
    Assignee: ZTE Corporation
    Inventor: Dongxiao Zhao
  • Patent number: 10036774
    Abstract: An integrated circuit device has at least one environment-hardened die and at least one less-environment-hardened die. Environment-hardened circuitry on the environment-hardened die is more resistant to the degradation when exposed to a predetermined environmental condition than the less-environment-hardened circuitry on the environment-hardened die. The dice are combined using a 3D or 2.5D integrated circuit technology. This is very useful for testing circuits at adverse environmental conditions (e.g. high temperature), or for providing circuits to operate at such conditions.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 31, 2018
    Assignee: ARM Limited
    Inventors: Gregory Munson Yeric, Vikas Chandra
  • Patent number: 10025327
    Abstract: A data center includes: a structure provided with an intake port at one side thereof and an exhaust port at the other side thereof; a rack disposed in the structure; an air blower configured to introduce outside air into the structure through the intake port to circulate the outside air from one side to the other side of the rack; a circulation passage configured to make a first space between the one side of the rack and the intake port and a second space between the other side of the rack and the exhaust port communicate with each other; a circulation amount control equipment disposed within the circulation passage; and an air circulation amount control device configured to control the circulation amount control equipment and an operation state of the electronic equipment such that the amount of the air which circulates the circulation passage is adjusted.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: July 17, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Endo, Masatoshi Ogawa, Shigeyoshi Umemiya, Shino Tokuyo, Hiroyuki Fukuda
  • Patent number: 10019188
    Abstract: In a method for operating a NAND flash memory system, a temperature sensing device detects a decrease in temperature of the NAND flash memory system below a first threshold temperature level, and a clock control unit adjusts an operating condition for a memory access operation in response to detecting the decrease in the temperature below the first threshold temperature level.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: July 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woonjae Chung, HanShin Shin
  • Patent number: 9915964
    Abstract: A semiconductor apparatus includes a control block that generates a first control signal, a second control signal, and a heating enable signal in response to an enable signal and a heating control signal, a temperature measurement block that generates a temperature code corresponding to temperature in response to the first and second control signals, a heater that generates heat while the heating enable signal is being enabled, a code latch block that stores the temperature code in response to the first and second control signals, and outputs a first code and a second code, a control code generation circuit that generates a signal by performing an operation on the first and second codes, and generates a control code by comparing the signal with a preset code, and a reference voltage generation circuit configured to change a voltage level of a reference voltage in response to the control code.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: March 13, 2018
    Assignee: SK hynix Inc.
    Inventor: Jong Sam Kim
  • Patent number: 9897490
    Abstract: In a first sensing state in which a first current flows in a forward direction with respect to a pn junction of a first semiconductor element and a second current of a different magnitude from the first current flows in a forward direction with respect to a pn junction of a second semiconductor element, a difference between a forward direction voltage of the pn junction of the first semiconductor element and a forward direction voltage of the pn junction of the second semiconductor element is converted into a digital value by a computer and acquired as a first digital value.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: February 20, 2018
    Assignee: SOCIONEXT INC.
    Inventors: Takashi Miyazaki, Hiroyuki Hamano
  • Patent number: 9880781
    Abstract: A storage device is provided which includes a nonvolatile memory and a temperature sensor. The temperature sensor is configured to detect a temperature of the storage device. The temperature sensor is configured to output temperature information. The storage device includes a memory controller. The memory controller is configured to access the nonvolatile memory in response to a request of an external host device. The memory controller is configured to obtain the temperature information from the temperature sensor according to a first period in a first mode. The temperature sensor is configured to obtain the temperature information from the temperature sensor according to a second period in a second mode. The second period is shorter than the first period.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: January 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yonggeun Oh, Dae-Ho Kim, Chul-Woo Lee, Gyucheol Han
  • Patent number: 9858980
    Abstract: On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch from a currently-applied refresh rate to a different refresh rate. In response to the condition, the refresh rate is dynamically switched. The switching does not require a change of a mode register. Thus, a refresh rate for the memory device can be dynamically changed on the fly.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventor: Kuljit S. Bains
  • Patent number: 9851771
    Abstract: Dynamic monitoring of current draw by a memory device or memory subsystem can enable a power management system to adjust a memory access performance parameter based on monitored power usage. The system can generate a power usage characterization for the memory device and/or memory subsystem based on monitoring current draw for a known pattern, and then subsequently use the power usage characterization to determine how to adjust the memory access performance parameter.
    Type: Grant
    Filed: December 28, 2013
    Date of Patent: December 26, 2017
    Assignee: Intel Corporation
    Inventors: Lawrence A Cooper, Justin J Song, Xiuting C Man, Nagi Aboulenein, Christopher E Cox, Rebecca Z Loop
  • Patent number: 9842662
    Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: December 12, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Carl Z. Zhou, John A. Rodriguez, Richard A. Bailey
  • Patent number: 9837146
    Abstract: Systems, methods and/or devices are used to adjust a read property for a memory portion of non-volatile memory. In one aspect, in response to receiving a program request, the device: detects a first temperature of the memory portion; and stores first temperature data corresponding to the detected first temperature. In response to receiving a read request, the device performs an adjustment determination, including: detecting a second temperature of the memory portion of the non-volatile memory, retrieving the stored first temperature data, and determining, in accordance with the detected second temperature and the retrieved first temperature data, whether to perform the read using an adjusted read property. In accordance with a determination to perform the read using the adjusted read property, the device performs a read on the memory portion using the adjusted read property.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: December 5, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Nian Niles Yang, Chris Nga Yee Yip
  • Patent number: 9778868
    Abstract: A data recorder for permanently storing pre-event data may include a read-write memory with a plurality of bit cells in the read-write memory. Each bit cell may have a bit state of a high value or a low value. A fusible structure in the data recorder may include a morphable element associated with each bit cell. A temperature-triggered module may thermally couple to the ambient environment and may electrically couple to each morphable element. The temperature-triggered module may be further configured to determine if a parameter of the ambient environment exceeds a predetermined threshold, and if so may then transmit a burn signal to the fusible structure so that each morphable element permanently secures the bit state for each bit cell.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: October 3, 2017
    Assignee: GE AVIATION SYSTEMS LLC
    Inventors: Bryan Adam Theriault, Brian Jacob Loyal
  • Patent number: 9767883
    Abstract: A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suyeon Doo, Taeyoung Oh, Namjong Kim, Chulsung Park
  • Patent number: 9760311
    Abstract: A storage system and method for adaptive thermal throttling are disclosed. In one embodiment, a method for adaptive thermal throttling is provided that is performed in a storage system having a memory. This method comprises determining if a temperature of the storage system is above a threshold temperature; and in response to determining that the temperature of the storage system is above the threshold temperature: reducing performance of the storage system in an iterative manner until the temperature of the storage system is within a temperature envelope around the threshold temperature; and storing, in the memory, a value indicating what the performance of the storage system was reduced to in order to get the temperature within the temperature envelope. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: September 12, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Nir Amir, Gadi Vishne, Joshua Lehmann, Judah Hahn
  • Patent number: 9720625
    Abstract: A storage system and method for adaptive thermal throttling are disclosed. In one embodiment, a method for adaptive thermal throttling is provided that is performed in a storage system having a memory. This method comprises determining if a temperature of the storage system is above a threshold temperature; and in response to determining that the temperature of the storage system is above the threshold temperature: reducing performance of the storage system in an iterative manner until the temperature of the storage system is within a temperature envelope around the threshold temperature; and storing, in the memory, a value indicating what the performance of the storage system was reduced to in order to get the temperature within the temperature envelope. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: August 1, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Nir Amir, Gadi Vishne, Joshua Lehmann, Judah Hahn
  • Patent number: 9704558
    Abstract: Provided is a method of refreshing a memory device by controlling a self-refresh cycle according to temperature. In the method, first self-refresh and second self-refresh are performed according to inner temperature of the memory device and a self-refresh cycle is controlled such that an all-bank-refresh (ABR) operation is not performed simultaneously with the start of the second self-refresh. The ABR operation is performed at the start of third self-refresh when the sum of a section of the first self-refresh in which the ABR operation is not performed and a section of the second self-refresh in which the ABR operation is not performed corresponds to a self-refresh cycle.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: July 11, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su-yeon Doo, Tae-young Oh, Cheol Kim, Geun-tae Park
  • Patent number: 9672893
    Abstract: A semiconductor device includes a decoded signal generation circuit suitable for executing a counting operation to generate a decoded signal in response to an oscillation signal during a refresh section, a refresh pulse generation circuit suitable for generating a refresh pulse for executing a refresh operation in response to the decoded signal and a temperature code, and a reset pulse generation circuit suitable for generating a reset pulse initializing the decoded signal in response to the refresh pulse.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: June 6, 2017
    Assignee: SK hynix Inc.
    Inventors: Chul Moon Jung, Mi Hyun Hwang, Man Keun Kang, Sang Kwon Lee
  • Patent number: 9653145
    Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs first to (M+1)th command/address signals (wherein, “M” denotes a natural number which is equal to or greater than two) and receives a detection signal to detect a normality/abnormality of a temperature sensor. The second semiconductor device enters a test mode in response to the (M+1)th command/address signal and compare first to Nth sensing codes (wherein, “N” denotes a natural number which is equal to or greater than two) generated by the temperature sensor with the first to Mth command/address signals to generate the detection signal. The second semiconductor device also executes a refresh operation in response to a refresh signal including a plurality of pulses whose cycle time is controlled by the first to Mth command/address signals.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: May 16, 2017
    Assignee: SK hynix Inc.
    Inventors: Hong Ki Moon, Jeong Tae Hwang
  • Patent number: 9633711
    Abstract: Methods of managing data of a storage device responsive to temperature can include measuring a temperature of the storage device, changing a duration of a refresh interval of the buffer memory responsive to the measured temperatures, changing a number of refresh bursts during the refresh interval responsive to the measured temperature, and refreshing data of the buffer memory based on the refresh interval and the number of the refresh bursts that are changed responsive to temperature.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: April 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung-bum Cho
  • Patent number: 9627018
    Abstract: A semiconductor device may be provided. The semiconductor device may include a stop signal generation circuit configured to compare an operation offset signal with an operation temperature code signal to generate a stop signal. The semiconductor device may include a temperature signal output circuit configured to generate an output temperature signal from a sensed temperature signal in synchronization with an operation clock signal which is generated based on the stop signal. The semiconductor4 device may include a temperature code processing circuit configured to receive a temperature difference code signal corresponding to the output temperature signal to generate the operation temperature code signal in synchronization with the operation clock signal.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 18, 2017
    Assignee: SK HYNIX INC.
    Inventor: Sang Hoon Lee
  • Patent number: 9620192
    Abstract: A semiconductor apparatus with a plurality of slices electrically coupled through through electrodes. Any one slice of the plurality of slices may be configured to generate a refresh cycle signal in response to a refresh command, and transmit the refresh cycle signal to the other slices through the through electrodes. The other slices may be configured to perform refresh operations in synchronization with the refresh cycle signal.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: April 11, 2017
    Assignee: SK Hynix Inc.
    Inventor: Chang Hyun Kim
  • Patent number: 9583206
    Abstract: A method includes, responsive to a power-up event at a data storage device that includes a memory, reading a flag stored at the data storage device and determining that the flag has a first value indicating that a reflow operation has not previously been detected at the memory. The method also includes, in response to determining that the flag has the first value, performing reflow detection at the memory. The method further includes, in response to the reflow detection indicating that the reflow operation has occurred, setting the flag to a second value.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: February 28, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ting Luo, Jianmin Huang, Changyuan Chen, Guirong Liang
  • Patent number: 9553572
    Abstract: A self clocking comparator for clocking a charge pump providing a high voltage output including multiple gain stages and a reset circuit. The gain stages are configured to assert the compare voltage at a first voltage level in a default state when the sense voltage is greater than the reference voltage, and to assert the compare voltage to a second voltage level in a reset state when the sense voltage falls below the reference voltage. The reset circuit resets, or otherwise forces, the gain stages back to the default state in response to the compare voltage transitioning to the second voltage level. The compare voltage oscillates while the sense voltage is less than the reference voltage at a frequency based on a magnitude of a difference between the sense voltage and the reference voltage up to a predetermined maximum frequency level.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: January 24, 2017
    Assignee: SILICON LABORATORIES INC.
    Inventor: Matthew R. Powell
  • Patent number: 9552877
    Abstract: A nonvolatile memory device is writable to a high resistance state and a low resistance state. The nonvolatile memory device may be heated to at least a threshold temperature, based on application of an alternating current (AC) signal, and may be written based on application of a voltage bias.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: January 24, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Robert J. Brooks
  • Patent number: 9502081
    Abstract: An internal voltage generation circuit may include a temperature information generation unit configured to generate a temperature code having a code value corresponding to a temperature. The temperature information generation unit may include a process variation information generation unit configured to generate a process code having a code value corresponding to a process variation. The temperature information generation unit may include a code combination unit configured to generate a combination code in response to a ratio control signal, the temperature code, and the process code. The temperature information generation unit may include an internal voltage generation unit configured to generate an internal voltage having a voltage level corresponding to a code value of the combination code.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: November 22, 2016
    Assignee: SK HYNIX INC.
    Inventors: Ho Uk Song, A Ram Rim
  • Patent number: 9396765
    Abstract: A stacked semiconductor package includes a package substrate, an interposer mounted on the package substrate, a plurality of semiconductor chips stacked on the interposer, and a control unit provided in the interposer, that stores in advance data to be written in the plurality of semiconductor chips, and that outputs the data stored in advance according a test mode signal.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: July 19, 2016
    Assignee: SK hynix Inc.
    Inventors: Min Su Park, Young Jun Ku
  • Patent number: 9390784
    Abstract: A semiconductor memory device includes: a memory unit including a first memory sub region including a first memory cell and a second memory sub region including a second memory cell; a temperature information obtaining unit that obtains temperature information; a temperature estimation unit that estimates a first temperature of the first memory sub region and a second temperature of the second memory sub region based on the temperature information; a first sub region control unit that controls the first memory sub region based on the first temperature; and a second sub region control unit that controls the second memory sub region based on the second temperature.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: July 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-hee Cho, Satoru Yamada, Sang-ho Shin, Sung-sam Lee
  • Patent number: 9384840
    Abstract: Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of a selected memory cell, page information for selected memory cell, or the location of a selected word line.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: July 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon Hee Choi, Ki Tae Park, Bo Geun Kim
  • Patent number: 9344358
    Abstract: For aging-aware routing, an aging module calculates an aging score for links and routers in a Network-on-Chip for a previous epoch. A routing module dynamically routes a flow through the links and the routers to satisfy routing criteria including a least total aging score for the links and the routers of the flow.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: May 17, 2016
    Assignee: Utah State University
    Inventors: Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy
  • Patent number: 9324435
    Abstract: A data transmitting method for a memory storage apparatus is provided. The method includes: initially setting a first threshold and a first accumulated value; and updating the first threshold by using the first threshold plus the first accumulated value at intervals of a first predetermined time. The method also includes when a detected temperature of the memory storage apparatus is greater than or equal to a temperature threshold, determining whether a size of received writing data is greater than or equal to the first threshold; and if no, writing the writing data into a rewritable non-volatile memory module and then updating the first threshold by using the first threshold minus the size of the writing data; and if yes, not writing the writing data into the rewritable non-volatile memory module. Accordingly, the method can effectively prevent overheat of system during operations of the memory storage apparatus.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: April 26, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chien-Hua Chu
  • Patent number: 9324444
    Abstract: A data storage device includes a nonvolatile memory device; and a controller electrically coupled with the nonvolatile memory device, and configured to control an operation of the nonvolatile memory device, wherein the controller is configured to change a frequency of an internal clock and a level of an internal voltage, according to whether data is being transmitted through a channel.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: April 26, 2016
    Assignee: SK hynix Inc.
    Inventor: Seung Jin Park
  • Patent number: 9236121
    Abstract: A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: January 12, 2016
    Assignee: SK Hynix Inc.
    Inventors: Seung Yun Lee, Hae Chan Park, Myoung Sub Kim, Se Ho Lee
  • Patent number: 9230616
    Abstract: Memory devices, memory device operational methods, and memory device implementation methods are described. According to one arrangement, a memory device includes memory circuitry configured to store data in a plurality of different data states, temperature sensor circuitry configured to sense a temperature of the memory device and to generate an initial temperature output which is indicative of the temperature of the memory device, and conversion circuitry coupled with the temperature sensor circuitry and configured to convert the initial temperature output into a converted temperature output which is indicative of the temperature of the memory device at a selected one of a plurality of possible different temperature resolutions, and wherein the converted temperature output is utilized by the memory circuitry to implement at least one operation with respect to storage of the data.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: January 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Yogesh Luthra, Makoto Kitagawa
  • Patent number: 9214215
    Abstract: Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: December 15, 2015
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Brian S. Doyle, Kaan Oguz, Satyarth Suri, Robert S. Chau, Charles S. Kuo, Mark L. Doczy, David L. Kencke
  • Patent number: 9121772
    Abstract: A temperature data coding unit 100 increases the data resolution in a high temperature range and reduces the data resolution in a low temperature range, and makes the data length of the temperature data a fixed length. When carrying out numerical estimation of the fixed length code value in terms of a 2's complement numerical code value, the temperature data coding unit 100 generates coded data that increases with an increase of the pre-coded temperature data in terms of the 2's complement numerical code value.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: September 1, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Teruaki Tanaka
  • Patent number: 9076539
    Abstract: A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: July 7, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-Kyung Kim, Dong-Min Kim, Hong-Sun Hwang
  • Patent number: 9047983
    Abstract: Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.
    Type: Grant
    Filed: April 19, 2014
    Date of Patent: June 2, 2015
    Assignee: SANDISK 3D LLC
    Inventors: Roy E. Scheuerlein, George Samachisa
  • Patent number: 9043539
    Abstract: A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: May 26, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Nakaba Kaiwa, Yutaka Ikeda, Hiroki Fujisawa, Tetsuaki Okahiro
  • Patent number: 9042175
    Abstract: Disclosed is a nonvolatile memory device which includes a memory cell connected to a bit line and a word line; a page buffer electrically connected to the bit line and sensing data stored in the memory cell; and a control logic controlling the page buffer to vary a develop time of the bit line or a sensing node connected to the bit line according to a current temperature during a read operation.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaesung Sim, Bongyong Lee
  • Patent number: 9036396
    Abstract: Circuitry and method for detecting occurrence of a reflow process to an embedded storage device are disclosed. A temperature sensing device includes a resistor, a temperature sensor, and a comparator. The first terminal of the resistor is coupled to a voltage source, and the second terminal of the resistor is coupled to both the first terminal of the temperature sensor and the first input of the comparator. The second terminal of the temperature sensor is grounded and the second input of the comparator is coupled to a reference voltage. The resistance state of the temperature sensor changes from a first resistance state to a second resistance state when the temperature surrounding the temperature sensor reaches a threshold. The comparator generates an output based on the resistance changes of the temperature sensor. The generated output may indicate whether a reflow process has occurred to the embedded storage device.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: May 19, 2015
    Assignee: SanDisk Technologies, Inc.
    Inventors: Tal Heller, Sukhminder Singh Lobana, Yacov Duzly
  • Patent number: 9036438
    Abstract: Data is programmed into and read from a set of target memory cells. When reading the data, temperature compensation is provided. The temperature compensation is based on temperature information and the state of one or more neighbor memory cells. In one embodiment, when data is read from set of target memory cells, the system senses the current temperature and determines the differences in temperature between the current temperature and the temperature at the time the data was programmed. If the difference in temperature is greater than a threshold, then the process of reading the data includes providing temperature compensation based on temperature information and neighbor state information. In one alternative, the decision to provide the temperature compensation can be triggered by conditions other than a temperature differential.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: May 19, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Gerrit Jan Hemink, Shinji Sato
  • Patent number: 9030905
    Abstract: A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: In-Chul Jeong