Abstract: A semiconductor memory device includes a first bank including a plurality of cell matrices a second bank including a plurality of cell matrices and a shared-fuse set, which is shared by the first and second banks, configured to output a defect indication signal when the first bank or the second bank is enabled and a defective cell matrix is included in the enabled bank.

Abstract: A semiconductor device includes a sensing unit configured to sense whether a value of a programming sensing node is within a predefined range, a fuse connected to the programming sensing node, a programming voltage supplying unit configured to supply a programming voltage to the programming sensing node, and a transferring unit configured to transfer the value of the programming sensing node in response to the sensing result of the sensing unit.

Abstract: Disclosed are a circuit and a method for controlling redundancy in a semiconductor memory apparatus. The circuit includes a peripheral circuit redundancy control block and a memory bank redundancy control block. The peripheral circuit redundancy control block buffers and latches an external command to generate an internal command. The peripheral circuit redundancy control block also buffers and latches an external address to generate a global address by comparing the external address with a predetermined output signal of a fuse circuit. The memory bank redundancy control block receives the global address corresponding to the internal command to selectively activate a redundancy word line or a main word line, such that the fuse circuit is provided in the peripheral circuit redundancy control block.

Abstract: According to an aspect of the present invention, there is provided a ferroelectric memory device including: a cell unit including: a first select transistor having a first source, a first drain, and a first gate, one of the first source and the first drain being connected to a bit line; and a memory cell unit having a plurality of first memory cells, each of the first memory cells including a first ferroelectric capacitor and a first memory transistor; and a ferroelectric memory fuse including: a second select transistor having a second source, a second drain, and a second gate connected to a second select line, one of the second source and the second drain being connected to one end of the bit line; and a memory fuse unit having a plurality of second memory cells, each of the second memory cells including a second ferroelectric capacitor and a second memory transistor.

Abstract: An e-fuse sense circuit employs a single ended sense scheme in which the reference voltage is compensated for leakage. A reference voltage generator includes a pull-up resistor of similar value to the selected bitline pull-up resistor. As the sensing trip point is adjusted by selection of a bitline pull-up resistor, a pair of pull-up and pull-down resistors are adjusted together to adjust the impedance of the reference voltage generator. A leakage-path simulation structure including a parallel connection of bitcells is added to the reference voltage generator. The leakage-path simulation structure imitates the bitcells on a bitline in the array of e-fuses. Leakage current on the bitline offsets the bitline voltage by a certain error voltage. The reference voltage is also offset by a fraction of the error voltage to balance the shifts in the ‘1’ and ‘0’ margin levels in the presence of leakage.

Abstract: A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.

Abstract: An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus, even when the defective addresses respectively different are written in a plurality of chips, a writing process to the latch circuit can be completed in a very short period of time. Thereby, an actual process for writing to the anti-fuse element can be performed in parallel for the chips, and as a result, the process for writing to the anti-fuse element can be performed at high speed.

Abstract: A semiconductor memory device includes: an input pad set configured to receive an external input signal and a reference voltage; an input buffer set configured to detect and transmit the input signal to an internal circuit of the semiconductor memory device by comparing the input signal with the reference voltage; and a reference voltage generation circuit configured to generate the reference voltage to supply the reference voltage to the input pad set and the input buffer set during a test operation, the reference voltage generation circuit being deactivated after the semiconductor memory device is packaged.

Abstract: Disclosed are a fuse box and a semiconductor integrated circuit having the same. The semiconductor integrated circuit includes a plurality of banks, column control blocks, and column fuse blocks. The plurality of banks including a plurality of mat rows and mat columns. The banks are arranged in row and column directions and disposed away from each other. The column control blocks are disposed in a space between the banks which are extended to the column direction. The column fuse blocks are disposed adjacent to the column control blocks and have a plurality of fuse boxes. The fuse boxes include fuse sets arranged in two rows. The fuse boxes are disposed to correspond to the one mat column. Each fuse box has an interconnection fuse and address fuses which are arranged with a constant interval and are the same type.

Abstract: A semiconductor device which may be used as an ID chip and data may be rewritten only one time. In addition, a semiconductor device may be used as an ID chip and data may be written except when manufacturing the chip. The invention has a modulating circuit, a demodulating circuit, a logic circuit, a memory circuit, and an antenna circuit over an insulating substrate. The modulating circuit and the demodulating circuit are electrically connected to an antenna circuit, the demodulating circuit is connected to the logic circuit, the memory circuit stores an output signal of the logic circuit, and the memory circuit is a fuse memory circuit using a fuse element.

Abstract: Devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory are included. A memory device can include a table with an output that is used to create a multiplication factor for a current to compensate for temperature changes in the memory device, where the output depends on an operating temperature of the memory device and a difference in the current between a highest specified operating temperature and a lowest specified operating temperature of the memory device.

Abstract: A memory array having both mask programmable and one-time programmable memory cells connected to the wordlines and the bitlines. All memory cells of the memory array are configured as one-time programmable memory cells. Any number of these one-time programmable memory cells are convertible into mask programmable memory cells through mask programming, such as diffusion mask programming or contact/via mask programming. Manufacturing of such a hybrid memory array is simplified because both types of memory cells are constructed of the same materials, therefore only one common set of manufacturing process steps is required. Inadvertent user programming of the mask programmable memory cells is inhibited by a programming lock circuit.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: The present invention relates to a method and circuit for verifying the state of a gated fuse element used with a one-time programmable CMOS memory device. A first expected state is set and a state of a first gate-ox fuse is sensed. The state of the first gate-ox fuse is compared to the first expected state to determine if they are equal, and a first signal is generated. A second expected state is set and a state of a second gate-ox fuse is sensed. The state of the second gate-ox fuse is compared to the second expected state to determine if they are equal, and a second signal is generated. A valid output is generated if both the first and second signals are in a correct state, both signals are high for example.

Abstract: An embodiment of the present invention is a technique to program a fuse. A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.

Abstract: A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.

Abstract: An integrated circuit has an E-fuse sense circuit configured to produce a READ voltage according to a fuse resistance of an E-fuse during a READ operation. The integrated circuit also has a reference sense circuit configured to produce a reference voltage according to a reference resistance of an on-chip reference resistor during the READ operation. The reference sense circuit replicates the E-fuse sense circuit. The E-fuse sense circuit and the reference sense circuit are coupled to a comparator that produces a bit value according to a difference between the READ voltage and the reference voltage.

Abstract: A semiconductor memory device includes a reference voltage generator for generating a plurality of reference voltages each having different voltage levels in response to a self refresh enable control signal, and a voltage comparator for generating a result signal that controls a self refresh operation cycle by comparing each of the plurality of reference voltages with a temperature information voltage that represents an internal temperature of an integrated circuit.

Abstract: In a method for reading a programmable anti-fuse block of a high-voltage integrated circuit a first voltage is applied to a first pin of the HVIC, the first voltage being lowered to a second voltage at a first node. Current is shunted from the first node, thereby lowering the second voltage to a third voltage. An isolation circuit block is then activated to couple the third voltage to a common node of the programmable anti-fuse block, the common node being coupled to a plurality of anti-fuses, each anti-fuse having a programmed state. A read signal is generated that causes a voltage potential representative of the programmed state of each anti-fuse to be latched into a corresponding latch element.

Abstract: A fuse circuit includes a fuse unit configured to form a current path on a first node according to whether or not a fuse is cut; a driving current controller configured to control a potential level of the first node in response to a test signal; and an output unit configured to output a fuse state signal in response to the potential level of the first node.

Abstract: A fuse monitoring circuit for a semiconductor memory device includes a fuse repair unit including a plurality of fuses each programmed with at least one repair address, configured to receive a fuse reset signal and to output a plurality of fuse state signals each corresponding to a connection state of one of the fuses, a fuse monitoring unit configured to receive a monitoring enable signal and to output a plurality of fuse state monitoring signals each corresponding to a corresponding one of the fuse state signals, each of the fuse state signals corresponding to one of a plurality of addresses, and an output unit configured to receive an output control signal and to output the fuse state monitoring signals to an output pad.

Abstract: A nonvolatile semiconductor memory according to an aspect of the invention includes a memory cell array and a power supply circuit. The memory cell array includes memory cells each having an insulating film and being programmed to store information by inflicting an electric stress on the insulating film to break the insulating film. The power supply circuit supplies to the memory cell a program voltage for the electric stress depending on a negative temperature coefficient the electric stress.

Abstract: The present invention provides a nonvolatile memory device that uses a resistance material. The nonvolatile memory device includes: a stacked memory cell array having a plurality of memory cell layers stacked in a vertical direction, the stacked memory cell array having at least one memory cell group and at least one redundancy memory cell group; and a repair control circuit coupled to the stacked memory cell array, the repair control circuit configured to repair a defective one of the at least one memory cell group with a selected one of the at least one redundancy memory cell group. The features that enable repair improve the fabrication yield of the nonvolatile memory device.

Abstract: An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group0, Group1. One of the memory banks is provided with redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells are also provided and these may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines which are selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.

Abstract: A method of storing data in an array of circuit elements, said method comprising injecting a current into selected circuit elements, said current causing a persistent change in a resistance of said selected circuit elements from a first resistance to a second higher resistance indicative of a binary data bit, wherein said current does not break an electrical circuit in which said circuit element is disposed.

Abstract: A semiconductor memory device includes a first anti-fuse element and a second anti-fuse element, respectively composed of a transistor, wherein the first anti-fuse element and the second anti-fuse element are configured so as to be concomitantly programmable, respectively formed in P-wells on a substrate, and the adjacent P-wells are isolated by N-wells of an opposite conductivity type, formed therebetween.

Abstract: A word line block select circuit includes a dummy repair logic unit including a dummy logic circuit to output a first control signal and having a delay path for a repair address decision, and a word line activation unit for activating a word line in response to the first control signal and an active command signal.

Abstract: An antifuse circuit includes a terminal, an antifuse, and a select transistor. The antifuse is coupled to the terminal and has an associated program voltage. The select transistor is coupled to the antifuse and has a gate terminal coupled to receive a first select signal. The select transistor operates in a snapback mode of operation in response to an assertion of the first select signal and the program voltage at the terminal.

Abstract: In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.

Abstract: A semiconductor device used as an ID chip is provided, of which operation is terminated when its role is finished or expires. According to the invention, an antenna circuit, a voltage detecting circuit, a current amplifier circuit, a signal processing circuit, and a fuse are provided over an insulating substrate. When large power is applied to the antenna circuit, a voltage is detected by voltage detecting circuit and a corresponding current is amplified by the current amplifier circuit, thereby the fuse is melted down. Also, when an anti-fuse is used, the anti-fuse can short an insulating film by applying an excessive voltage. In this manner, the semiconductor device has a function for making it invalid by stopping operation of the signal processing circuit when the role of the device is finished or expires.

Abstract: A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address.

Abstract: A fuse data read circuit includes a fuse data holding unit which holds fuse data, a fuse data read unit which detects fuse data, and a bias voltage generating circuit which generates a bias voltage. The fuse data read unit includes a current mirror circuit and a control circuit provided between the current mirror circuit and the fuse data holding unit. The bias voltage generating circuit applies the bias voltage to the control circuit.

Abstract: A memory includes a cell region; a spare region including a spare block; a fuse region storing remedy information necessary for an access to the spare block instead of a remedy target block, the fuse region comprising non-defective cells in the remedy target block, or including cells in a first block of the spare region; an initial reading fuse storing a block address for identifying the remedy target block or the first block allocated as the fuse region, and a selection address for selecting a region in the remedy target block or a region in the first block allocated as the fuse region; and a controller configured to acquire the remedy information from the fuse region based on the block address and the selection address, and to change the access to the remedy target block to the access to the spare block based on the remedy information.

Abstract: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.

Abstract: A bit memory circuit of an antifuse element set includes two antifuse elements of which logical states are changed from an insulation state to a conductive state when a program voltage is applied. 1-bit data is represented by the logical states of the two antifuse elements. The two antifuse elements are collectively controlled by one decoder circuit. When writing data, the decoder circuit simultaneously performs insulation-breakdown on the two antifuse elements by simultaneously connecting the two antifuse elements to program voltage lines, respectively.

Abstract: Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances.

Abstract: Techniques, apparatus and circuits based on magnetic or magnetoresistive tunnel junctions (MTJs). In one aspect, a programmable circuit device can include a magnetic tunnel junction (MTJ); a MTJ control circuit coupled to the MTJ to control the MTJ to cause a breakdown in the MTJ in programming the MTJ; and a sensing circuit coupled to the MTJ to sense a voltage under a breakdown condition of the MTJ.

Abstract: A redundancy circuit includes an address redundancy circuit block that compares column address information of a defective memory cell and an external input column address and outputs a redundancy column activation signal, and an input/output (IO) redundancy circuit block that, in response to IO fuse information, which is information about a sub-block where a column line of the defective memory cell is arranged, and the redundancy column activation signal, controls whether or not to activate a global IO line connected to an IO pad of the sub-block.

Abstract: A fuse device includes a fuse unit, which includes a cathode, an anode, and a fuse link coupling the cathode and the anode. A transistor includes at least a portion of the fuse unit to be used as an element of the transistor. In at least one example embodiment, the transistor includes a source and a drain disposed on a substrate at each of a plurality of sides of the fuse link, the fuse link being a gate for the transistor.

Abstract: A fuse circuit includes a first power supply line, a second power supply line, a first current source connected between the first power supply line and an output terminal, a second current source connected between the second power supply line and the output terminal, the second current source having higher current supply capacity or current draw-out capacity than the first current source, and a fuse connected in series with the second current source between the second power supply line and the output terminal.

Abstract: A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.

Abstract: A circuit for reading and programming a fuse. The electronic circuit includes a data fuse coupled to a data node and a reference fuse coupled to a reference node. A programming circuit is coupled to the data node, wherein the programming circuit is configured to, when activated, cause the data fuse to be programmed. A sensing circuit is configured to draw current from the data node and the reference node in order to develop a voltage differential between the data node and the reference node during a read operation. A read circuit is configured to, when activated, enable the sensing circuit to develop the voltage differential during the read operation. A protection circuit is configured to form a voltage divider within the sensing circuit during programming of the fuse.

Abstract: A semiconductor memory device comprises a logic circuit supplied with a first supply voltage; a cell array supplied with a second supply voltage higher than the first supply voltage and including plural mutually intersecting word lines and bit lines and plural memory cells connected at intersections thereof; and a word line driver operative to drive the word lines. The word line driver includes plural pull-up circuits connected between the supply terminal of the first supply voltage and the drive terminal of the word line and between the supply terminal of the second supply voltage and the drive terminal of the word line, and a pull-down circuit connected between the drive terminal of the word line and the ground terminal, and drives the word line with an intermediate voltage between the first and second supply voltages in accordance with a driving force ratio between the plural pull-up circuits at the time of driving the word line.

Abstract: Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.

Abstract: A multi-chip package includes a plurality of memory chips and a control chip, wherein the control chip stores information about whether the memory chips are operating normally and selects chips that are operating normally according to an address signal.

Abstract: A redundancy circuit of a semiconductor memory apparatus includes an enable signal generation unit configured to have a plurality of enable fuses corresponding to a first mat grouping information signal and a second mat grouping information signal and enable an enable signal when at least one of the plurality of enable fuses is cut and a mat grouping information signal corresponding to the cut fuse is inputted; a fail address setting control block configured to select the first mat grouping information signal or the second mat grouping information signal depending upon whether an enable fuse corresponding to the first mat grouping information signal is cut or not, and generate fail setting addresses; and a comparison section configured to compare the fail setting addresses with real addresses and generate a redundancy address.

Abstract: A semiconductor device includes a first memory unit, a second memory unit, and a determination unit receiving a first signal permitting a write operation to one of the first memory unit and the second memory unit, and a second signal indicating whether the write operation of information to the first memory unit is finished, wherein the determination unit outputs a signal prohibiting a write operation to the second memory unit, if the second signal indicates the write operation of the information is finished.

Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

Abstract: In a method of manufacturing a semiconductor device, element properties of an element property extraction pattern formed on a semiconductor wafer is extracted as element properties of a current control element corresponding to the element property extraction pattern. A supply energy to the current control element is set which is formed between nodes on the semiconductor wafer, based on the extracted element properties. The set supply energy is supplied to the current control element to irreversible control an electrical connection between the nodes through the device breakdown by the current control element.

Abstract: A redundancy circuit includes at least one fuse set circuit and a fuse control circuit. The at least one fuse set circuit includes a plurality of fuse cells, each of the plurality of fuse cells having a first transistor and a second transistor having same sizes. The first transistor has a first contact resistance and the second transistor has a second contact resistance different from the first contact resistance. Each of the plurality of fuse cells stores a fuse address indicating a defective cell in a repair operation and outputs a repair address corresponding to the stored fuse address. The fuse control circuit, connected to the plurality of fuse cells, controls the plurality of fuse cells in response to a program signal and a precharge signal such that the corresponding fuse address is stored in each of the fuse cells.