Abstract: A word line block select circuit includes a dummy repair logic unit including a dummy logic circuit to output a first control signal and having a delay path for a repair address decision, and a word line activation unit for activating a word line in response to the first control signal and an active command signal.

Abstract: Programmable antifuse transistor, in particular n-channel MOS transistor, and a method for programming at least one such antifuse transistor, includes at least one gate with a gate terminal, source with a source terminal, drain with a drain terminal, and substrate with a substrate terminal, configured so that active circuits/circuit elements do not have to be located at a distance from the antifuse, minimizing area requirements, without additional process steps the level of the potential difference between source terminal and substrate terminal is less than about 0.5 volts, drain terminal and source terminal lie at different potentials. By adjusting drain-source voltage and/or the gate-source voltage a flow of charge carriers occurs between source and drain, causing semiconductor material between source and drain to be thermally heated and to locally melt, forming at least one permanently conducting channel between source and drain.

Abstract: A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Abstract: A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit.

Abstract: A flash memory device includes a main cell array configured to have main memory cells for storing data and a redundancy cell array configured to have redundancy memory cells for repairing a failed memory cell of the main cell array. A page buffer circuit is configured to perform a program operation, a verifying operation and a read operation on the main cell array and the redundancy cell array. A repair circuit includes fuse circuits having fuse memory cells each of which is programmed in response to address information. The repair circuit is operated in response to a program state of the fuse memory cells and output a repair signal. A data input/output controller is configured to control input/output of data to/from the main memory cell or the redundancy memory cell in accordance with the repair signal outputted by the repair circuit.

Abstract: Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second e-fuse string configured to alternately select an e-fuse from the first e-fuse string or the second e-fuse string to be programmed; and a comparator connected to both the first e-fuse string and the second e-fuse string configured to compare a voltage across the first e-fuse string to a voltage across the second e-fuse string to determine a programming state of the e-fuse system.

Abstract: A semiconductor device includes a sensing unit configured to sense whether a value of a programming sensing node is within a predefined range, a fuse connected to the programming sensing node, a programming voltage supplying unit configured to supply a programming voltage to the programming sensing node, and a transferring unit configured to transfer the value of the programming sensing node in response to the sensing result of the sensing unit.

Abstract: A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.

Abstract: Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit.

Abstract: To provide an electrical fuse that is connected to a detection node via a selective transistor, a precharge transistor that precharges the detection node in a state where the selective transistor is off; a bias transistor that passes a bias current to the detection node in a state where the selective transistor is on and the precharge transistor is off, and a detection circuit that detects a potential of the detection node in a state where the bias current is flowing into the detection node, wherein the bias transistor reduces an amount of the bias current in a stepwise manner or a continuous manner.

Abstract: Antifuses and program circuits having the same. The antifuses are embodied as a transistor. When a first power supply voltage is applied to a source, a first program voltage for causing impact ionization is applied to a gate and drain, and a second program voltage for causing channel initiated secondary electron/channel initiated secondary hole (CHISEL/CHISHL) is applied to a well, a dielectric material may be ruptured between the gate adjacent to the drain and the well so that an antifuse may be programmed.

Abstract: A flash memory device includes a chip disable fuse circuit that has a fuse and that outputs a chip disable signal when the fuse is cut out, and a ready/busy control circuit that forcibly activates a ready/busy signal representing an internal operational state in response to the chip disable signal and externally outputs the ready/busy signal through a ready/busy output pin.

Abstract: A memory includes a cell region; a spare region including a spare block; a fuse region storing remedy information necessary for an access to the spare block instead of a remedy target block, the fuse region comprising non-defective cells in the remedy target block, or including cells in a first block of the spare region; an initial reading fuse storing a block address for identifying the remedy target block or the first block allocated as the fuse region, and a selection address for selecting a region in the remedy target block or a region in the first block allocated as the fuse region; and a controller configured to acquire the remedy information from the fuse region based on the block address and the selection address, and to change the access to the remedy target block to the access to the spare block based on the remedy information.

Abstract: An anti-fuse memory cell includes: a first transistor connected with a word line and configured to output a second voltage based on a first voltage supplied to the word line in a write mode; a second transistor connected with a bit line, and configured to output a third voltage supplied to the bit line when the second voltage is supplied to a gate of the second transistor in the write mode; and an anti-fuse element connected to a ground line, and having an insulator film. The insulator film is set to a conductive state with the third voltage supplied from the second transistor.

Abstract: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus includes a core block configured to receive and store external input data, a control unit configured to activate a control signal in response to a test mode signal and a command, when the external input data has a predetermined value, and a fuse circuit configured to perform fuse programming when the control signal is activated.

Abstract: A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit.

Abstract: Stateless hardware security modules facilitate securing data transfers between devices in a data communication system. The stateless hardware security module may communicate with other devices via a secure communication channel to securely transfer information between the client device and another device. As a result, sensitive information such as cryptographic keys and data may be securely routed between the client device and another device. The stateless hardware security module may support a limited set of key management operations to facilitate routing of information between the client device and another device. However, the stateless hardware security module does not need to maintain state information for the keys it maintains and/or uses. As a result, the stateless hardware security module may be advantageously integrated into a variety of client devices.

Abstract: Methods and systems for split threshold voltage programmable bitcells are disclosed and may include selectively programming bitcells in a memory device by applying a high voltage to a gate terminal of the bitcells, where the programming burns a conductive hole in an oxide layer above a higher threshold voltage layer in a memory device. The bitcells may comprise an oxide layer and a doped channel, which may comprise a plurality of different threshold voltage layers. The plurality of different threshold voltage layers may comprise at least one layer with a higher threshold voltage and at least one layer with a lower threshold voltage. The oxide may comprise a gate oxide. The bitcell may comprise an anti-fuse device. The layer with a higher threshold voltage may be separated from an output terminal of the bitcell by the at least one layer with a lower threshold voltage.

Abstract: A one-time programmable memory. The one-time programmable memory has an antifuse and a read circuit configured to read the antifuse. An isolation transistor couples the antifuse to the read circuit. The read circuit and the isolation transistor have different power domains.

Abstract: A device includes a memory cell array and a control circuit, the memory cell array including word-lines, bit-lines, and memory cells arranged at the intersections of the word-lines and the bit-lines, each memory cell including an electrically programmable antifuse element. The control circuit may perform, as a first step, applying a programming voltage to one of the word-lines while applying a ground voltage to bit-lines each connected to respective selected memory cells, and as a second step, after the first step, keeping one of the one word-lines at the programming voltage while concurrently reading the electrical states of the selected memory cells, and according to the read electrical states, applying the ground voltage again to a bit-line connected to an unprogrammed selected memory cell after the first step, and applying a voltage higher than the ground voltage to a bit-line connected to a programmed selected memory cell after the first step.

Abstract: Circuitry on an integrated circuit is provided that may be used to program fuses such as polysilicon fuses. Fuse programming may be performed using an elevated power supply voltage. Other circuitry on the integrated circuit may be powered using a standard power supply voltage that is less than the elevated power supply voltage. Fuse sensing may be performed using the standard power supply voltage. A control block may be used to produce a fuse programming control signal. Power-on-reset circuitry may monitor the elevated power supply voltage and may produce a corresponding elevated power supply voltage power-on-reset signal indicative of whether the elevated power supply voltage is valid. The power-on-reset circuitry may also produce a standard power supply power-on-reset signal indicative of whether the standard power supply voltage is valid. The power-on-reset signals may be used in controlling fuse programming and fuse sensing.

Abstract: A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated.

Abstract: A semiconductor integrated circuit for selecting one from a plurality of external storage devices and loading an execution program that includes a fuse part having a plurality of internal fuse circuits, and a processing unit that loads the execution program from the external storage device selected according to a value indicated by the internal fuse circuit.

Abstract: According to one embodiment, a semiconductor memory device includes a first reference cell being arranged in a first cell array, and a plurality of first fuse cells being arranged in the first cell array. The first reference cell and the plurality of first fuse cells are arranged on the same row or column.

Abstract: A semiconductor memory device includes banks of unit cells, wherein two or more adjacent banks of the banks share a redundancy circuit configured to perform a defect repair operation when an address for accessing a defective unit cell is input.

Abstract: A non-volatile memory cell including an antifuse element having a programming node and a control node, a capacitor element, a precharge element, an access element, and a leakage element. The antifuse element is configured to have changed resistivity (representing a change in logic state) after the programming node is subjected to one or more voltage pulses. The capacitor element, coupled to the programming node, is configured to provide the one or more voltage pulses to the programming node. The precharge element, coupled to the programming node, is configured to increase the one or more voltage pulses provided to the programming to node. The access element, coupled to the control node, is configured to allow determination of the logic state of the antifuse element based on current flow through the access element. The leakage element is coupled to the control node and configured to modify the current flowing through the access element when the resistivity of the antifuse element has not been changed.

Abstract: A semiconductor device includes a first high potential power supply, a second low potential power supply, a third power supply having a potential higher than the first, a fourth power supply having a potential more negative than the second, and an anti-fuse element having a node at each end, one of which is connected to the fourth power supply. A driver transistor has a source connected to the third power supply, a gate connected to a control node and a drain connected to one end of the anti-fuse element. A decoding circuit includes a load transistor connected between the third power supply and the control node and at least one selection transistor connected between the second power supply and the control node. A decision circuit is connected to the first and second power supplies. The decision circuit decides the resistance value of the anti-fuse element. The anti-fuse element is rendered electrically conductive in response to activation of the driver transistor as selected by the decoding circuit.

Abstract: Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.

Abstract: A semiconductor device includes internal voltage generating circuits, a switching circuit, load circuits, a control circuit. Each of the plurality of load circuits is supplied with voltage through the switching circuit from any one of the plurality of internal voltage generating circuits. The control circuit defines connecting combinations by the switch circuit. The control circuit supplies a control signal to the switch circuit, based on the control signal corresponding to the definitions of the connecting combinations. The control circuit allows switching the connecting combinations when the semiconductor device tests in a test mode. The control circuit prohibits switching the connecting combinations in a non-test mode. The switch circuit connects between each of m of the internal voltage generating circuits and each of n of the load circuits through a connecting combination which is selected, based on the control signal, from mn of the connecting combinations.

Abstract: A semiconductor memory device includes an enable fuse unit configured to generate a repair enable signal corresponding to a cutting state of an enable fuse after a power-up operation starts, and an address fuse unit enabled in response to the repair enable signal, and configured to generate an output signal in response to an external address and whether or not an address fuse is programmed.

Abstract: A fuse circuit includes a program unit and a sensing unit. The program unit is programmed in response to a program signal and outputs a program output signal in response to a sensing enable signal. The sensing unit outputs a sensing output signal based on the program output signal and the sensing output signal indicates whether the program unit is programmed or not. The program unit includes an anti-fuse cell, a selection transistor, a program transistor and a sensing transistor. The anti-fuse cell includes at least two anti-fuse elements which are connected in parallel and are respectively broken down at different levels of a program voltage.

Abstract: A semiconductor integrated circuit device includes a first block, a second block, and a control section. The first block includes a first fuse, a first switching configured to write data to the first fuse, a first holding portion capable of holding a first instruction, and a first instruction portion configured to turn on the first switching when a second instruction is given thereto with the first instruction. The second block includes a second fuse, a second switching configured to write data to the second fuse, a second holding portion capable of holding the first instruction, and a second instruction portion configured to turn on the second switching when the second instruction is given thereto with the first instruction. The control section issues the second instruction at a point in time when the first instruction is held in the first and second holding portions.

Abstract: An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.

Abstract: A semiconductor device including a first switch coupled to a first power supply line, a second switch coupled to the first switch and to a second power supply line, and a storage part provided in a path which is between the second power supply line and the first switch, and having a high resistance state and a low resistance state, and wherein the first switch is turned on and the second switch is turned off when a resistance state of the storage part is in a high resistance state.

Abstract: A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.

Abstract: The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output from the fuse selection circuit, is supplied with an externally inputted trigger signal that permits nonvolatile recording of the fuse elements, and, in response to the output and the trigger signal, records the fuse element corresponding to the internal address signal line among the plurality of fuse elements while recording at least one of the plurality of fuse elements other than the fuse element thus recorded.

Abstract: There are provided a row predecoder that predocodes an address irrespective of whether the address to which access is requested is a defective address, a row main decoder that controls a sub-word driver, based on a predecode signal generated by the row predecoder, and a repair determining circuit that determines whether the address is a defective address. The row main decoder, the row predecoder, and the repair determining circuit all have a shape in which a column direction is set to be a longitudinal direction. The row predecoder and the repair determining circuit are arranged adjacent to each other in the column direction, and are arranged in parallel with the row main decoder.

Abstract: Nonvolatile memory element circuitry is provided that is based on metal-oxide-semiconductor transistor structures. A nonvolatile memory element may be based on a metal-oxide-semiconductor transistor structure that has a gate, a drain, a source, and a body. During programming operations, control circuitry floats the body while applying a positive voltage to the drain and a negative voltage to the source. This causes the drain and source, which serve as the collector and emitter in a parasitic bipolar transistor, to break down. The drain-to-source (collector-to-emitter) breakdown causes sufficient current to flow through the source to alter the source electrode and thereby increase the resistance of the source significantly. During sensing operations, control circuitry may apply a voltage across the drain and source while grounding the body to determine whether the memory element has been programmed.

Abstract: A nonvolatile semiconductor memory device includes a memory cell, a precharge control circuit, a power supply circuit, a bit line driver, a word line driver, a first multiplexer, and a second multiplexer. The memory cell includes an anti-fuse storage element and a selection transistor. Before data are written into the anti-fuse storage element of the memory cell, the anti-fuse storage element is set up in a precharged state by the precharge control circuit, the bit line driver, the word line driver, the first multiplexer, and the second multiplexer.

Abstract: The application discloses an integrated circuit comprising: circuitry; a fusebox for storing an array of data identifying faulty elements within said circuitry; at least one fusebox controller for repairing said faulty elements in said circuitry in response to data received from said fusebox; a data communication path linking said fusebox controller with said fusebox; wherein said data stored in said fusebox is compacted data and said at least one fusebox controller comprises a data expander for expanding said compacted data received from said fusebox via said data communication path prior to repairing any faulty elements in said circuitry.

Abstract: A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section reading series resistance of the first filament and the second filament.

Abstract: Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.

Abstract: Embodiments extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements. Accordingly, embodiments significantly reduce area requirements and control circuitry complexity of memory elements. Embodiments can be used in non-volatile memory storage, for example, and are suitable for use in system on chip (SoC) products.

Abstract: An anti-fuse circuit includes an anti-fuse coupled to a sensing node, a driving unit configured to rupture the anti-fuse in response to a rupture enable signal, an anti-fuse status detecting unit configured to output an anti-fuse status detecting signal in response to a voltage at the sensing node corresponding to a rupture status of the anti-fuse, and a sensing current supplying unit configured to supply sensing current to the sensing node in response to a rupture sensing signal.

Abstract: A semiconductor memory device includes a repair control signal generation unit configured to compare a repair target address programmed corresponding to a repair target memory cell with an external address, and generate a repair control signal. an address decoding unit configured to control a normal memory cell or a redundancy memory cell corresponding to the external address to be accessed in response to the repair control signal and an internal active signal, and an activation interval detection unit configured to generate an interval detection signal by detecting a time interval between an activation timing of the repair control signal and an activation timing of the internal active signal in a test operation mode.

Abstract: A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based one-time programmable (OTP) element. In one example, the static storage element includes a thin gate-oxide that acts as a resistance element, which, depending on whether its blown, sets the latch into one of two states.

Abstract: A semiconductor memory device can reduce a circuit area necessary for row repair. The semiconductor memory device includes a plurality of memory banks, a plurality of cell arrays arranged in each of the memory banks, a plurality of array word lines arranged in each of the cell arrays, one or more repair word lines arranged in each of the cell arrays, and a plurality of repair information storages configured to store bank information and row addresses of the array word lines to be replaced with the repair word lines.

Abstract: Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory.

Abstract: A combo semiconductor memory apparatus capable of reducing current and power consumption is provided. The semiconductor memory apparatus includes: a signal generator that generates a voltage control signal according to the level of an external voltage; and a voltage generator that pumps up the level of the external voltage in response to the voltage control signal and outputs the pumped voltage to a high-level voltage output terminal, or supplies the external voltage as a high-level voltage.

Abstract: A temperature sensor includes a temperature sensing unit for producing a sensing level by sensing an internal temperature in a semiconductor memory device, a reference level generating unit for setting up a reference level by selecting one of a plurality of reference voltages, which are set up according to the internal temperature of the semiconductor memory device, in response to a test mode signal and a temperature detecting signal, wherein the reference level generating unit includes fuse, and a comparison unit for comparing the sensing level to the reference level and producing the temperature detecting signal.