Abstract: It is an object to provide memory and a semiconductor device in which falsification of data written thereinto is prevented. The memory includes a memory circuit, a writing circuit, and a reading circuit. The memory circuit has a memory cell array in which a plurality of memory cells where “0” and “1” of binary data can be written are arranged. The writing circuit includes a first writing circuit which writes one of “0” and “1” of binary data into one of the memory cells included in the memory circuit, and a second writing circuit which writes the other of “0” and “1” of binary data into one of the memory cells included in the memory circuit.

Abstract: An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on the information stored in the nonvolatile memory.

Abstract: An electrically programmable fuse, a method of operating the same and an integrated circuit (IC) incorporating the fuse or the method. In one embodiment, the fuse includes: (1) at least one fuse element configured to be programmed with contents and (2) an inhibitor coupled to the at least one fuse element and configured to be activated to inhibit subsequent reprogramming of the at least one fuse element.

Abstract: Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second e-fuse string configured to alternately select an e-fuse from the first e-fuse string or the second e-fuse string to be programmed; and a comparator connected to both the first e-fuse string and the second e-fuse string configured to compare a voltage across the first e-fuse string to a voltage across the second e-fuse string to determine a programming state of the e-fuse system.

Abstract: A semiconductor memory device includes a repair node; a fuse, one side of which is coupled to the repair node; a pull-down unit configured to selectively transfer a ground voltage to the repair node; a pull-up unit configured to selectively transfer a driving voltage to another side of the fuse; a latch unit configured to latch a signal at the repair node; and a switch unit coupled between the latch unit and the repair node and configured to selectively transfer the signal from the repair node to the latch unit.

Abstract: A latch type fuse circuit includes a non-volatile memory, a PMOS transistor, and an output circuit. The non-volatile memory cell stores a logic bit. A voltage level of a source of the PMOS transistor determines the latch type fuse operating in the data program status or the data read status. In the data program status, a gate of the PMOS transistor receives a first signal including an address and the logic bit for determining the logic bit written in the non-volatile memory cell. The output circuit includes two NMOS transistors and an inverter. In the data read status, the output circuit can latch the logic bit.

Abstract: A semiconductor memory device includes: a repair node; a fuse one side of which is coupled to the repair node; a pull-down unit configured to selectively transfer a ground voltage to the repair node; a pull-up unit configured to selectively transfer a driving voltage to another side of the fuse; and a voltage drop unit coupled between the pull-up unit and the fuse and configured to lower a voltage level of the driving voltage.

Abstract: A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit.

Abstract: A non-volatile semiconductor storage device includes: a plurality of memory cells storing information based on a change in resistance value; and a plurality of first and second wirings connected to the plurality of memory cells and activated in reading data from and writing data to a certain one of the memory cells. Each of the memory cells includes: an irreversible storage element storing information based on a change in resistance value associated with breakdown of an insulation film; and a voltage booster circuit receiving an input of a voltage-boost clock performing clock operation in writing data to a certain one of the memory cells and applying a voltage-boosted signal boosted based on the voltage-boost clock to one end of the irreversible storage element.

Abstract: Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

Abstract: An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The switch device is disposed in the integrated circuit, and has an output node coupled to the e-fuse units and a first input node coupled to a first power source which supplies a first reference voltage acting as a programming voltage of the e-fuse macro. The switch device connects the first power source to the e-fuse units when the e-fuse macro is operated under a programming mode.

Abstract: To include an input circuit block to which a plurality of bits are input and a processing circuit block that processes an internal signal output from the input circuit block. The input circuit block includes a plurality of unit input circuits arranged in an X direction to which the bits are input, respectively. Each of the unit input circuits includes an input wiring pattern that extends in a Y direction and a transistor of which a control electrode is connected to a corresponding one of the input wiring pattern. Coordinates of the input wiring pattern and the transistor corresponding to the input wiring pattern in the X direction do not overlap with each other. With this arrangement, by sharing the input wiring pattern between circuit blocks adjacent to each other in the Y direction, it is possible to reduce the number of pre-decode wirings.

Abstract: A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.

Abstract: A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.

Abstract: A programmable latch circuit (200) can include a volatile latch (206) that may regenerate a value determined by programmable section (202). In a test operation, a variable current source (216?) can generate a current (IBASE) that can be mirrored in test sections (252-0 and 252-1) and compared to a current drawn by either programmable element (210-0) or (210-1) by a latching operation of volatile latch (206). Variable current source (216?) can enable characterization of programmable elements (210-0 or 210-1) as well as adjustable test threshold limits. A program voltage (Vprog) applied to programmable elements (210-0 or 210-1) can be also be variable to allow for characterization of programmable elements (210-0 and 210-1) over a range of voltages.

Abstract: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion.

Abstract: The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output from the fuse selection circuit, is supplied with an externally inputted trigger signal that permits nonvolatile recording of the fuse elements, and, in response to the output and the trigger signal, records the fuse element corresponding to the internal address signal line among the plurality of fuse elements while recording at least one of the plurality of fuse elements other than the fuse element thus recorded.

Abstract: A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.

Abstract: A semiconductor memory device comprises an anti-fuse, a memory circuit including memory cells, and a peripheral circuit configured to access only an area of the memory circuit selected depending on a state of the anti-fuse.

Abstract: One-time programmable cell and memory device having the same includes a first metal oxide semiconductor (MOS) transistor configured to form a current path between a first node and a second node in response to a read-control signal, a second MOS transistor configured to form a current path between a third node and the second node in response to a write-control signal and an anti-fuse connected between the second node and a ground voltage terminal, wherein a voltage applied to the second node is output as an output signal.

Abstract: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.

Abstract: Disclosed are a unit cell capable of improving a reliability by enhancing a data sensing margin in a read operation, and a nonvolatile memory device with the same. The unit cell of a nonvolatile memory device includes: an antifuse having a first terminal between an input terminal and an output terminal; and a first switching unit coupled between a second terminal of the antifuse and a ground voltage terminal.

Abstract: A semiconductor integrated circuit has a voltage supply terminal; a first input terminal fed with a first input signal; an output terminal that outputs an output signal; a second input terminal fed with a second input signal; a first MOS transistor having one end connected to the voltage supply terminal and a gate electrode connected to the first input terminal; a second MOS transistor having one end connected to a first potential, an other end connected to the output terminal, and a gate electrode connected to the second input terminal; and a program element acting as a MOS transistor having one end connected to the other end of the second MOS transistor and an other end connected to a second potential higher than the first potential.

Abstract: Provided are an electrical fuse, a semiconductor device having the same, and a method of programming and reading the electrical fuse. The electrical fuse includes first and second anodes disposed apart from each other. A cathode is interposed between the first and second anodes. A first fuse link couples the first anode to the cathode, and a second fuse link couples the second anode to the cathode.

Abstract: An integrated circuit includes an array of memory cells and a first circuit. The array includes word lines. Each word line is coupled to a plurality of memory cells. The first circuit is configured to refresh memory cells along a first number of word lines in response to a refresh command. The first number of word lines is based on a sensed temperature.

Abstract: A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated.

Abstract: Structures for fuses to control repair of multiple memories embedded on an integrated circuit are provided along with methods of use. A set of fuses is shared to control repair of a plurality of memories. Some of the fuses are associated with a memory to be repaired. Others of the fuses identify how the repair is accomplished.

Abstract: A fuse circuit or a redundancy circuit is capable of detecting a fuse with a crack. The fuse circuit includes a fuse block configured to drive an output node through a current path including a fuse in response to a fuse enable signal, and a voltage detection block configured to detect a voltage level of the output node based on a critical voltage adjusted according to a test mode signal, thereby generating a fuse condition signal.

Abstract: A fuse circuit includes a fuse unit configured to form a current path on a first node according to whether or not a fuse is cut; a driving current controller configured to control a potential level of the first node in response to a test signal; and an output unit configured to output a fuse state signal in response to the potential level of the first node.

Abstract: A semiconductor device includes a first terminal, a second terminal, and a fuse link that connects between the first terminal and the second terminal. The first terminal and the fuse link have a polysilicon layer doped with an impurity ion and a layer containing a metal element laminated on the polysilicon layer. The second terminal has a polysilicon layer not doped with an impurity ion and a layer containing a metal element laminated on the polysilicon layer, in at least a part of an end side connected to the fuse link.

Abstract: E-fuses in an E-fuse memory array are programmed by applying a first programming pulse to a plurality of E-fuses to program the plurality of E-fuses to a first state; and then applying a second programming pulse to at least a selected E-fuse in the plurality of E-fuses to program the selected E-fuse to a second state.

Abstract: A semiconductor device is provided including a first fuse link having a copper-containing metal film, a second fuse link having a polysilicon film, a semiconductor substrate, and a field insulating film formed on the semiconductor substrate. The second fuse link is formed on the field insulating film. An interlayer insulating film is provided between the first fuse link and the second fuse link. The first fuse link is electrically connected to the second fuse link via a first plug formed in the interlayer insulating film.

Abstract: A semiconductor memory device can reduce a circuit area necessary for row repair. The semiconductor memory device includes a plurality of memory banks, a plurality of cell arrays arranged in each of the memory banks, a plurality of array word lines arranged in each of the cell arrays, one or more repair word lines arranged in each of the cell arrays, and a plurality of repair information storages configured to store bank information and row addresses of the array word lines to be replaced with the repair word lines.

Abstract: A flash memory device includes a main cell array configured to have main memory cells for storing data and a redundancy cell array configured to have redundancy memory cells for repairing a failed memory cell of the main cell array. A page buffer circuit is configured to perform a program operation, a verifying operation and a read operation on the main cell array and the redundancy cell array. A repair circuit includes fuse circuits having fuse memory cells each of which is programmed in response to address information. The repair circuit is operated in response to a program state of the fuse memory cells and output a repair signal. A data input/output controller is configured to control input/output of data to/from the main memory cell or the redundancy memory cell in accordance with the repair signal outputted by the repair circuit.

Abstract: A semiconductor integrated circuit device includes a first fuse circuit, a second fuse circuit, and a control signal generating circuit which sends a first control signal and executes program such that the resistance value of the first fuse circuit becomes greater than the resistance value of the second fuse circuit, and sends a second control signal and executes reprogram such that the resistance value of the second fuse circuit becomes greater than the resistance value of the first fuse circuit.

Abstract: A fuse circuit of a semiconductor integrated apparatus includes first and second fuse blocks. The first fuse block includes a first up fuse block where a first plurality of fuses are arranged and a first down fuse block where a second plurality of fuses are arranged. The second plurality of fuses comprises fewer fuses than the first plurality of fuses. The second fuse block includes a second up fuse block where a third plurality of fuses are arranged, the third plurality of fuses comprising the same number of fuses as the second plurality of fuses, and a second down fuse block that includes a fourth plurality of fuses, the fourth plurality of fuses comprising the same number of fuses as the first plurality of fuses. The first up fuse block is opposite the second up fuse block and the first down fuse block is opposite the second down fuse block.

Abstract: An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.

Abstract: A nonvolatile memory device includes at least one memory cell which comprises a diode and a metal oxide antifuse dielectric layer, and a first electrode and a second electrode electrically contacting the at least one memory cell. In use, the diode acts as a read/write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

Abstract: A fuse circuit includes a fuse unit configured to drive an output terminal via a current path including a fuse in response to a fuse enable signal; and a comparison unit configured to be activated in response to an activation signal for comparing a reference voltage having a predetermined level with a voltage level of the output terminal to generate a fuse state signal.

Abstract: A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory cells. A row decoder selects the word lines in response to a row address. Further, the row address decoder selects the redundant word line when a replacement signal is received. A column decoder selects the bit lines in response to a column address. A row address redundancy circuit stores a redundant row address. The row address redundancy circuit provides the replacement signal when the redundant row address corresponds to the received address. The mode setting circuit receives a mode signal having a normal mode and a test mode. The mode setting circuit outputs the replacement signal to the row decoder when the mode signal is in the normal mode, and prohibits an output of the replacement signal.

Abstract: In a semiconductor memory device, a repair circuit includes mode fuses to select one of plural repair modes corresponding to plural kinds of defects, respectively. The semiconductor memory device can repair a defective memory cell having operational margin defect without using redundancy memory cells.

Abstract: A fuse monitoring circuit for a semiconductor device includes a repair fuse unit including a number of fuses to which a repair address is programmed, and configured to output fuse state signals corresponding to the connection states of the respective fuses in response to a fuse initialization signal. A serial fuse monitoring unit is configured to output a fuse state monitoring signal corresponding to each fuse state signal selected by an applied address in response to a serial monitoring test mode signal. Also, a parallel fuse monitoring unit is configured to output a repair monitoring signal by comparing an applied address and the repair address in response to a parallel monitoring test mode signal. An output unit is configured to output the fuse state monitoring signal and the repair monitoring signal to an output pad in response to an output control signal.

Abstract: An anti-fuse memory cell includes: a first transistor connected with a word line and configured to output a second voltage based on a first voltage supplied to the word line in a write mode; a second transistor connected with a bit line, and configured to output a third voltage supplied to the bit line when the second voltage is supplied to a gate of the second transistor in the write mode; and an anti-fuse element connected to a ground line, and having an insulator film. The insulator film is set to a conductive state with the third voltage supplied from the second transistor.

Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can includeselectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.

Abstract: Address comparison circuits each compare the defect addresses programmed in the redundancy fuse circuits with an access address and output a redundancy signal when a comparison result is a match. A switch circuit is controlled to switch according to a redundancy selection signal output from a selection fuse circuit, and validates in response to the redundancy signal either a corresponding regular redundancy line or the reservation redundancy line. By dividing the redundancy lines into the regular redundancy lines and the reservation redundancy line, each of the redundancy fuse circuits can be made to correspond to one of the plurality of redundancy lines with the simple switch circuit. Therefore, a difference in propagation delay time of a signal can be made small and a difference in access time can be made small between when relieving a defect and when there is no defect.

Abstract: A program lock circuit for inhibiting programming of memory cells. A memory array can have both mask programmable and one-time programmable memory cells connected to the wordlines and the bitlines. Since the one-time programmable memory cells are convertible into mask programmable memory cells through mask programming, such as diffusion mask programming or contact/via mask programming, these mask programmed cells are still electrically programmable, thereby destroying the originally stored data. The programming lock circuit inhibits programming of the mask programmed cells by detecting an activated wordline during a programming operation, and then immediately disabling or decoupling the high voltage supply that is provided to the wordline drivers. Mask programmed transistor elements coupled to each wordline detect the wordline voltage and disable the high voltage supply. A mask programmable master lock device can be provided to inhibit all the rows in the memory array from being programmed.

Abstract: A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp, for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.

Abstract: A device includes a memory configured so that, in the event that one pass-gate transistor associated with a bit cell is determined to be excessively weak such that reading the bit cell could be undesirably difficult, a second pass-gate transistor can be configured to support a read operation. For example, during a manufacturing test procedure, the access speed of each bit cell at a memory device is determined. If a bit cell fails to achieve a desired access speed, the column of the memory that includes the defective bit cell can be configured to access information stored at the bit cell using the second bit line associated with the second pass-gate transistor.

Abstract: A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non-selected, and a low resistance when connected to the selected row and column.

Abstract: A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and a control block for comparing the write data with the global data to thereby disable the amplifying block when the write data and the global data have substantially the same data value.