Abstract: A circuit for power-off state storage in an electronic device having a positive power supply includes a storage circuit comprising first and second storage capacitors and a write circuit having a plurality of N-type transistors coupled to the storage circuit. The write circuit is operable to write a data bit to the first and second storage capacitors. The power-off state storage circuit also has a sense amplifier connected to the storage circuit and that is operable to read the data bit stored by the storage capacitors. The first and second capacitors in the storage circuit are electrically isolated from the positive power supply such that when the positive power supply is terminated any charge stored on the first and second capacitors is prevented from discharging to the terminated power supply.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can detect a brown-out of a supply voltage. The memory device comprises a voltage detection circuit to monitor a supply voltage and provide a signal if the supply voltage drops below a predetermined value. A latch is coupled to the voltage detection circuit and can be programmed to indicate if the supply voltage dropped below the predetermined value. An external controller can read a status of the latch. The memory, therefore, can provide an indication to an external controller that a reset, or initialization, operation is needed.

Abstract: A memory integrated circuit (100) includes a core cell array (102) having a plurality of core cells for storing data in one of a plurality of states, a plurality of power supply buses (140, 142, 144, 146) including a sensing power supply bus (144) and a sensing ground bus (146) dedicated to sensing states of core cells. The integrated circuit firther includes a sense threshold generating circuit (126) which generates a sense threshold signal in response to a power supply potential on the sensing power supply bus and a ground potential of the sensing ground bus. The integrated circuit still further includes a plurality of sense amplifiers (108) which detect the states of core cells in relation to the sense threshold signal. The sense amplifiers are coupled to the sensing power supply bus and the sensing ground bus so that substantially all power supply noise at the plurality of sense amplifiers and the sense threshold generator is common node noise.

Abstract: A semiconductor memory device for providing data together with an echo clock as an indicating signal representing a time for providing or presenting data in an electronic system is described. The device comprises an echo data latch circuit for generating a source signal of the echo clock in response to an output of a sense amplifier for sensing and amplifying the data of a memory cell during a read operation, and for producing the source signal of the echo clock in response to a predetermined level of power voltage during a write operation; and an output circuit, connected between the echo data latch circuit and an echo clock output terminal, for receiving the source signal of the echo clock and for outputting the echo clock to the output terminal in response to control data relating to an external clock, thereby minimizing or reducing clock skew and also preventing speed push.

Abstract: A DRAM includes first to third voltage lowering circuits for lowering a power supply voltage supplied from the exterior and supplying the lowered voltage to an internal circuit. The first voltage lowering circuit is a feedback type circuit for creating a first potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a {overscore (RAS)} signal input buffer, {overscore (CAS)} signal input buffer and {overscore (WE)} signal input buffer. The second voltage lowering circuit is a feedback type circuit is a source follower type circuit for creating a second potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a VBL generating circuit for generating a bit line precharge potential and a VPL generating circuit for generating a cell plate potential.

Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.

Abstract: A stencil printer for printing an image on a paper or similar recording medium with a master wrapped around its ink drum is disclosed. The stencil printer can be held in a power save mode for saving power when it is not used, and can recover from the power save mode without any wasteful step so as to prevent the first print time from being delayed.

Abstract: A method for accessing to a DRAM and a DRAM controller of the same, which enables a high speed DRAM access and a DRAM controller. Provided is an accessing method to a DRAM, which comprises the steps of detecting an access type to the DRAM; and changing an access mode depending on the detected access type. Furthermore, provided is an accessing method to a DRAM which comprises the steps of detecting whether a currently accessed row address and an address lastly accessed; and changing an access mode depending on an existence of the coincidence of the detected row addresses.

Abstract: A hardware assisted memory module (HAMM) is coupled to a conventional computer system. During normal operation of the computer system, the HAMM behaves like a conventional memory module. The HAMM, however, detects and responds to at least one of the following trigger events: 1) power failure, 2) operating system hang-up, or 3) unexpected system reset. Upon detection of a trigger event, the HAMM electronically isolates itself from the host computer system before copying digital information from volatile memory to nonvolatile memory. Once isolated, the HAMM takes its power from an auxiliary power supply. The HAMM can be configured to copy all or part of the digital information to nonvolatile memory. Upon either a request or at power-up, the HAMM copies the digital information from the nonvolatile memory into the volatile memory. If there is a normal computer shutdown, the operating system will first warn the HAMM before shutting down, thus precluding it from performing a backup operation.

Abstract: The present invention relates to a semiconductor storage device in which data retention current consumption can be reduced. This device comprises memory cells, an internal power supply circuit for supplying an internal voltage HVC to the memory cells, transistors for halting the internal power supply circuit, and a switch circuit (transistors) for selectively supplying one of the internal voltage HVC or an externally supplied voltage HVC_EXT to the memory cells. When the memory cells are in a stand-by state (SLEEP=1) and are not engaged in a refresh operation, the internal power supply circuit is halted, and the externally supplied voltage HVC_EXT is supplied to the memory cells.

Abstract: The present invention is provided with a switch circuit which can turn on/off electric power supply from a battery. Further, a CPU transfers and evacuates specific data stored in a DRAM when electric power supply from a main power supply is stopped and electric power supply from a battery is performed. Thereafter, the CPU turns off the switch circuit and stops electric power supply from the battery.

Abstract: A latch type level shift circuit includes an internal power supply potential generating circuit for generating first and second internal power supply potentials; a latch circuit having first and second nodes and driven by the first and second internal power supply potentials; a level shifter having first and second output terminals and driven by the first internal power supply potential and a fixed potential; a first MOS transistor having a gate applied with the fixed potential; and a second MOS transistor having a gate applied with the fixed potential. The first MOS transistor is connected between the first node and the first output terminal, and the second MOS transistor is connected between the second node and the second output terminal.

Abstract: A memory device includes a memory cell array, control circuits, and a voltage regulation system. The voltage regulation system includes an array power bus distributing an array supply voltage to the array, and a control circuit power bus distributing a control circuit supply voltage to the control circuits. Regulator circuits are coupled to the array power bus at spaced-apart locations along the bus which allow each regulator circuit to respond independently to a localized variation in the array supply voltage. Other regulator circuits are similarly coupled to the control circuit power bus. The regulator circuits which are unneeded for a particular operating mode of the memory device can be turned off during active memory cycles, and all the regulator circuits can be turned off during stand-by memory cycles.

Abstract: A DRAM module is applied to the system LSI which is provided with a standby mode for suppressing the whole operation thereof and an operation standby mode which permits at least the DRAM module to operate but suppresses the operation of other circuits. The above-mentioned modes as well as a substrate bias control technology are applied to the CMOS system LSI that operates on a low voltage. The system LSI is controlled to hold or not to hold data, enabling a memory of a large capacity to be mounted and consuming a sufficiently decreased amount of electric power.

Abstract: A DRAM includes first to third voltage lowering circuits for lowering a power supply voltage supplied from the exterior and supplying the lowered voltage to an internal circuit. The first to third voltage lowering circuits are separately provided. The first voltage lowering circuit is a feedback type circuit having a P-channel MOS transistor. The first voltage lowering circuit is an exclusive circuit for creating a first potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a {overscore (RAS)} signal input buffer, {overscore (CAS)} signal input buffer and {overscore (WE)} signal input buffer. The second voltage lowering circuit is a feedback type circuit having a P-channel MOS transistor or source follower type circuit having an N-channel MOS transistor.

Abstract: An IC card comprising an electronic device and a battery within a plastic card for electrically energizing the electronic device. The battery is comprised of a monolithic electrochemical cell having a lithium-containing cathode, a carbon anode, and a porous polymer separator infused with electrolyte solution. The cell has a thickness of less than 0.7 mm. A package containing the cell formed of a sheet of flexible laminate material having at least one metal foil layer and a layer of an adhesive-like polymeric material. The battery has an overall thickness of less than 0.8 mm.

Abstract: A removable memory device includes a memory for storing individual information therein, and a memory manager for protecting the memory when the removable memory device is not connected to a portable terminal device and for allowing access thereto when the removable memory device is connected to the portable terminal. A controller physically part of the removable memory device, is used for detecting an interconnection with the portable terminal device and for controlling the memory manager. The removable memory device protects the individual information stored within it from being illegally used.

Abstract: An electronic control unit is provided with a microcomputer, a power supply circuit and a filter circuit. The microcomputer comprises a CPU, a ROM, a RAM and a SRAM. A voltage-drop detecting circuit within the power supply circuit receives a constant voltage generated in a constant voltage circuit and outputs a voltage detection signal WI by monitoring fall of such constant voltage. The filter circuit also receives the WI signal, generates a WI(A) signal and a WI(B) signal and outputs the WI(B) signal to the SRAM as the signal for restricting the data write operation. The CPU allows start of the data write operation to the SRAM and executes the write operation of data for each data that requires the concurrency when both WI(A) and WI(B) signals indicate permission of the data write operation.

Abstract: In a sleep mode, data held in a logic circuit is saved to a memory circuit under the control of a transfer control circuit, and thereafter supply of an operation power supply voltage to the logic circuit from a logic power source is stopped. A memory-embedded LSI capable of reducing current consumption in a standby state is provided.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can detect a brown-out of a supply voltage. The memory device comprises a voltage detection circuit to monitor a supply voltage and provide a signal if the supply voltage drops below a predetermined value. A latch is coupled to the voltage detection circuit and can be programmed to indicate if the supply voltage dropped below the predetermined value. An external controller can read a status of the latch. The memory, therefore, can provide an indication to an external controller that a reset, or initialization, operation is needed.

Abstract: A method and circuit are disclosed for maintaining stored data within a ferroelectric memory device. The circuit includes a first circuit for selectively logically inverting the data in the ferroelectric memory device. A second circuit enables the first circuit at the one or more predetermined times. A third circuit logically inverts data to be written to and data read from the ferroelectric memory device following every other predetermined time. In this way, the circuit is capable of inverting the data values stored in the ferroelectric memory device, thereby reducing the susceptibility of imprint.

Abstract: The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.

Abstract: In order to prevent data bits stored in the memory cells of a dynamic random access memory device from destruction, a booster circuit is coupled between a power supply pin and an internal power supply line, and keeps the voltage level on the internal power supply line constant regardless of the voltage level at the power supply pin.

Abstract: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Abstract: The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.

Abstract: A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.

Abstract: A system for preventing data loss when volatile memory is used to store data either internal or external to a host computer. In the preferred embodiment, the system provides uninterrupted power to the volatile memory and to a non-volatile storage device such as a magnetic disk drive or other non-volatile memory. Upon loss of commercial power, host computer shut down, or manual initiation, the data stored in the volatile memory will be automatically backed-up to the non-volatile storage device via a high bandwidth data path. Under normal conditions, data stored in volatile memory are accessible by the host computer using a high bandwidth data path.

Abstract: An electronic system, comprising a digital processor and an EEPROM, has circuit logic and program software or firmware for determining if a programming voltage level is sufficient for reliably programming the EEPROM. A charge pump is enabled and generates a voltage used for programming of the EEPROM. The enabled charge pump thereby loads a battery power supply. In addition, a test load may be connected to the output of the charge pump to simulate the EEPROM load during a programming operation to the EEPROM. The charge pump output voltage is measured to determine if at least a desired voltage value is obtained. Once the charge pump voltage level has been pre-qualified for the desired voltage value, an actual programming operation to the EEPROM may be performed. If the voltage level does not reach the desired value then a programming operation is inhibited and the electronic system may alarm or shut down operation.

Abstract: A memory system for a digital computer includes a non-volatile random access memory for storing past and present values of state variables is immune from electromagnetic transients and other disturbances which can affect the integrity of the memory. Each memory cell is designed with an energy storage device and logic devices which control the logic sequence for charging of the energy storing devices. These memory cells are aligned in an array and specially designed system is included with this that takes into account the length of time required in order to charge each cell in the array.

Abstract: A dynamic semiconductor memory device of a random access type has an initialization circuit that controls the switching-on operation of the semiconductor memory device and of its circuit components. The initialization circuit supplies a supply voltage stable signal once the supply voltage has been stabilized after the switching-on of the semiconductor memory device. The initialization circuit has an enable circuit that receives the supply voltage stable signal and further command signals externally applied to the semiconductor memory device. The enable circuit supplies an enable signal after a predetermined proper initialization sequence of the command signals applied to the semiconductor memory device is identified. The enable signal effects the unlatching of a control circuit provided for the proper operation of the semiconductor memory device.

Abstract: According to disclosed embodiments, a semiconductor memory (100) can include a restore voltage control circuit (106) that can supply a first internal voltage V.sub.INT that is lower than an external power supply voltage Vcc, a second internal voltage V.sub.INTS 1 that is lower than the first internal voltage V.sub.INT, and a third internal voltage V.sub.INT 2 equal to or less than the first internal voltage V.sub.INT and greater than the second internal voltage V.sub.INTS 1. The semiconductor memory (100) can further include a p-channel MOS transistor (T108) that can provide a conductive path between a voltage supply path (116) and a sense amplifier (104) in response to a sense signal Se at the first internal voltage V.sub.INT. A switch signal generating circuit (112) can supply a switch signal Sw that can change the potential on the voltage supply path (116) from the second internal voltage V.sub.INTS 1 to the third internal voltage V.sub.INTS 2 while transistor T108 is conductive.

Abstract: A control device for a motor vehicle includes a central processing unit that is coupled to a non-volatile memory, a volatile memory and a key switch. The control device ensures transmission of data between memories with high reliability when control operation is repeatedly stopped and started upon the turn-off and turn-on of the key switch, while assuring a reduced period of time during which power is supplied from a back-up power supply to the device, and with a reduced frequency of writing of the data.

Abstract: An isolation mechanism serves to isolate digital signal processor outputs from a dynamic random access memory controller upon the occurrence of a low power condition. The isolation prevents corruption of dynamic random access memory due to low power. The isolation mechanism receives inputs of a first low power indicator and a second low power indicator. The first low power indicator pulls low and the second low power indicator is forced high when a low power condition exists. One embodiment of the isolation mechanism includes a NAND gate connected to a first low power indicator signal and to a second low power indicator signal as inputs, a NOR gate connected with a NAND gate output as input, and a flip flop connected with a NOR gate output and the first low power indicator as inputs. The flip flop output is input to the NOR gate.

Abstract: A battery assembly is provided for holding a battery and for supplying power to an integrated circuit. When the battery is removed from the battery assembly, the battery assembly provides a LOW level signal to either the high voltage input (Vdd) of the integrated circuit or the reset port of the integrated circuit. The battery assembly includes a battery holder, a negative electrode attached to the battery holder and electrically connected to the a negative power line related to the integrated circuit, and a positive electrode also attached to the battery holder and connected to a positive power line to provide power to the integrated circuit. The positive and negative electrodes are disposed such that the battery may be held between the positive and negative electrodes, with positive and negative terminals of the battery in electrical contact with the positive and negative electrodes. The negative electrode includes an electrically conductive extension.

Abstract: A DRAM includes first to third voltage lowering-circuits for lowering a power supply voltage supplied from the exterior and supplying the lowered voltage to an internal circuit. The first to third voltage lowering circuits are separately provided. The first voltage lowering circuit is a feedback type circuit having a P-channel MOS transistor. The first voltage lowering circuit is an exclusive circuit for creating a first potential by lowering thus power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a RAM signal input buffer, CAS signal input buffer and WE signal input buffer. The second voltage lowering circuit is a feedback type circuit having a P-channel MOS transistor or source follower type circuit having an N-channel MOS transistor.

Abstract: A memory cell circuit for a programmable logic device is provided that allows groups of memory cells to be powered down when one or more of the memory cells in a group is defective. Each memory cell contains two cross-coupled inverters for storing programming data for the programmable logic device. A first inverter in each cell is powered by a global power signal. A second inverter in each cell is powered by a power supply signal. The memory cells are powered down by taking the global power signal low while maintaining the power supply signal high. Because the second inverter remains active during power down, the memory cells may be shut down completely. The memory cell circuit may be used to set all of the memory cells to a known state upon power up.

Abstract: A method for saving and restoring data in the event of unwanted interruption of programming, the control logic unit of the memory controls writing of the data that would otherwise be lost and its address, in an appropriate backup memory location. To this end, the backup memory location is maintained erased, such as to allow immediate writing of the data and its address, in case of interruption of programming. To guarantee functioning even in the absence of an external supply, appropriate charge accumulators are provided, which can guarantee availability of a write-only cycle. As soon as a voltage drop is detected, the operations in progress are interrupted, and the backup operations for the data being programmed are activated; when the memory is switched on again, it is verified whether an interruption of the writing cycle has previously occurred, and thus the data saved can be recovered into the main memory.

Abstract: A power distribution unit that can detect system status includes: an optional line filter, a live power source for driving a I2C device, a power sensor which monitors system power status in connection with the I2C device through a I2C BUS, and a relay and on/off switch circuit which turns on/off system power in accordance with the I2C device through the I2C BUS.

Abstract: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Abstract: A technique allowing a terminal device located in a remote place to protect data existing on an information processing system and then control an electric source of the information processing system is provided. An information processing system according to the present invention includes a service processor for discriminating an order issued by a terminal device located in a remote place, an electric source control circuit for controlling connection or disconnection of an electric source in response to an electric source connection or disconnection order issued by the service processor, and an electric source unit for conducting connection or disconnection of an electric source in response to an electric source connection or disconnection order issued by the electric source control circuit.

Abstract: A battery module comprises at least one battery, and one or more memory sections for memorizing management information of the at least one battery at cutting operation of connection, when a connection between the at least one battery and at least one external device is cut, and the at least one battery and the memory sections are structured as one body.

Abstract: An automobile has an electronic device with a nonvolatile memory implementation. The electronic device includes non-programmable nonvolatile memory (ROM), volatile memory (RAM) and programmable nonvolatile memory (EEPROM). A controller (CPU) is coupled to and controls reads and writes to and from the ROM, RAM, and EEPROM. When the CPU detects a key-off event it calculates an error recovery code (checksum) for a data string stored in the RAM and stores the checksum and data into one of two memory locations in the EEPROM. The CPU will alternate between the two memory locations each cycle. When the CPU detects a key-on event it calculates the checksum for the data string stored in the RAM. If the data string is invalid or if validity of the EEPROM data cannot be confirmed, then the CPU copies a predetermined data string from the ROM to the RAM. If the CPU determines that the calculated KAM checksum does not equal the stored KAM checksum, then the CPU copies the EEPROM data string to the KAM.

Abstract: A power failure mode for a memory controller, such as a memory controller used in an input/output processor, which, when the memory controller has system power, refreshes a memory unit, such as an SDRAM memory unit, as required to maintain the memory image. In one embodiment, when a power failure occurs, the memory controller issues a self-refresh command to the memory, which has battery-backup power. A PCI reset signal may be used to determine when a power failure has occurred. The self-refresh command places the memory in a self-refresh mode, and a programmable logic device may be used to ensure that a clock enable signal input to the memory maintains the self-refresh mode. When system power returns, the memory controller resumes refreshing the memory.

Abstract: In a system using a clock synchronous type synchronous DRAM (SDRAM), when a power supply voltage monitoring circuit informs a timing circuit of a decrease in voltage from a main power supply, the timing circuit outputs a self refresh request signal to a CPU. In response to the self refresh request signal, the CPU outputs a clock enable signal synchronous with the system clock, and a self refresh transfer command signal, which is expressed by a combination of states of memory access control signals, to the SDRAM, so as to start up self refresh of the SDRAM. After the self refresh has been started up, the CPU outputs a clock enable mask signal that masks the clock enable signal to switch a clock enable signal to be supplied to the SDRAM from the clock enable signal output from the CPU to a voltage detection signal of a backup power supply. A reset signal then outputs a reset signal to transfer to backup operation.

Abstract: A semiconductor circuit, in particular for use in an integrated module, has at least one operational assembly with a drive circuit, such as a microprocessor, and a data memory. The semiconductor circuit has at least one initialization assembly for testing and/or for initializing the operational assembly. A disconnectable connecting line connects the operational assembly to the initialization assembly. In order to increase reliability, the initialization assembly is permanently disconnected from the operational assembly, by disconnecting the connecting lines, after the semiconductor circuit has been completed. In order to make it more difficult to reactivate the disconnected connecting lines, the semiconductor circuit has a potential line connected to the initialization assembly and/or to the operational assembly in a region of the connecting line.

Abstract: A non-contact type IC card includes a rectifier circuit for supplying a source voltage to respective circuits of an IC card based on the strength of radio waves received from a host computer. A reference voltage generating circuit generates a reference voltage. A comparison circuit compares the source voltage with the reference voltage. A control circuit prohibits the writing of data if the source voltage becomes less than the reference voltage.

Abstract: A non-volatile static random access memory device configured by adding a floating gate type metal oxide semiconductor device to an SRAM including a pair of access elements respectively switched on and off in accordance with the state of a signal on an address line and adapted to establish a data transfer path between memory cell and associated negative and positive data lines, and a pair of inverters respectively coupled to the access elements, thereby allowing the SRAM to exhibit non-volatile memory characteristics. The floating gate type MOS device has a silicon substrate, a tunneling oxide film formed over the silicon substrate, a floating gate formed on the tunneling oxide film, an oxide film formed over the floating gate, a control gate formed over the oxide film, and a source and a drain respectively formed in an upper surface of the silicon substrate at both sides of the control gate.

Abstract: To reduce both the noise level according to separation or short-circuitng of the electrical supply line of the sense amplifiers and the electrical supply line of the word line driving circuit and to effectively prevent destruction of the stored data in the nonselecteded memory cell. Electrical supply line (Vssw) of the power supply voltage with respect to word line driving circuit (SWD) and electrical supply line (Vssa) of power supply voltage with respect to sense amplifier driving circuit (SAD) are arranged separately in memory array area 2 (e.g., in the space in the row direction of memory array (SMAx,y)) and connected to shared electrical supply wiring (Vsso) within peripheral circuit area 3.

Abstract: In a semiconductor memory device, a plurality of output buffers, one for each output data bit, are powered by an internal voltage control circuit so as to provide high speed operation yet minimize power consumption. The internal voltage control circuit inclues multiple internal voltage generators. Responsive to the number of output buffers in use during a read operation, one or more of the voltage generators are activated to power the output buffers. Additionally, the current capacity of each of the individual voltage generators is controlled responsive to the number of output buffers in use during the read operation, so that bandwidth of the memory device is maximized but power is not wasted.

Abstract: A memory management method for use in a portable computer to prolong the lifetime of an internal battery in the portable computer. The portable computer includes a non-volatile memory storage device. When the portable terminal is operating from the internal battery or cell, a recording operation is performed in an unused memory region and an address value of data to be deleted is registered in a delete queue, rather than being deleted at that time. Later, when the portable terminal is connected to an external power source, data to be deleted is deleted all at the same time, thereby reducing power consumption of the battery or cell in the portable computer. This method utilizes less capacity of the cell and prolongs operation time of the internal battery cell. Data can be recovered when a user desires recovery of the data unless the data corresponding to the address values recorded in the delete queue has already been deleted.