Abstract: A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

Abstract: An improved Flash memory device with a synchronous interface has been detailed that enhances initialization of the Flash memory device. In the prior art, initialization of synchronous Flash memory requires the release of hardware signal line, RP#, or an initialization command, LCR, and a following initialization time wait period of 50 ?S to 100 ?S. The improved Flash memory device of the detailed invention begins initialization of internal values upon acquiring stable power. The initialization cycle of the detailed synchronous Flash memory loops and continues until a “STOP” command is received from the host controller and is immediately available for access. This allows the utilization of the detailed synchronous Flash memory in systems wherein the host controller cannot supply an initializing signal (RP# or LCR). The detailed synchronous Flash memory also allows for immediate availability of the Flash memory upon issuance of the “STOP” command allowing for a fast first access.

Abstract: A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.

Abstract: A ferroelectric memory device having a function of preventing destruction of data stored in an unselected memory cell. The ferroelectric memory device includes a protection circuit for protecting data in the unselected memory cell. The protection circuit is provided on an unselected-bitline-voltage supply line and an unselected-wordline-voltage supply line.

Abstract: A method and related apparatus for utilizing an ACPI to maintain data stored in a DRAM includes a processor, a DRAM, a south bridge chipset, and a rechargeable battery device. The south bridge chipset includes a system controller, a buffer, a memory controller, an integrated device electronics controller, and a data conversion circuit. The data conversion circuit converts a hard-disk access command transmitted from the system controller into a memory access command of the memory controller. The memory controller accesses the buffer and the DRAM by executing the memory access command. When the computer system enters a power-saving mode, a switch is turned on allowing the battery device to constantly self-refresh the DRAM for maintaining the data stored in the DRAM. When the computer system powers up, the switch is turned off and the battery device is recharged.

Abstract: A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically placed into the test mode at integrated circuit power-up from a power-down state. At power up, secure data is other than present within a secure data-path of the integrated circuit. Access is provided to the secure data path via a second data path coupled with the first secure data-path. Via the access path, data other than secure data is provided to the integrated circuit, the data for performing test functions of the integrated circuit operating in the test mode. Once data other than secure data is provided to first secure data path, the test mode is terminated and access via other than the secure ports is disabled. The test mode is only re-entered by powering down the integrated circuit and re-initialising it.

Abstract: A method for managing page-based data storage media such as flash media, a system that uses that method, and a computer-readable storage medium bearing code for implementing the method. New data are written to the storage medium in a manner that precludes corruption of old data if the writing of the new data is interrupted. Specifically, risk zones are defined, by identifying, for each page, the other pages whose data are put at risk of corruption if writing to the page is interrupted. A page, that otherwise would be the target of a write operation, is not written if any of the pages in its risk zone contain data that could be corrupted if the write operation is interrupted.

Abstract: When power stoppage of a main power supply is detected during a normal operation, a power controller switches a power supply for a DRAM from the main power supply to a battery power supply and makes an instruction signal for instruction a self-refresh mode to a memory controller active. In response to this, the memory controller changes a clock enable signal for the DRAM to a low level to establish the self-refresh mode of the DRAM, and, after, the self-refresh mode of the DRAM is established, supplying of power to the memory controller is stopped. The clock enable signal for the DRAM is maintained to the low level by pull-down resistance even when the supplying of power to the memory controller is stopped from a condition that the signal is changed to the low level in the self-refresh mode, thereby maintaining the self-refresh mode of the DRAM.

Abstract: A semiconductor device that quickly saves data stored in an area to which power is supplied intermittently. Power is supplied intermittently to a first area. Power is supplied continuously to a second area. A memory is located in the second area. A save circuit saves data used in the first area in the memory before the supply of power being stopped. A restoration circuit restores data which has been saved in the memory to a predetermined circuit in the first area. A power supply control circuit supplies power to the memory if data has been saved in the memory. Otherwise the power supply control circuit stops the supply of power to the memory.

Abstract: A semiconductor memory in which the protection state of data in a nonvolatile memory can be changed quickly and which provides sufficient security. A volatile protection state specification section controls the protection state of data in the nonvolatile memory. A nonvolatile initial state store section determines the initial state of the protection state specification section.

Abstract: A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program execution at the instruction of the program that was asserted for execution when the CPU was powered down. The CPU is permitted to power down frequently, even during execution of a program, and results in reduced average overall power consumption.

Abstract: A memory storage device includes a memory cell configurable to have at least a first conductive state and includes a first and second conductor each electrically coupled to the memory cell. A regulation circuit is configured to regulate a sense voltage on the second conductor to be independent of a current conducted through the first conductor when the memory cell is configured to have the first conductive state.

Abstract: A semiconductor memory device which includes an internal voltage generator circuit for adjusting an external power supply voltage and generating first and second internal power supply voltages. The first internal power supply voltage is supplied to a memory cell array via a first power supply line, and the second internal power supply voltage is supplied to a peripheral circuit via a second power supply line. A control circuit controls the internal voltage generator circuit so that the levels of the first and second internal power supply voltages vary depending on a mode of operation.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: A non-volatile semiconductor memory device includes a memory cell array having electrically erasable and programmable non-volatile memory cells, a part of the memory cell array being defined as a initial set-up data region for storing a plurality of initial set-up data that define memory operation conditions, data latch circuits for holding the initial set-up data read out from the initial set-up data region, a controller for controlling data program and erase operations for the memory cell array, and a clock generator for generating a clock signal that is used to define an operation timing of the controller, wherein the controller is configured to perform such an initial set-up operation that sequentially reads out the plurality of initial set-up data stored in the initial set-up data region and transfers them to the respective data latch circuits on receipt of power-on or a command input, the initial set-up operation being so performed as to read out a clock cycle adjustment data within the plurality of ini

Abstract: A method and system for upgrading a programmable battery unit in a mobile information handling system. The method and system make use of unique address words, checks, and comparisons stored in memory in order to allow upgrades in the battery unit. Non-reprogrammable section provides security in calculating checksums of addresses in the non-reprogrammable section and programmable section of memory.

Abstract: A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.

Abstract: When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.

Abstract: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Abstract: An apparatus and method for exclusively binding data to a data processing system. The logical binding apparatus of the present invention includes a detachable circuit device mounted within a system planar. Data to be bound within the system planar is stored in a memory device within the detachable circuit device. A battery signal is applied from the system planar to a binding pin on the detachable circuit device, wherein the binding pin is applied to the input of a binding latch. The binding latch remains in a reset state while the battery signal is applied. Upon removal of said binding signal from the binding pin, the binding latch is set thus signaling a processing unit within the detachable circuit device to remove the data from the memory device.

Abstract: Memory devices, refresh logic and approaches to selectively refresh each row of memory cells within a memory device depending on whether or not each is marked as having data to be preserved.

Abstract: The present invention relates to a data processing system comprising a processor (100), at least one data memory (132), at least one program memory (134) and a main bus (110), common to the data and program memories and connecting these memories to the processor, characterized in that at least one of the memories has a rapid-access mode and in that the device also comprises a distribution interface (120) between the main bus (110) and the memories in order to alternately put in communication, by means of the main bus, one from among the data memory and the program memory with the processor, in a so-called active-access mode, and to keep the other memory in a so-called passive-access mode allowing subsequent rapid access.

Abstract: A method for recording power failure time of a computer system. The computer system includes a power supply for generating a power signal, a memory for recording data, and a processor for processing data. The processor has a power port connected to the power supply for receiving the power signal, an input port for receiving a power good signal, and an output port connected to the memory for outputting the power failure time of the computer system to the memory. The recording method includes writing a power failure time and a check number into the memory when the input port of the processor does not receive the power good signal, and when the power signal has dropped below a threshold voltage.

Abstract: A ferroelectric memory device has a function of protecting data held in memory cells from an unexpected unstable power supply voltage generated when the power is turned on or off, or when reading or writing data, and a function of reducing power consumption during reading or writing of data. The ferroelectric memory device includes a short circuit which is operated when the power is turned on or off, or after reading or writing of data occurs. The short circuit short-circuits all of a voltage supply line for a selected word line, a voltage supply line for an unselected word line, a voltage supply line for a selected bit line and a voltage supply line for an unselected bit line, or short-circuits the voltage supply line for the unselected word line and the voltage supply line for the unselected bit line.

Abstract: In a nonvolatile memory such as flash memory where data is stored sector by sector, a method of overwriting a data sector is provided. The old data to be overwritten in a data sector along with its error detection code are initially saved to a backup region which is also in a non-volatile area. The old data in the data sector is then erased and new data along with its own error detection code are written into the same data sector where the old data was previously stored. When a power outage occurs during the overwrite process, error checking is performed to determine whether the data in the data sector is valid using the associated error detection code. Because the old data is saved in a non-volatile area, even if such unexpected power outage occurs during the overwrite process and the data in the data sector is determined to be invalid, at least the old data can be recovered from the non-volatile backup region which is not affected by the power outage.

Abstract: A semiconductor memory that can make the transition from a power-down state in a synchronous mode to an asynchronous mode without setting by a control register and that needs no extra circuits. A state selection section chooses, by selecting an existing internal signal the level of which changes in the power-down state or an existing internal signal the level of which does not change in the power-down state in accordance with a state selection signal inputted in advance and passing a signal selected to a synchronous/asynchronous mode setting section, whether the semiconductor memory should make the transition from the power-down state to a standby state in the synchronous mode or a standby state in the asynchronous mode. In accordance with the selection by the state selection section, the synchronous/asynchronous mode setting section generates a signal for causing the semiconductor memory to make the transition between the synchronous mode and the asynchronous mode.

Abstract: A memory device has a memory cell including a plurality of active devices, which can be switched on by an applied threshold voltage. A power line is coupled to at least one storage node by one of the active devices. One other of the active devices couples a virtual ground to the storage node. Potentials of the power line and the virtual ground cause the plurality of active devices to be selectively operated in near subthreshold and/or superthreshold regimes in accordance with a mode of operation.

Abstract: A method for operating a cache having a sleep mode is provided. The cache is located within a memory hierarchy of a computer system, and the method is comprised of receiving a first cache request, and servicing the first cache request. A sleep mode signal is asserted in response to completion of the servicing of the first cache request. Thereafter, a second cache request is received, and the sleep mode signal is deasserted in response to receiving the second cache request. Thereafter, the second cache request is serviced.

Abstract: In a semiconductor memory, during the rewriting of the signal stored in a memory cell, a displacement current is produced in the cell capacitor, which has to be supplied by an on-chip plate generator. If a very large number of cell capacitors are simultaneously subjected to charge reversal, as may be necessary in particular during power-up, then the plate generator cannot supply the required current within the predetermined time window. Therefore, the memory cells can assume undesired, incorrect values. It is proposed to precharge the memory cells to a predetermined potential during the switch-on of the operating voltage. Therefore, the displacement current is reduced overall, so that the plate generator can apply the required current for charging the memory cells. This measure prevents a change to the cell contents using simple measures.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells, and has a package configuration that is compatible with an SDRAM. The memory device includes a memory array, a programmable register circuitry to store protection data, and a voltage detector to determine if a memory power supply voltage drops below a predetermined level. Control circuitry is provided to program the register circuitry and prevent erase or write operations to the memory array in response to the voltage detector. In operation, the memory monitors a power supply voltage coupled to the memory, and prohibits write or erase operations from being performed if the supply voltage drops below a predetermined value.

Abstract: A memory card substrate includes a first solder pad assembly formed on a top edge of the memory card substrate. The first solder pad assembly has multiple first solder pads equally spaced from each other and multiple first gaps each sandwiched between two adjacent first solder pads. A second solder pad assembly is formed on a bottom edge of the memory card substrate and has multiple second solder pads equally spaced from each other and multiple second gaps each sandwiched between two adjacent second solder pads. Each first solder pad corresponds to one of the second gaps so that the first solder pads are alternately arranged on the top edge relative to the second solder pads on the bottom edge.

Abstract: A flash programmable microprocessor-based control module is operated in a manner to protect the integrity of event data stored in the programmable memory of the module while permitting authorized manufacturing and field alteration of the programmable memory with a Download and Execute routine. The Download and Execute routine is resident in a designated sector of the module's read-only memory, and download access to the module's random access memory after module manufacture has been completed is denied. During manufacture of the module, and during field programming of the controller prior to the writing of event data, the programmable memory may be externally altered by an authorized service tool by transferring the Download and Execute routine from read-only memory to random access memory for execution by the module's microprocessor, and downloading the new data or code over a data link coupling the service tool to the module.

Abstract: A method for controlling power for a semiconductor storage device and the semiconductor storage device are provided which enable power consumption to be greatly reduced in a standby state. The power control method uses an ultra-low power consumption mode in which power control can be exerted in the standby state. In the ultra-low power consumption mode, a burst self-refresh state, power-OFF state, and power-ON state are provided. In the burst self-refresh state, memory cells are refreshed in a centralized manner. In the power-OFF state, an internal power source circuit can be partially turned OFF. In the power-ON state, internal power sources having been partially turned OFF are turned ON. Therefore, it is possible to greatly reduce power consumption in the standby state.

Abstract: A memory cell includes at least one active device for selectively connecting a supply voltage node to a power line. The power line couples capacitive elements through the at least one active device to the supply voltage node to maintain a high state while accessing a storage node. The high state is provided by a boost created by the addition of the capacitive elements.

Abstract: A semiconductor memory device, which performs refreshing for data retention, provided with a power down mode that stops refreshing. The device includes a request generation circuit, which generates a refresh request signal with an oscillation signal generated by an oscillation circuit. The oscillation circuit stops generation of the oscillation signal in response to a power down mode entry signal. This reduces the current consumption of the semiconductor memory device.

Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.

Abstract: A transient rejecting system for protecting the state of a memory is described. The transient rejecting system includes a signal transfer circuit and a charge storage circuit coupled to at least one pin of a circuit. The signal transfer circuit receives a supply signal and determines when a transient event occurs. When a transient event occurs, the charge storage circuit provides a signal to the pin of the circuit maintaining the state of the memory prior to the transient. During normal operation, the charge storage circuit is charged, and the supply signal is provided to the pin of the memory circuit. P-channel FETs are used in the signal transfer circuit and allow for low voltage operation of the transient rejecting system.

Abstract: A non-volatile semiconductor storage device provided with a boost circuit for setting, for at least a certain period of time, a source line selectively connected to a memory cell to a negative potential, when reading out data from the memory cell is disclosed.

Abstract: The invention relates to an electronic assembly having a non-volatile memory device with a controllable write protection feature and a switching configuration for generating a write protection signal from potentials at the supply terminals of the electronic assembly.

Abstract: The application of a nonactive level to a word line in a semiconductor memory is controlled by a precharge control. In order to initiate the precharge operation, a pair of reference bit lines are provided to which initially different potentials can be fed, which are subsequently amplified by a reference sense amplifier. The potential of one of the reference bit lines is amplified in a differential amplifier in order thereupon to cause a control device to initiate the precharge operation.

Abstract: A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.

Abstract: A method of adaptively writing magnetic memory cells of a MRAM is disclosed according to an embodiment of the present invention. The method comprises providing a logical data block of a memory array having magnetic memory cells, each magnetic memory cell in a known initial state and each magnetic memory cell configured along an easy-axis magnetic field generating conductor and writing to the magnetic memory cells using a predefined minimum current level. The method may further comprise sensing the magnetic memory cells to determine if data has been successfully written, incrementing the current level if writing was unsuccessful and repeating above.

Abstract: A semiconductor memory device is provided with a power supply circuit. The power supply circuit includes a reference voltage generating circuit which generates a first reference voltage, a booster circuit which generates a first internal power supply voltage by boosting an external power supply voltage using the first reference voltage, another reference voltage generating circuit which generates a second reference voltage, and a VDC circuit which generates a second internal power supply voltage by down-converting the first internal power supply voltage to a voltage level of the second reference voltage. The generated second internal power supply voltage is supplied to a DLL, and the DLL generates a periodic signal having a phase corresponding to the voltage level of the second internal power supply voltage.

Abstract: A semiconductor memory module with a changeover device by which an internal voltage supply circuit can be switched on or off in a simple manner. The changeover device has two evaluation circuits, one evaluation circuit being used for switching on the voltage supply and the second evaluation circuit being used for switching off the voltage supply. In this way, the two evaluation circuits can be optimized with regard to functionality, circuit layout and current consumption.

Abstract: A non-volatile semiconductor memory device includes a memory cell array having electrically erasable and programmable non-volatile memory cells, a part of the memory cell array being defined as a initial set-up data region for storing a plurality of initial set-up data that define memory operation conditions, data latch circuits for holding the initial set-up data read out from the initial set-up data region, a controller for controlling data program and erase operations for the memory cell array, and a clock generator for generating a clock signal that is used to define an operation timing of the controller, wherein the controller is configured to perform such an initial set-up operation that sequentially reads out the plurality of initial set-up data stored in the initial set-up data region and transfers them to the respective data latch circuits on receipt of power-on or a command input, the initial set-up operation being so performed as to read out a clock cycle adjustment data within the plurality of ini

Abstract: A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.

Abstract: A power-up control circuit has three components including a normal power-supply voltage level detection section, a special command section for detecting a deep-sleep enable input signal, and an output driver section that logically combines the output signal of the normal power-supply voltage level detection section and the special command detecting section to provide an improved, combined power-up control signal CPWRUP. The combined power-up control signal CPWRUP signal is temporarily brought to a LOW state for a predetermined period of time immediately after the end of a power-saving mode of operation, such as a deep-sleep mode of operation for a memory device. The LOW state of the combined power-up control signal CPWRUP output signal allows all internal circuitry to be returned to their initial states that are the same as those obtained after a normal power-up sequence, even though the external voltage level stays at its normal level.

Abstract: A hold-up power supply for flash memory systems is provided. The hold-up power supply provides the flash memory with the power needed to temporarily operate when a power loss exists. This allows the flash memory system to complete any erasures and writes, and thus allows it to shut down gracefully. The hold-up power supply detects when a power loss on a power supply bus is occurring and supplies the power needed for the flash memory system to temporally operate. The hold-up power supply stores power in at least one capacitor. During normal operation, power from a high voltage supply bus is used to charge the storage capacitors. When a power supply loss is detected, the power supply bus is disconnected from the flash memory system. A hold-up controller controls the power flow from the storage capacitors to the flash memory system. The hold-up controller uses feedback to assure that the proper voltage is provided from the storage capacitors to the flash memory system.

Abstract: When a power supply detection unit 5 detects an OFF command of a battery 2, a DRAM 1 is changed to a self-refresh mode. Then, power is fed from a backup power supply 4 to the DRAM 1.

Abstract: A semiconductor memory device is organized in such a way that undesirable interference and cross-coupling between various signals generated during operation of the device is minimized. The semiconductor memory device comprises an array of rows and columns of memory cells organized logically and physically into a plurality of sub-arrays. Within each sub-array, the memory cells are organized logically and physically into a plurality of dependent, interleaved banks of memory cells. The banks of memory cells, in turn, each comprise a plurality of memory cores comprising a plurality of memory cells. The memory cores are arranged in such a way as to define a plurality of substantially elongate, orthogonal “stripes” therebetween. Row decoder circuitry for selecting a specified row of memory cells is disposed along the stripes extending in a first direction.