Standby Power Patents (Class 365/229)
  • Patent number: 11322187
    Abstract: The present application discloses a protection circuit for a memory in a display panel and a display panel. The circuit comprises a timing controller, a memory, a power circuit, and a switching circuit. Instead of having a computer provide a write protection signal to the memory to limit data in the memory from being overwritten, the power circuit provides a stable and reliable write protection signal to the memory, and then the timing controller controls the switching circuit to be turned on for grounding the write protection signal of the memory only when an instruction to write data to the memory is received.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 3, 2022
    Assignee: HKC Corporation Limited
    Inventor: Huailiang He
  • Patent number: 11301324
    Abstract: A server computer is configured to write a first copy of a block of data to a first namespace on a first non-volatile memory-based cache drive and a second copy of the block of data to a RAID controller for de-staging of the data to hard disk drives of a RAID array. Acknowledgment of hardening of the data on the hard disk drives initiates purging of the first copy of the block of data from the cache drive. High availability is enabled by writing a third copy of the block of data to a second server to store the block of data in a second namespace on a second non-volatile memory-based cache drive. Restoring of data after power loss accesses the data on the first non-volatile memory-based cache drive.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: April 12, 2022
    Assignee: SANMINA CORPORATION
    Inventors: Kais Belgaied, Richard Elling, Franz Michael Schuette
  • Patent number: 11275663
    Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 ?S) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Nimrod Angel, Ameya Ambardekar, Sapumal Wijeratne, Vikas Vij, Tod Schiff, Alexander Uan-Zo-Li
  • Patent number: 11226897
    Abstract: Disclosed herein are techniques for implementing hybrid memory modules with improved inter-memory data transmission paths. The claimed embodiments address the problem of implementing a hybrid memory module that exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices) during data backup and data restore operations. Some embodiments are directed to approaches for providing a direct data transmission path coupling a non-volatile memory controller and the DRAM devices to transmit data between the DRAM devices and the flash devices. In one or more embodiments, the DRAM devices can be port switched devices, with a first port coupled to the data buffers and a second port coupled to the direct data transmission path. Further, in one or more embodiments, such data buffers can be disabled when transmitting data between the DRAM devices and the flash devices.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: January 18, 2022
    Assignee: Rambus Inc.
    Inventor: Aws Shallal
  • Patent number: 11202262
    Abstract: In some embodiments, a method of reducing power consumption by a mobile telephone includes (1) providing a mobile telephone including a processor, an antenna, and a memory having computer program code; and (2) employing the processor of the mobile telephone and computer program code to (a) determine if the mobile telephone is in a vehicle; and (b) in response to the mobile telephone being in a vehicle, initiate a reduced power sequence in which the mobile telephone repeatedly turns off transmission by the antenna of the mobile telephone for a first time period and turns on transmission by the antenna of the mobile telephone for a second time period. Numerous other aspects are provided.
    Type: Grant
    Filed: December 30, 2018
    Date of Patent: December 14, 2021
    Assignee: Dugan Patents, LLC
    Inventors: Brian M. Dugan, Valerie G. Dugan
  • Patent number: 11188263
    Abstract: The present disclosure relates to a method for data writing, a device and a storage medium, wherein the method includes acquiring a first data to be written and saving a plurality of sub-blocks of the first data in one or more designated aggregated queue of multiple aggregated queues according to an aggregation strategy; performing, in each designated aggregated queue, data interception on a plurality of sub-blocks in a current queue to obtain a second data to be written; and writing the second data in a storage device. The data distribution written in the storage device becomes more ideal by a multi-queue aggregation, and thus the method for data writing according to the embodiments of the present disclosure can reduce the time consumed in reading the storage device effectively.
    Type: Grant
    Filed: January 18, 2020
    Date of Patent: November 30, 2021
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Lei Li, Ying Chu, Qian Cheng, Qun Zhao
  • Patent number: 10978111
    Abstract: In an aspect of the disclosure, a reference voltage holding circuit is provided. The reference voltage holding circuit is for maintaining a sense amplifier reference voltage provided by a sense amplifier reference circuit, and the reference voltage holding circuit includes: a reference voltage generating circuit configured to provide a bias reference voltage; a current generating circuit electrically coupled to the reference voltage generating circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current mirror circuit and configured to provide for the standby bias current and to maintain the standby bias voltage which drives the sense amplifier reference voltage when reference voltage holding circuit operates under a standby operation and approximates the sense amplifier reference voltage as long as the sense amplifier reference voltage remains enabled.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Poongyeub Lee, Ting-Kuo Yen
  • Patent number: 10908825
    Abstract: An embodiment of a semiconductor apparatus may include technology to determine a persistent region and a non-persistent region of a volatile media based on an amount of power available from one or more backup power sources, and periodically backup only the non-persistent region of the volatile media to a non-volatile media. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Peng Li, Sanjeev Trika, Jawad Khan, Myron Loewen
  • Patent number: 10877541
    Abstract: A system can comprise a memory device and sequencing circuitry configured to provide enable signals to a number of voltage regulators in association with providing sequenced power signals to the memory device. The system can include voltage threshold detection circuitry configured to: detect primary supply voltage events; and responsive to detecting a primary supply voltage event, deassert a timer enable signal provided to timing circuitry. The timing circuitry is configured to, responsive to the deassertion of the timer enable signal: deassert a primary enable signal provided to the sequencing circuitry; and maintain the primary enable signal in a deasserted state for a particular amount of time prior to reasserting the primary enable signal.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Keith A. Benjamin, Thomas Dougherty
  • Patent number: 10861506
    Abstract: Examples disclosed herein relate to dual in-line memory module (DIMM) battery backup. Some examples disclosed herein describe systems that include a backup power source pluggable into a DIMM slot. The backup power source may include a plurality of battery cells electrically connected to a DIMM to provide backup power to the DIMM. Each of the plurality of battery cells supporting the DIMM may be electrically connected to a DC-to-DC converter in series and to each other in parallel.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 8, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Hai Nguyen, Daniel Hsieh, Abhishek Banerjee
  • Patent number: 10839862
    Abstract: An indication of a power loss can be received at a cross point array memory dual in-line memory module (DIMM) operation component of a memory sub-system. The cross point array memory DIMM operation component includes a volatile memory component and a non-volatile cross point array memory component. In response to receiving the indication of the power loss, a type of write operation for the non-volatile cross point array memory component of the cross point array memory DIMM operation component is determined based on a characteristic of the memory sub-system. Data stored at the volatile memory component of the cross point array memory DIMM operation component is retrieved and written to the non-volatile cross point array memory component of the cross point array memory DIMM operation component by using the determined type of write operation.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Edward McGlaughlin, Ying Yu Tai, Samir Mittal
  • Patent number: 10818371
    Abstract: A data storage device includes a memory controller and a memory device. The memory device includes a current memory block. The memory controller is coupled to the memory device and configured to access the memory device. In response to detection of a sudden power-off that has occurred before the memory device is powered up, the memory controller is configured to find a last valid page and a last valid word line corresponding to the last valid page by scanning a plurality of pages in the current memory block, and determine whether to use one or more empty pages belonging to a word line group that is the same as that of the last valid page according to a read count and an erase count of the current memory block.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Wen-Sheng Lin
  • Patent number: 10790669
    Abstract: A power saving control device includes: an acquirer that acquires a power saving request; and a controller that determines whether or not power saving control for reducing a power consumption of a load device is to be performed in response to the power saving request, and that, when determining that the power saving control is to be performed, performs the power saving control. When the load device consumes power, the controller determines that the power saving control is not to be performed under a condition that no power flows from a power system into a facility in which the load device is installed, the condition being one of one or more conditions.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 29, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akira Baba, Haruka Nakasone
  • Patent number: 10678924
    Abstract: Various features relate to the providing Software-Resilient User Privacy within smartphones or other devices by storing and processing all pertinent values needed for user privacy—such as security keys and access attempt counters—in hardware, such as within a System-on-a-Chip (SoC) processor formed on an integrated circuit (IC). For example, an on-die ephemeral Volatile Memory (eVM) device may be employed for storing access attempt counters or other parameters used to control malicious attack countermeasures. In one example, the eVM employs static random-access memory (SRAM) formed on the die and exploits capacitive remanence to recover stored counter values even if power is disconnected, then reconnected. On-chip NVM may be used for permanent storage of other privacy values, such as a device-unique secret key that is generated locally on the device and not known to the chip vendor, the device Original Equipment Manufacturer (OEM)) or the owner/user of the device.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: June 9, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Vincent Pierre Le Roy, Ivan McLean
  • Patent number: 10678467
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a persistent memory system communicatively coupled to the processor, the persistent memory system comprising one or more persistent memory modules and a plurality of targeted save registers, each targeted save register associated with a respective portion of the persistent memory system, and each targeted save register having a value indicative of how save operations from volatile memory to non-volatile memory of the persistent memory system are to be performed with respect to the respective portion of the persistent memory system.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: June 9, 2020
    Assignee: Dell Products L.P.
    Inventors: Vadhiraj Sankaranarayanan, Krishna Pradyumna Kakarla, Balaji Bapu Gururaja Rao, Elie Antoun Jreij
  • Patent number: 10635586
    Abstract: Disclosed herein are techniques for implementing hybrid memory modules with improved inter-memory data transmission paths. The claimed embodiments address the problem of implementing a hybrid memory module that exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices) during data backup and data restore operations. Some embodiments are directed to approaches for providing a direct data transmission path coupling a non-volatile memory controller and the DRAM devices to transmit data between the DRAM devices and the flash devices. In one or more embodiments, the DRAM devices can be port switched devices, with a first port coupled to the data buffers and a second port coupled to the direct data transmission path. Further, in one or more embodiments, such data buffers can be disabled when transmitting data between the DRAM devices and the flash devices.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: April 28, 2020
    Assignee: Rambus Inc
    Inventor: Aws Shallal
  • Patent number: 10551892
    Abstract: Approaches, techniques, and mechanisms are disclosed for a centralized backup power support system that improves testability of non-volatile dual in-line memory modules (NVDIMM) on Automatic Test Equipment (ATE) testers and in-system tests. An NVDIMM includes both volatile memories and non-volatile memories. According to an embodiment, a compact backup power distribution board is powered with an external power supply with an individual protection circuit. The backup power distribution board has an unlimited energy capacity for any density of NVDIMM and zero charge waiting time. According to an embodiment, instead of using an electric double-layer capacitor (EDLC) to support backup power, a resistor is used instead of an EDLC on each backup power module. There is no charging time when the backup power module does not have EDLC cells, resulting in significant reduction in test time and production cost and increase in production output.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: February 4, 2020
    Assignee: SMART Modular Technologies, Inc.
    Inventor: Jinying Shen
  • Patent number: 10497404
    Abstract: A clamping circuit includes an energy storage section and a pulse generator to generate a pulse in which the energy storage section stores energy from a main power supply.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: December 3, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Eugene Mikhaylovich Dvoskin, Noel D. Scott
  • Patent number: 10433776
    Abstract: A pulse oximeter may reduce power consumption in the absence of overriding conditions. Various sampling mechanisms may be used individually or in combination. Various parameters may be monitored to trigger or override a reduced power consumption state. In this manner, a pulse oximeter can lower power consumption without sacrificing performance during, for example, high noise conditions or oxygen desaturations.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: October 8, 2019
    Assignee: MASIMO CORPORATION
    Inventor: Ammar Al-Ali
  • Patent number: 10325474
    Abstract: Embodiments of the present disclosure relate to a solution for fault unit indication. In some embodiments, there is provided a method for positioning a fault unit. The method comprises supplying power to a controller and a light emitting diode (LED) circuit by a battery module, wherein the LED circuit includes a plurality of LEDs associated with a plurality of units. The method further comprises transmitting a trigger signal to the controller by the battery module in response to receiving a control signal for triggering positioning, such that an LED of the plurality of LEDs associated with a fault unit is turned on.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: June 18, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Jesse Cheng, Haifang Zhai, Wei Shu, Sean Xu, Sandburg Hu
  • Patent number: 10289074
    Abstract: A controller teaches a teaching point of a slave axis corresponding to a master axis so as to perform a synchronous operation. The controller calculates a teaching range based on one moving speed pattern selected from a plurality of moving speed patterns of the master axis which are preliminarily registered, a preliminarily-set allowable speed in an operation of the slave axis, and a calculated teaching range, in which teaching can be performed, of a following teaching point, so as to display the teaching range on a display device.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 14, 2019
    Assignee: FANUC CORPORATION
    Inventor: Takehiro Yamaguchi
  • Patent number: 10241702
    Abstract: A sequential delay mechanism is provided for a memory subsystem of a host system. A first independent SAVE region of NVDIMMs of the memory subsystem is configured to start a memory SAVE immediately upon receiving a SAVE signal from the host system, and other independent SAVE regions of the NVDIMMs are configured to implement the delay mechanism. A memory SAVE to the NVDIMMs is activated immediately in the first independent SAVE region when the SAVE signal is received, and the other independent SAVE regions sequentially delay their activation of the memory SAVE.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 26, 2019
    Assignee: AgigA Tech Inc.
    Inventors: Ronald H Sartore, Torry J Steed
  • Patent number: 10241727
    Abstract: Disclosed herein are techniques for implementing hybrid memory modules with improved inter-memory data transmission paths. The claimed embodiments address the problem of implementing a hybrid memory module that exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices) during data backup and data restore operations. Some embodiments are directed to approaches for providing a direct data transmission path coupling a non-volatile memory controller and the DRAM devices to transmit data between the DRAM devices and the flash devices. In one or more embodiments, the DRAM devices can be port switched devices, with a first port coupled to the data buffers and a second port coupled to the direct data transmission path. Further, in one or more embodiments, such data buffers can be disabled when transmitting data between the DRAM devices and the flash devices.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: March 26, 2019
    Assignee: Rambus Inc.
    Inventor: Aws Shallal
  • Patent number: 10234929
    Abstract: A first control apparatus includes a first memory unit including a local cache, a first power supply that supplies electric power to the first memory unit, and a control unit. The control unit controls a write into a memory device by a write-back method, using the local cache. The control unit mirrors data of the local cache in a mirror cache of a second control apparatus. The control unit determines whether the mirror cache is included in a second memory unit that receives electric power from a second power supply of the second control apparatus, upon detecting an abnormal state of a battery for supplying electric power to the second memory unit in case of power outage of the second power supply. The second memory unit switches write control for the memory device to a write-through method, when the second memory unit includes the mirror cache.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Hidefumi Kobayashi, Satoshi Yazawa, Atsushi Igashira, Wataru Iizuka, Motohiro Sakai, Akihito Kobayashi, Shinichiro Matsumura, Kenji Kobayashi
  • Patent number: 10216255
    Abstract: The invention relates to a power distribution system, such as a Power over Ethernet power distribution system. A powered device provides a pulse, such as a Maintain Power Signature, when in standby such that a power providing device remains providing power to it. To increase energy efficiency, the MPS can be cycled (60 ms pulse every 300 ms to 400 ms) according to the IEEE802.3af/at standards. By introducing a controllable switch, for electrically decoupling at least part of the powered device from the power providing device, and a pulse generator, the MPS can be generated in a more energy efficient way and/or can be shortened (e.g. to 5 ms). As an example, the controllable switch can decouple the bulk capacitor of the powered device during MPS generation to prevent the bulk capacitor from filtering out the MPS.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: February 26, 2019
    Assignee: PHILIPS LIGHTING HOLDING B.V.
    Inventors: Lennart Yseboodt, Matthias Wendt
  • Patent number: 10204054
    Abstract: Implementations disclosed herein provide a method comprising detecting a power supply status, determining a media cache cleaning scheme based on the detected power supply status, and performing the determined cleaning scheme until a predetermined threshold is reached.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: February 12, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Loo Shing Tan, WenXiang Xie, Aung Khant, Feng Shen
  • Patent number: 10198300
    Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: February 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Briana E. Foxworth, Saravanan Sethuraman, Kevin M. Mcilvain, Lucas W. Mulkey, Adam J. McPadden
  • Patent number: 10031571
    Abstract: In accordance with embodiments of the present disclosure, a method for power loss protection of one or more storage resources may include receiving information from each of the one or more storage resources regarding power loss protection capabilities of such storage resource. The method may also include based on the information, repurposing, for each power loss protection capable storage resource, a communications channel between a logic device and such power loss protection capable storage resource for transmission of a respective early power-off warning signal for such power loss protection capable storage resource. The method may further include in response to a power event of a power supply unit for providing electrical energy to the one or more storage resources, asserting for each power loss protection capable storage resource its respective early power-off warning signal.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: July 24, 2018
    Assignee: Dell Products L.P.
    Inventors: Michael J. Stumpf, Timothy M. Lambert, Frank Widjaja Yu
  • Patent number: 10007611
    Abstract: Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer program product for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a transfer logic used in a power-loss save of the write cache. The one or more operating parameters include an instance-specific process speed of the transfer logic which is retrieved as bin data. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 26, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kirk D. Lamb
  • Patent number: 9965289
    Abstract: In accordance with embodiments of the present disclosure, a method may include, during boot of an information handling system, determining a first amount of energy required by the information handling system to flush a cache integral to the information handling system to memory integral to the information handling system in response to a power loss of one or more power supplies for supplying electrical energy to the information handling system, determining whether a second amount of energy available for hold-up of one or more power supplies in response to the power loss exceeds the first amount of energy, and responsive to determining whether the second amount of energy exceeds the first amount of energy, configuring the cache.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: May 8, 2018
    Assignee: Dell Products L.P.
    Inventors: John Erven Jenne, Stuart Allen Berke, Dit Charoen
  • Patent number: 9933843
    Abstract: A method for reducing a need for power in a backup mode of operation in a data center includes receiving a first alert from an uninterruptible power supply indicating that the uninterruptible power supply is operating in a first mode, wherein the first mode includes deriving power from a stored energy source, identifying at least one host server configured to receive power from the uninterruptible power supply in the first mode, suspending execution of at least one virtual machine on the at least one host server, receiving a second alert from the uninterruptible power supply indicating that the uninterruptible power supply is operating in a second mode, wherein the second mode includes deriving power from one of a mains power source and a generator, and resuming execution of the at least one virtual machine.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 3, 2018
    Assignee: SCHNEIDER ELECTRIC IT CORPORATION
    Inventors: Torben Nielsen, Flemming Johansen, Jens Engsted Kiib, Mikkel Dalgas, Kresten Peter Vester
  • Patent number: 9921762
    Abstract: Data stored in a volatile memory subsystem is backed up redundantly into first and second channels of a non-volatile memory subsystem. The data is retrieved from the volatile memory subsystem upon detection of a trigger condition indicative of real or imminent power loss or reduction and multiple copies are stored in dedicated non-volatile memory channels. The stored copies may be error checked and corrected, and re-written if necessary. The redundantly backed up data can be subsequently retrieved from the non-volatile memory subsystem, error-corrected, and an error-free copy communicated to the volatile memory subsystem.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: March 20, 2018
    Assignee: Netlist, Inc.
    Inventors: Mike Hossein Amidi, Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
  • Patent number: 9848806
    Abstract: A pulse oximeter may reduce power consumption in the absence of overriding conditions. Various sampling mechanisms may be used individually or in combination. Various parameters may be monitored to trigger or override a reduced power consumption state. In this manner, a pulse oximeter can lower power consumption without sacrificing performance during, for example, high noise conditions or oxygen desaturations.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: December 26, 2017
    Assignee: MASIMO CORPORATION
    Inventor: Ammar Al-Ali
  • Patent number: 9830954
    Abstract: A method and apparatus for dynamic power management of memories. In one embodiment of the invention, the power consumption of the memories is reduced based on the operating state of the memories. For example, in one embodiment of the invention, the power supply to the memories is reduced when the memories are in an inactive state by reducing and/or turning off the input voltage(s) to the memories. In one embodiment of the invention, the processing unit dynamically changes the strength of the On-Die Termination pull-up/pull-down resistance based on the memory operating mode, memory voltage, and memory temperature.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Lance E. Hacking, Hee-Jun Park
  • Patent number: 9817610
    Abstract: An apparatus forms a memory system that is physically populated into a host. In a powered-on state, the apparatus logically connects to the host through a host memory controller configured to receive host-initiated commands. The memory system includes a command buffer coupled to the host memory controller to receive the host-initiated commands. The memory system comprises both volatile memory (e.g., RAM) and non-volatile memory (e.g., FLASH). A non-volatile memory controller (NVC) is coupled to the volatile memory, and is also coupled to the non-volatile memory. A command sequence processor that is co-resident with the NVC responds to a trigger signal by logically disconnecting from the host, then dispatching command sequences that perform successive read/write operations between the volatile memory and the non-volatile memory. The successive read/write operations are performed even when the host is in a powered-down state.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: November 14, 2017
    Assignee: INPHI CORPORATION
    Inventors: Aws Shallal, Dan Kunkel
  • Patent number: 9786365
    Abstract: An integrated circuit according to an embodiment includes: a first wiring line group including at least three first wiring lines; a second wiring line group including second wiring lines; first resistive change elements each including a first and second terminals, and a first resistive change layer; a first select circuit including first input terminals connected to the second wiring lines and a first output terminal, the first select circuit selecting a first input terminal from the first input terminals, and output information from the first output terminal; a third and fourth wiring lines; and a second select circuit selecting two first wiring lines from the first wiring line group, connecting one of the selected two first wiring lines to the third wiring line, and connecting the other one of the selected two first wiring lines to the fourth wiring line.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 10, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Koichiro Zaitsu
  • Patent number: 9767030
    Abstract: Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer implemented method for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a component used in a power-loss save of the write cache. The component is selected from the group consisting of an energy storage element, a non-volatile memory, and a transfer logic. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: September 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kirk D. Lamb
  • Patent number: 9720389
    Abstract: Context recognition methods and apparatus are provided for an application processor and a micro control unit. It is determined whether an operation switch condition for switching to a sleep mode is satisfied. A request for execution of a context recognition function is sent to a micro control unit, when the operation switch condition is satisfied. The application processor switches to the sleep mode, when the context recognition function is executed by the micro control unit. The micro control unit collects sensor data at previously stored time intervals, and previously stored state information is updated based on the sensor data.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hyun-Su Hong, Jae-Myeon Lee, Ji-Heon Oh, Kyong-Ha Park, Sung-Min Park
  • Patent number: 9652377
    Abstract: According to one embodiment, the memory system includes a nonvolatile semiconductor memory, a data buffer, a volatile memory for storing a management table uniquely associates the user data with an address of the physical storage region of nonvolatile semiconductor memory, a controller that carries out a force quit process for writing the user data stored in a data buffer, the management table stored in volatile memory into the nonvolatile semiconductor memory, and a storage battery. The controller starts the force quit process prior to the power supply of the internal power supply regulator is switched from an external power supply to the storage battery.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: May 16, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kimura, Hiroki Matsushita
  • Patent number: 9619380
    Abstract: A data writing method for a memory storage apparatus having a first buffer memory, a second buffer memory and a rewritable non-volatile memory module is provided, and the transmission bandwidth of the first buffer memory is larger than the transmission bandwidth of the second buffer memory. The method includes: receiving a write command and first data thereof; determining whether the first data belongs to the successive big data; if the first data belongs to the successive big data, temporarily storing the first data into a first data buffer area of the first buffer memory, writing the first write data from the first data buffer area to the rewritable non-volatile memory module; and if the first data does not belongs to the successive big data, temporarily storing the first data into a second data buffer area of the second buffer memory.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 11, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9583974
    Abstract: An uninterruptible power supply system for supplying electrical power to an electrical apparatus. The system includes an alternating current (AC) power source providing AC power and a direct current (DC) power source providing DC power. The system also includes a power selector system having a power selector for selecting AC power or DC power for powering the electrical apparatus. The power selector system has a sensor for determining if AC power is acceptable for powering the electrical apparatus. In addition, the system includes a power automation system for charging the DC power source and a power management module for controlling the power selector system and the power automation system. The power management module switches to DC power for powering the electrical apparatus when the AC power is unacceptable. When DC power is used, DC power is provided directly to the electrical apparatus without converting the DC power.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 28, 2017
    Inventor: Asif Ahsanullah
  • Patent number: 9563381
    Abstract: A method of controlling volatile memory (VM) and VM controller operatively connectable to VM. The method includes: intercepting reset signal intended to cause reset of, at least, VM; assessing transfer-related (TR) state related to the VM; blocking the intercepted reset signal from reaching VM if the assessed TR state does not meet predefined criterion, and transferring the reset signal to VM if the assessed TR state meets the predefined criterion. The VM controller is configured to: receive a reset signal originating in computer system and intended to cause reset of, at least, the VM; detect if the VM has been powered-up during a predetermined timeframe prior to the receipt of the reset signal; and block the received reset signal from reaching the VM if the VM powering-up has not been detected and transfer the reset signal to the VM if the VM powering-up has been detected.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: February 7, 2017
    Assignee: STORONE LTD.
    Inventor: Raz Gordon
  • Patent number: 9529547
    Abstract: A memory device comprising a memory controller and a homogeneous memory accessible by the memory controller, wherein the homogeneous memory is divided by the memory controller in a first memory partition and a second memory partition, wherein the first memory partition is allocated to a first type of information comprising user data and ECC data that are arranged interleaved with the user data, and wherein the second memory partition is allocated to a second type of information comprising further user data.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: December 27, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Michael Staudenmaier, Vincent Aubineau, Iosef E. Martinez-Pelayo
  • Patent number: 9519544
    Abstract: A memory module includes an emergency power supply block, a volatile memory, a nonvolatile memory, and a control block configured to control data of the volatile memory to be backed up in the nonvolatile memory, by using a power supplied from the emergency power supply block, upon a power failure, and control the data of the volatile memory to be recovered, by using data backed up in the nonvolatile memory, upon a power recovery, wherein the control block controls the data of the volatile memory not to be backed up while controlling the data of the volatile memory to be recovered, even upon the power failure.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: December 13, 2016
    Assignee: SK Hynix Inc.
    Inventor: Choung-Ki Song
  • Patent number: 9492605
    Abstract: An infusion pump assembly includes a reservoir assembly configured to contain an infusible fluid. A motor assembly is configured to act upon the reservoir assembly and dispense at least a portion of the infusible fluid contained within the reservoir assembly. Processing logic is configured to control the motor assembly. A primary power supply is configured to provide primary electrical energy to at least a portion of the processing logic. A backup power supply is configured to provide backup electrical energy to the at least a portion of the processing logic in the event that the primary power supply fails to provide the primary electrical energy to the at least a portion of the processing logic.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: November 15, 2016
    Assignee: DEKA Products Limited Partnership
    Inventor: Marc A. Mandro
  • Patent number: 9484917
    Abstract: Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply; and a circuit to operate with the second power supply, wherein the clamp is operable to adjust the second power supply when the apparatus enters a low power mode.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: November 1, 2016
    Assignee: Intel Corporation
    Inventors: Arijit Raychowdhury, Charles Augustine, James W. Tschanz, Vivek K. De
  • Patent number: 9448610
    Abstract: A vehicle mount computer having a configurable behavior controlled by a vehicle's ignition switch. A user can configure the computer to perform an action, switch modes, or execute a software application in response to the ignition switch being pressed or the position of the ignition switch being adjusted. For example, the computer can be configured to switch to a standby mode or hibernation mode, shutdown, prompt the user to select an action, or do nothing in response to the ignition switch being placed in an off position. The ignition switch can be electrically coupled to an input of the computer so that the computer's operating system or another application can monitor the status of the ignition switch. The operating system or application can cause the computer to perform the configured response upon detecting a change in the ignition switch's position or an actuation of the ignition switch.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: September 20, 2016
    Assignee: EMS Technologies, Inc.
    Inventors: Brett A. Davis, Terry Jendon, Michael W. Holladay, Alison E. Veazey
  • Patent number: 9436612
    Abstract: Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer implemented method for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a component used in a power-loss save of the write cache. The component is selected from the group consisting of an energy storage element, a non-volatile memory, and a transfer logic. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: September 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kirk D. Lamb
  • Patent number: 9431067
    Abstract: The present invention provides a volatile memory backup system including an all-solid-state battery. The backup system includes a volatile memory, a nonvolatile memory connected to the volatile memory so as to transfer data therebetween, an all-solid-state battery connected to the volatile memory and the nonvolatile memory, the battery continuously or intermittently supplying a current to the volatile memory during a power failure to retain data in the volatile memory, and a controller connected in parallel with the battery, the controller intermittently supplying a peak current to the volatile memory during the power failure and intermittently transferring divided volumes of data in the volatile memory to the nonvolatile memory by the peak current and a current from the battery temporarily increased in association with the peak current to store the data in the nonvolatile memory, thereby gradually accumulating the data in the volatile memory into the nonvolatile memory.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 30, 2016
    Assignee: NGK Insulators, Ltd.
    Inventors: Iwao Ohwada, Kenshin Kitoh
  • Patent number: 9390767
    Abstract: A memory module is provided comprising a substrate having an interface to a host system, volatile memory, non-volatile memory, and a logic device. The logic device may receive the indicator of an external triggering event and copies data from the volatile memory devices to the non-volatile memory devices upon receipt of such indicator. When the indicator of the triggering event has cleared, the logic device restores the data from the non-volatile to the volatile memory devices. The memory module may include a passive backup power source (e.g., super-capacitor) that is charged by an external power source and temporarily provides power to the memory module to copy the data from volatile to non-volatile memory. A voltage detector within the memory module may monitor the voltage of an external power source and generates an indicator of a power loss event if voltage of the external power source falls below a threshold level.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: July 12, 2016
    Assignee: SANMINA CORPORATION
    Inventors: Paul Sweere, Jonathan R. Hinkle