Abstract: Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.

Abstract: A semiconductor integrated circuit includes a buffer which outputs a memory control signal to a terminal coupled to a memory device, a power supply control circuit which controls a supply of a power supply voltage from a power supply line to the buffer based on a power control signal, a pull-up control circuit configured to control a pull-up of the terminal based on a pull-up control signal, and a control signal generating circuit. The control signal generating circuit generates, during an output period, the power control signal to supply the power supply voltage to the buffer, and the pull-up control signal to stop the pull-up of the terminal, and generates, during an idle period, the power control signal to stop the supply of the power supply voltage to the buffer, and the pull-up control signal to perform the pull-up of the terminal.

Abstract: To provide more uniform performance levels for solid state drive (SSDs), the static power level used by an SSD in an idle state is measured and used to determine a static power offset for each of the drives. The static power offset is set as a parameter for the SSD and used to offset a received power supply level for use on the drive. For a data storage system of multiple SSDs, a common scaling factor can be used to set the degree to which the static power offset is implemented, allowing for a choice between uniformity of power and uniformity of performance for the SSDs of a data storage system.

Abstract: This application discloses a mechanism to securely store and compute with a matrix of numbers or any two-dimensional array of binary values in a storage entity called a matrix space. A matrix space is designed to store matrices or arrays of values into arrays of volatile or non-volatile memory cells with accessibility in two or three dimensions. Any row or column or line of storage elements in the storage entity is directly accessible for writing, reading, or clearing via row bit lines and column bit lines, respectively. The elements in rows of the arrays are selected or controlled for access using row address lines and the elements in columns of the arrays are selected or controlled for access using column address lines. Access control methods and mechanisms with keys to secure, share, lock, and unlock regions in the matrix space for matrices and arrays under the control of an operating system or a virtual-machine hypervisor by permitted threads and processes are also disclosed.

Abstract: A semiconductor circuit according to the present disclosure includes: a first circuit configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit configured to apply an inverted voltage of a voltage at a second node to the first node; a first storage element including first, second, and third terminals; a first transistor including a drain coupled to the first node and a source coupled to the first terminal of the first storage element; a second transistor including a gate coupled to the first node or the second node and a drain coupled to the second terminal of the first storage element; and a third transistor including a gate coupled to the first node or the second node and a drain coupled to the second terminal of the first storage element. The first storage element is configured to set a resistance state between the first terminal and the second and third terminals in accordance with a direction of a current flowing between the second and third terminals.

Abstract: A semiconductor integrated circuit includes a buffer which outputs a memory control signal to a terminal coupled to a memory device, a power supply control circuit which controls a supply of a power supply voltage from a power supply line to the buffer based on a power control signal, a pull-up control circuit configured to control a pull-up of the terminal based on a pull-up control signal, and a control signal generating circuit. The control signal generating circuit generates, during an output period, the power control signal to supply the power supply voltage to the buffer, and the pull-up control signal to stop the pull-up of the terminal, and generates, during an idle period, the power control signal to stop the supply of the power supply voltage to the buffer, and the pull-up control signal to perform the pull-up of the terminal.

Abstract: A processing device in a memory sub-system detects a preemptive power loss condition in the memory sub-system and, in response, causes operations of a local media controller associated with a memory device in the memory sub-system to be suspended, wherein responsive to being suspended, the local media controller to perform power loss handling operations to complete a subset of a plurality of pending memory access operations, and wherein to perform the power loss handling operations, the local media controller to complete the subset of the plurality of pending memory access operations for which an acknowledgment signal has been sent to a requestor. The processing device further detects a full power loss and restore condition in the memory sub-system, responsive to detecting the full power loss and restore condition, initializes the memory device and causes operations of the local media controller to resume.

Abstract: Embodiments of the disclosure are directed to a system having a memory module, a voltage generation module, and a plurality of multiplexors. The memory module has a plurality of memory blocks. The voltage generation module supplies two or more voltage rails. The multiplexors are electrically connected to the voltage generation module. Each memory block is electrically connected to one of the multiplexors. Each multiplexor is configured to switch between the two or more voltage rails based on an operational parameter of each memory block. The operational parameter of each memory block may be process control speed, storage status, an operating mode, temperature, or any combination thereof. The operating mode may further be an active mode, a standby mode, and a deep sleep mode.

Abstract: A mobile computing device includes: a battery compartment configured to removably secure a first battery pack; an output device; and a processor configured to: detect a second battery pack in proximity to the mobile computing device; responsive to detecting the second battery pack, place the mobile computing device in a low-power operational mode; control the output device to generate a battery swap readiness notification; and responsive to securing of the second battery pack in the battery compartment in place of the first battery pack, return the mobile computing device to a full-power operational mode.

Abstract: One or more aspects of the present disclosure relate to data protection techniques in response to power disruptions a power supply from a continuous power source for a storage device can be monitored. A power disruption event interrupting the power supply from the continuous power source can further be identified. In response to detecting an event, a storage system can be switched to a backup power supply, power consumption of one or more components of the storage device can be controlled based on information associated with each component and an amount of power available in the backup power supply. Further, one or more power interruption operations can be performed while the backup power supply includes sufficient power for performing the power interruption operations.

Abstract: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

Abstract: The present application discloses a protection circuit for a memory in a display panel and a display panel. The circuit comprises a timing controller, a memory, a power circuit, and a switching circuit. Instead of having a computer provide a write protection signal to the memory to limit data in the memory from being overwritten, the power circuit provides a stable and reliable write protection signal to the memory, and then the timing controller controls the switching circuit to be turned on for grounding the write protection signal of the memory only when an instruction to write data to the memory is received.

Abstract: A server computer is configured to write a first copy of a block of data to a first namespace on a first non-volatile memory-based cache drive and a second copy of the block of data to a RAID controller for de-staging of the data to hard disk drives of a RAID array. Acknowledgment of hardening of the data on the hard disk drives initiates purging of the first copy of the block of data from the cache drive. High availability is enabled by writing a third copy of the block of data to a second server to store the block of data in a second namespace on a second non-volatile memory-based cache drive. Restoring of data after power loss accesses the data on the first non-volatile memory-based cache drive.

Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 ?S) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).

Abstract: Disclosed herein are techniques for implementing hybrid memory modules with improved inter-memory data transmission paths. The claimed embodiments address the problem of implementing a hybrid memory module that exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices) during data backup and data restore operations. Some embodiments are directed to approaches for providing a direct data transmission path coupling a non-volatile memory controller and the DRAM devices to transmit data between the DRAM devices and the flash devices. In one or more embodiments, the DRAM devices can be port switched devices, with a first port coupled to the data buffers and a second port coupled to the direct data transmission path. Further, in one or more embodiments, such data buffers can be disabled when transmitting data between the DRAM devices and the flash devices.

Abstract: In some embodiments, a method of reducing power consumption by a mobile telephone includes (1) providing a mobile telephone including a processor, an antenna, and a memory having computer program code; and (2) employing the processor of the mobile telephone and computer program code to (a) determine if the mobile telephone is in a vehicle; and (b) in response to the mobile telephone being in a vehicle, initiate a reduced power sequence in which the mobile telephone repeatedly turns off transmission by the antenna of the mobile telephone for a first time period and turns on transmission by the antenna of the mobile telephone for a second time period. Numerous other aspects are provided.

Abstract: The present disclosure relates to a method for data writing, a device and a storage medium, wherein the method includes acquiring a first data to be written and saving a plurality of sub-blocks of the first data in one or more designated aggregated queue of multiple aggregated queues according to an aggregation strategy; performing, in each designated aggregated queue, data interception on a plurality of sub-blocks in a current queue to obtain a second data to be written; and writing the second data in a storage device. The data distribution written in the storage device becomes more ideal by a multi-queue aggregation, and thus the method for data writing according to the embodiments of the present disclosure can reduce the time consumed in reading the storage device effectively.

Abstract: In an aspect of the disclosure, a reference voltage holding circuit is provided. The reference voltage holding circuit is for maintaining a sense amplifier reference voltage provided by a sense amplifier reference circuit, and the reference voltage holding circuit includes: a reference voltage generating circuit configured to provide a bias reference voltage; a current generating circuit electrically coupled to the reference voltage generating circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current mirror circuit and configured to provide for the standby bias current and to maintain the standby bias voltage which drives the sense amplifier reference voltage when reference voltage holding circuit operates under a standby operation and approximates the sense amplifier reference voltage as long as the sense amplifier reference voltage remains enabled.

Abstract: An embodiment of a semiconductor apparatus may include technology to determine a persistent region and a non-persistent region of a volatile media based on an amount of power available from one or more backup power sources, and periodically backup only the non-persistent region of the volatile media to a non-volatile media. Other embodiments are disclosed and claimed.

Abstract: A system can comprise a memory device and sequencing circuitry configured to provide enable signals to a number of voltage regulators in association with providing sequenced power signals to the memory device. The system can include voltage threshold detection circuitry configured to: detect primary supply voltage events; and responsive to detecting a primary supply voltage event, deassert a timer enable signal provided to timing circuitry. The timing circuitry is configured to, responsive to the deassertion of the timer enable signal: deassert a primary enable signal provided to the sequencing circuitry; and maintain the primary enable signal in a deasserted state for a particular amount of time prior to reasserting the primary enable signal.

Abstract: Examples disclosed herein relate to dual in-line memory module (DIMM) battery backup. Some examples disclosed herein describe systems that include a backup power source pluggable into a DIMM slot. The backup power source may include a plurality of battery cells electrically connected to a DIMM to provide backup power to the DIMM. Each of the plurality of battery cells supporting the DIMM may be electrically connected to a DC-to-DC converter in series and to each other in parallel.

Abstract: An indication of a power loss can be received at a cross point array memory dual in-line memory module (DIMM) operation component of a memory sub-system. The cross point array memory DIMM operation component includes a volatile memory component and a non-volatile cross point array memory component. In response to receiving the indication of the power loss, a type of write operation for the non-volatile cross point array memory component of the cross point array memory DIMM operation component is determined based on a characteristic of the memory sub-system. Data stored at the volatile memory component of the cross point array memory DIMM operation component is retrieved and written to the non-volatile cross point array memory component of the cross point array memory DIMM operation component by using the determined type of write operation.

Abstract: A data storage device includes a memory controller and a memory device. The memory device includes a current memory block. The memory controller is coupled to the memory device and configured to access the memory device. In response to detection of a sudden power-off that has occurred before the memory device is powered up, the memory controller is configured to find a last valid page and a last valid word line corresponding to the last valid page by scanning a plurality of pages in the current memory block, and determine whether to use one or more empty pages belonging to a word line group that is the same as that of the last valid page according to a read count and an erase count of the current memory block.

Abstract: A power saving control device includes: an acquirer that acquires a power saving request; and a controller that determines whether or not power saving control for reducing a power consumption of a load device is to be performed in response to the power saving request, and that, when determining that the power saving control is to be performed, performs the power saving control. When the load device consumes power, the controller determines that the power saving control is not to be performed under a condition that no power flows from a power system into a facility in which the load device is installed, the condition being one of one or more conditions.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a persistent memory system communicatively coupled to the processor, the persistent memory system comprising one or more persistent memory modules and a plurality of targeted save registers, each targeted save register associated with a respective portion of the persistent memory system, and each targeted save register having a value indicative of how save operations from volatile memory to non-volatile memory of the persistent memory system are to be performed with respect to the respective portion of the persistent memory system.

Abstract: Various features relate to the providing Software-Resilient User Privacy within smartphones or other devices by storing and processing all pertinent values needed for user privacy—such as security keys and access attempt counters—in hardware, such as within a System-on-a-Chip (SoC) processor formed on an integrated circuit (IC). For example, an on-die ephemeral Volatile Memory (eVM) device may be employed for storing access attempt counters or other parameters used to control malicious attack countermeasures. In one example, the eVM employs static random-access memory (SRAM) formed on the die and exploits capacitive remanence to recover stored counter values even if power is disconnected, then reconnected. On-chip NVM may be used for permanent storage of other privacy values, such as a device-unique secret key that is generated locally on the device and not known to the chip vendor, the device Original Equipment Manufacturer (OEM)) or the owner/user of the device.

Abstract: Disclosed herein are techniques for implementing hybrid memory modules with improved inter-memory data transmission paths. The claimed embodiments address the problem of implementing a hybrid memory module that exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices) during data backup and data restore operations. Some embodiments are directed to approaches for providing a direct data transmission path coupling a non-volatile memory controller and the DRAM devices to transmit data between the DRAM devices and the flash devices. In one or more embodiments, the DRAM devices can be port switched devices, with a first port coupled to the data buffers and a second port coupled to the direct data transmission path. Further, in one or more embodiments, such data buffers can be disabled when transmitting data between the DRAM devices and the flash devices.

Abstract: Approaches, techniques, and mechanisms are disclosed for a centralized backup power support system that improves testability of non-volatile dual in-line memory modules (NVDIMM) on Automatic Test Equipment (ATE) testers and in-system tests. An NVDIMM includes both volatile memories and non-volatile memories. According to an embodiment, a compact backup power distribution board is powered with an external power supply with an individual protection circuit. The backup power distribution board has an unlimited energy capacity for any density of NVDIMM and zero charge waiting time. According to an embodiment, instead of using an electric double-layer capacitor (EDLC) to support backup power, a resistor is used instead of an EDLC on each backup power module. There is no charging time when the backup power module does not have EDLC cells, resulting in significant reduction in test time and production cost and increase in production output.

Abstract: A clamping circuit includes an energy storage section and a pulse generator to generate a pulse in which the energy storage section stores energy from a main power supply.

Abstract: A pulse oximeter may reduce power consumption in the absence of overriding conditions. Various sampling mechanisms may be used individually or in combination. Various parameters may be monitored to trigger or override a reduced power consumption state. In this manner, a pulse oximeter can lower power consumption without sacrificing performance during, for example, high noise conditions or oxygen desaturations.

Abstract: Embodiments of the present disclosure relate to a solution for fault unit indication. In some embodiments, there is provided a method for positioning a fault unit. The method comprises supplying power to a controller and a light emitting diode (LED) circuit by a battery module, wherein the LED circuit includes a plurality of LEDs associated with a plurality of units. The method further comprises transmitting a trigger signal to the controller by the battery module in response to receiving a control signal for triggering positioning, such that an LED of the plurality of LEDs associated with a fault unit is turned on.

Abstract: A controller teaches a teaching point of a slave axis corresponding to a master axis so as to perform a synchronous operation. The controller calculates a teaching range based on one moving speed pattern selected from a plurality of moving speed patterns of the master axis which are preliminarily registered, a preliminarily-set allowable speed in an operation of the slave axis, and a calculated teaching range, in which teaching can be performed, of a following teaching point, so as to display the teaching range on a display device.

Abstract: A sequential delay mechanism is provided for a memory subsystem of a host system. A first independent SAVE region of NVDIMMs of the memory subsystem is configured to start a memory SAVE immediately upon receiving a SAVE signal from the host system, and other independent SAVE regions of the NVDIMMs are configured to implement the delay mechanism. A memory SAVE to the NVDIMMs is activated immediately in the first independent SAVE region when the SAVE signal is received, and the other independent SAVE regions sequentially delay their activation of the memory SAVE.

Abstract: Disclosed herein are techniques for implementing hybrid memory modules with improved inter-memory data transmission paths. The claimed embodiments address the problem of implementing a hybrid memory module that exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices) during data backup and data restore operations. Some embodiments are directed to approaches for providing a direct data transmission path coupling a non-volatile memory controller and the DRAM devices to transmit data between the DRAM devices and the flash devices. In one or more embodiments, the DRAM devices can be port switched devices, with a first port coupled to the data buffers and a second port coupled to the direct data transmission path. Further, in one or more embodiments, such data buffers can be disabled when transmitting data between the DRAM devices and the flash devices.

Abstract: A first control apparatus includes a first memory unit including a local cache, a first power supply that supplies electric power to the first memory unit, and a control unit. The control unit controls a write into a memory device by a write-back method, using the local cache. The control unit mirrors data of the local cache in a mirror cache of a second control apparatus. The control unit determines whether the mirror cache is included in a second memory unit that receives electric power from a second power supply of the second control apparatus, upon detecting an abnormal state of a battery for supplying electric power to the second memory unit in case of power outage of the second power supply. The second memory unit switches write control for the memory device to a write-through method, when the second memory unit includes the mirror cache.

Abstract: The invention relates to a power distribution system, such as a Power over Ethernet power distribution system. A powered device provides a pulse, such as a Maintain Power Signature, when in standby such that a power providing device remains providing power to it. To increase energy efficiency, the MPS can be cycled (60 ms pulse every 300 ms to 400 ms) according to the IEEE802.3af/at standards. By introducing a controllable switch, for electrically decoupling at least part of the powered device from the power providing device, and a pulse generator, the MPS can be generated in a more energy efficient way and/or can be shortened (e.g. to 5 ms). As an example, the controllable switch can decouple the bulk capacitor of the powered device during MPS generation to prevent the bulk capacitor from filtering out the MPS.

Abstract: Implementations disclosed herein provide a method comprising detecting a power supply status, determining a media cache cleaning scheme based on the detected power supply status, and performing the determined cleaning scheme until a predetermined threshold is reached.

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Abstract: In accordance with embodiments of the present disclosure, a method for power loss protection of one or more storage resources may include receiving information from each of the one or more storage resources regarding power loss protection capabilities of such storage resource. The method may also include based on the information, repurposing, for each power loss protection capable storage resource, a communications channel between a logic device and such power loss protection capable storage resource for transmission of a respective early power-off warning signal for such power loss protection capable storage resource. The method may further include in response to a power event of a power supply unit for providing electrical energy to the one or more storage resources, asserting for each power loss protection capable storage resource its respective early power-off warning signal.

Abstract: Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer program product for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a transfer logic used in a power-loss save of the write cache. The one or more operating parameters include an instance-specific process speed of the transfer logic which is retrieved as bin data. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller.

Abstract: In accordance with embodiments of the present disclosure, a method may include, during boot of an information handling system, determining a first amount of energy required by the information handling system to flush a cache integral to the information handling system to memory integral to the information handling system in response to a power loss of one or more power supplies for supplying electrical energy to the information handling system, determining whether a second amount of energy available for hold-up of one or more power supplies in response to the power loss exceeds the first amount of energy, and responsive to determining whether the second amount of energy exceeds the first amount of energy, configuring the cache.

Abstract: A method for reducing a need for power in a backup mode of operation in a data center includes receiving a first alert from an uninterruptible power supply indicating that the uninterruptible power supply is operating in a first mode, wherein the first mode includes deriving power from a stored energy source, identifying at least one host server configured to receive power from the uninterruptible power supply in the first mode, suspending execution of at least one virtual machine on the at least one host server, receiving a second alert from the uninterruptible power supply indicating that the uninterruptible power supply is operating in a second mode, wherein the second mode includes deriving power from one of a mains power source and a generator, and resuming execution of the at least one virtual machine.

Abstract: Data stored in a volatile memory subsystem is backed up redundantly into first and second channels of a non-volatile memory subsystem. The data is retrieved from the volatile memory subsystem upon detection of a trigger condition indicative of real or imminent power loss or reduction and multiple copies are stored in dedicated non-volatile memory channels. The stored copies may be error checked and corrected, and re-written if necessary. The redundantly backed up data can be subsequently retrieved from the non-volatile memory subsystem, error-corrected, and an error-free copy communicated to the volatile memory subsystem.

Abstract: A pulse oximeter may reduce power consumption in the absence of overriding conditions. Various sampling mechanisms may be used individually or in combination. Various parameters may be monitored to trigger or override a reduced power consumption state. In this manner, a pulse oximeter can lower power consumption without sacrificing performance during, for example, high noise conditions or oxygen desaturations.

Abstract: A method and apparatus for dynamic power management of memories. In one embodiment of the invention, the power consumption of the memories is reduced based on the operating state of the memories. For example, in one embodiment of the invention, the power supply to the memories is reduced when the memories are in an inactive state by reducing and/or turning off the input voltage(s) to the memories. In one embodiment of the invention, the processing unit dynamically changes the strength of the On-Die Termination pull-up/pull-down resistance based on the memory operating mode, memory voltage, and memory temperature.

Abstract: An apparatus forms a memory system that is physically populated into a host. In a powered-on state, the apparatus logically connects to the host through a host memory controller configured to receive host-initiated commands. The memory system includes a command buffer coupled to the host memory controller to receive the host-initiated commands. The memory system comprises both volatile memory (e.g., RAM) and non-volatile memory (e.g., FLASH). A non-volatile memory controller (NVC) is coupled to the volatile memory, and is also coupled to the non-volatile memory. A command sequence processor that is co-resident with the NVC responds to a trigger signal by logically disconnecting from the host, then dispatching command sequences that perform successive read/write operations between the volatile memory and the non-volatile memory. The successive read/write operations are performed even when the host is in a powered-down state.

Abstract: An integrated circuit according to an embodiment includes: a first wiring line group including at least three first wiring lines; a second wiring line group including second wiring lines; first resistive change elements each including a first and second terminals, and a first resistive change layer; a first select circuit including first input terminals connected to the second wiring lines and a first output terminal, the first select circuit selecting a first input terminal from the first input terminals, and output information from the first output terminal; a third and fourth wiring lines; and a second select circuit selecting two first wiring lines from the first wiring line group, connecting one of the selected two first wiring lines to the third wiring line, and connecting the other one of the selected two first wiring lines to the fourth wiring line.

Abstract: Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer implemented method for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a component used in a power-loss save of the write cache. The component is selected from the group consisting of an energy storage element, a non-volatile memory, and a transfer logic. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller.

Abstract: Context recognition methods and apparatus are provided for an application processor and a micro control unit. It is determined whether an operation switch condition for switching to a sleep mode is satisfied. A request for execution of a context recognition function is sent to a micro control unit, when the operation switch condition is satisfied. The application processor switches to the sleep mode, when the context recognition function is executed by the micro control unit. The micro control unit collects sensor data at previously stored time intervals, and previously stored state information is updated based on the sensor data.

Abstract: According to one embodiment, the memory system includes a nonvolatile semiconductor memory, a data buffer, a volatile memory for storing a management table uniquely associates the user data with an address of the physical storage region of nonvolatile semiconductor memory, a controller that carries out a force quit process for writing the user data stored in a data buffer, the management table stored in volatile memory into the nonvolatile semiconductor memory, and a storage battery. The controller starts the force quit process prior to the power supply of the internal power supply regulator is switched from an external power supply to the storage battery.