Multiple Port Access Patents (Class 365/230.05)
  • Patent number: 10388330
    Abstract: Memory devices connected in a chain topology to a host controller that communicate using Low Voltage Differential Signaling (LVDS) and out-of-band signaling.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Mark Leinwander
  • Patent number: 10332590
    Abstract: Static random access memory (SRAM) bit cells employing current mirror-gated read ports for reduced power consumption are disclosed. In one aspect, an SRAM bit cell includes a read port employing a first transistor electrically coupled to a current sum line and to a current mirror circuit. A level of current that flows through the first transistor in response to voltage applied by the current mirror circuit correlates to a magnitude of the voltage. The read port includes a second transistor electrically coupled to the first transistor, to a driver circuit, and to an output node of a first inverter. Connecting the first and second transistors of the read port in this manner allows a voltage applied to the second transistor to generate a current that flows to the first transistor if the second transistor is activated. The current level depends on the voltage applied by the current mirror circuit.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Jianguo Yao
  • Patent number: 10224091
    Abstract: A system includes multiple memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address input circuit coupled to the address path that refreshes a first set of memory banks via the address path and, when the command address input circuit refreshes the first set of memory banks, activates a row of a second set of memory banks to store the data or read the data from the row of the second set of memory banks via the address path.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: March 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Joosang Lee
  • Patent number: 10210947
    Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: February 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Sano, Shunya Nagata, Shinji Tanaka
  • Patent number: 10163497
    Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Min Chan, Wei-Cheng Wu, Yen-Huei Chen
  • Patent number: 10141046
    Abstract: A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 27, 2018
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 10068647
    Abstract: A semiconductor memory device includes a first block that includes a first set of word lines, a second block that includes a second set of word lines and is adjacent to the first block in a first direction, a first transistor group adjacent to the first and second blocks in a second direction crossing the first direction, and a second transistor group adjacent to the first transistor group in the second direction. Each of the word lines in the first set is electrically connected to a transistor in the first transistor group, and each of the word lines in the second set is electrically connected to a transistor in the first transistor group.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: September 4, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Nobuaki Okada, Toshiki Hisada
  • Patent number: 10061542
    Abstract: Aspects of a memory and method for accessing the memory are disclosed. The memory includes a plurality of memory cells configured to support a read and write operation in a memory cycle in a first mode and a write only operation in the memory cycle in a second mode. The memory further includes a control circuit configured to generate a read clock for the read operation and a write clock for the write operation. The timing of the write clock is a function of the timing of the read clock in the first mode, and the timing of the memory cycle in the second mode.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 28, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Tony Chung Yiu Kwok, Nishith Nitin Desai, Changho Jung
  • Patent number: 10043571
    Abstract: SRAM structures are provided. A SRAM structure includes multiple SRAM cells arranged in multiple rows and multiple columns. The SRAM cells in the same row are divided into multiple groups. Each group includes a first SRAM cell and a second SRAM cell adjacent to the first SRAM cell. The first and second Vss lines and the first and second word-line landing pads are formed in a first metallization layer and extend parallel to a first direction. The third Vss line and the first word line are formed in a second metallization layer and extend parallel to a second direction. The first word-line landing pad is positioned within the rectangular shape of the first or second SRAM cell, and the second word-line landing pad is positioned within the rectangular shape of the second SRAM cell. The second metallization layer is positioned on the first metallization layer.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10043581
    Abstract: A memory circuit capable of implementing calculation operations, including: memory cells arranged in rows and in columns, each cell including: a data bit storage node, a read-out transistor connected by its gate to the storage node, and a selection transistor series-connected with the read-out transistor between a reference node and a conductive output track common to all the cells of a same column; and a control circuit configured to simultaneously activate the selection transistors of at least two cells of a same column of the circuit, and to read from the conductive output track of the column a value representative of the result of a logic operation having as operands the data of the two cells.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 7, 2018
    Assignee: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventors: Jean-Philippe Noel, Kaya Can Akyel
  • Patent number: 9972401
    Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: May 15, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Sano, Shunya Nagata, Shinji Tanaka
  • Patent number: 9905292
    Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: February 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Min Chan, Wei-Cheng Wu, Yen-Huei Chen
  • Patent number: 9881667
    Abstract: A memory cell includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: January 30, 2018
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 9876017
    Abstract: Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: January 23, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Stanley Seungchul Song, Zhongze Wang, Kern Rim, Choh Fei Yeap
  • Patent number: 9836404
    Abstract: Systems and techniques are disclosed for the mirroring of cache data from a storage controller to a storage class memory (“SCM”) device. The storage controller receives a write request, caches the write data, and mirrors the write data to the SCM device instead of to a cache of another storage controller. The SCM device stores the mirrored data in the SCM device. The storage controller acknowledges the write to the host. If the storage controller later fails, an alternate controller assumes ownership of storage volumes associated with the failed controller. Upon receipt of a new read request to the failed controller, the alternate controller checks the SCM device for a cache hit. If there is, the data is read from the SCM device; otherwise, it is read from the storage volume(s). The read data is cached at the alternate controller and then sent on to the requesting host.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: December 5, 2017
    Assignee: NetApp, Inc.
    Inventors: Sandeep Kumar R. Ummadi, Brian McKean, Gregory Friebus, Pradeep Ganesan
  • Patent number: 9824024
    Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, an arithmetic circuit, and a control circuit. The control circuit may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement first-in first-out modules, shift registers, or delay-line modules in addition to implementing memory modules with random access.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: November 21, 2017
    Assignee: Altera Corporation
    Inventors: Carl Ebeling, Jeffrey Christopher Chromczak, David Lewis
  • Patent number: 9812189
    Abstract: An apparatus is provided which comprises: a memory array; first logic to detect whether first and second word-lines (WL) for a row of the memory array are active; and second logic to deactivate one of the first and second WLs such that one of the first and second WLs is active for the row.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventors: Pramod Kolar, Wei-Hsiang Ma, Gunjan H. Pandya
  • Patent number: 9806083
    Abstract: Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: October 31, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Stanley Seungchul Song, Zhongze Wang, Kern Rim, Choh Fei Yeap
  • Patent number: 9646974
    Abstract: A dual-port static random access memory (SRAM) cell includes first through third power lines, a storage unit connected to the first through third power lines, a first port having first and second pass-gate transistors controlled by a first wordline, a second port having third and fourth pass-gate transistors controlled by a second wordline, and first through fourth bitlines coupled to the storage unit through the first through fourth pass-gate transistors, respectively. The first through fourth bitlines and the first through third power lines each extend in a first direction and are formed of a first metal layer. The first wordline extends in a second direction substantially perpendicular to the first direction and is formed of a second metal layer above the first metal layer. The second wordline extends in the second direction and is formed of a upper-level metal layer above the second metal layer.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: May 9, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9627062
    Abstract: There is provided a memory unit that comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to a first local bit line and a second local bit line by respective first and second access transistors, and each memory cell being associated with a word line configured to control the first and second access transistors of the memory cell. The first and second local bit lines of each memory cell group being operatively connected to respective first and second column bit lines by respective first and second group access switches, the first group access switch being configured to be controlled by the second column bit line, and the second group access switch being configured to be controlled by the first column bit line.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: April 18, 2017
    Assignee: SURECORE LIMITED
    Inventor: Andrew Pickering
  • Patent number: 9606943
    Abstract: An external storage device includes a memory, a controller, a first interface, a second interface, a first switching module, and a second switching module. The controller is coupled to the memory. The first interface is used to connect to a first electronic device. The second interface used to connect to a second electronic device. The first switching module is coupled to the controller, the first interface, and the second interface. The second switching module is coupled to the controller, the first interface, the second interface, and the first switching module. When the first interface is electrically connected to a first electronic device and the second interface is electrically connected to the second electronic device, the first electronic device charges the controller and the second electronic device through the first switching module, and the first electronic device accesses the memory through the second switching module and the controller.
    Type: Grant
    Filed: June 15, 2014
    Date of Patent: March 28, 2017
    Assignee: Transcend Information, Inc.
    Inventors: Li-Min Lien, Ren-Wei Chen
  • Patent number: 9589624
    Abstract: In a semiconductor device in accordance with one embodiment, a memory access control unit counts the number of addresses accessed by burst access to each address included in an address set of an external memory that is going to be accessed. When the number of addresses is larger than a reference value, the memory access control unit performs burst access to the address, and when the number of addresses is smaller than the reference value, the memory access control unit performs random access to the address.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: March 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Shorin Kyo
  • Patent number: 9576645
    Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Min Chan, Wei-Cheng Wu, Yen-Huei Chen
  • Patent number: 9570154
    Abstract: A dual-port SRAM timing control circuit, with three NMOS transistors connected in series respectively between ground and nodes of the two bit lines to which the cell structure corresponds. The gates of the NMOS transistors are connected to a corresponding wordline, a pulse signal and a timing control signal, respectively. The each pulse signals are formed by a corresponding clock signal inputted into a first pulse generator, respectively. An address signal, after passing through an address latch, is inputted into an address comparator for comparison, with the address comparison result outputted to a timing control signal generator; and the pulse signal, after undergoing an AND operation, is inputted into the timing control signal generator, with a timing control signal outputted.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 14, 2017
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Yijun Qian
  • Patent number: 9508113
    Abstract: A pipeline system includes input buffers, a relay for controlling withdrawal of data stored in the input buffers, and functional blocks for performing one or more processing operations. A method of operating a pipeline system includes withdrawing data from one of input buffers and performing different one or more processing operations.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: November 29, 2016
    Assignees: Samsung Electronics Co., Ltd., Kongju National University Industry-University Cooperation Foundation
    Inventors: Won-jong Lee, Hyun-sang Park, Young-sam Shin, Jae-don Lee
  • Patent number: 9490006
    Abstract: In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: November 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Xiuli Yang, He-Zhou Wan, Ming-En Bu, Mu-Jen Huang, Ching-Wei Wu
  • Patent number: 9470759
    Abstract: In general, a test instrument includes a processing system programmed to control operation of the test instrument, including communication with a control system, and programmed to run one or more test programs to test a device interfaced to the test instrument, the processing system including multiple processing devices, and a configurable interface, through which communications are exchanged with the device interfaced to the test instrument, the configurable interface including physical ports, to which different configurations are assignable.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: October 18, 2016
    Assignee: Teradyne, Inc.
    Inventors: Stephen J. Bourassa, Michael Francis McGoldrick, David Kaushansky, Michael Thomas Fluet
  • Patent number: 9466357
    Abstract: A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: October 11, 2016
    Assignee: Faraday Technology Corp.
    Inventors: Ching-Te Chuang, Chien-Yu Lu, Ming-Ching Zheng, Ming-Hsien Tu
  • Patent number: 9455026
    Abstract: An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: September 27, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Stanley Seungchul Song, Zhongze Wang, Ping Liu, Kern Rim, Choh Fei Yeap
  • Patent number: 9424188
    Abstract: A method of operation of a non-volatile memory packaging system includes: addressing an integrated circuit package having a system interface; accessing a module controller, in the integrated circuit package, through system interface; accessing a random access memory, in the integrated circuit package, by the module controller for storing data from the system interface; writing to a non-volatile memory, in the integrated circuit package by the module controller, with the data from the random access memory; and monitoring an address look-up register, by the module controller, for reading the data from the non-volatile memory or the random access memory through the system interface.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: August 23, 2016
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Mike H. Amidi, Michael Rubino, Alessandro Fin
  • Patent number: 9419617
    Abstract: A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to control the output node during a standby mode. The circuit also comprises a transistor coupled to the output node. The control circuit is configured to turn off the transistor during the standby mode.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Bryan Sheffield, Chih-Chang Lin
  • Patent number: 9368443
    Abstract: A memory includes a plurality of memory cells. A first line is over the plurality of memory cells. The first line in a first layout section includes a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A second line is over the plurality of memory cells. The second line in the first layout section includes the first metal layer and a third metal layer. The third metal layer is over the second metal layer The first line is electrically isolated from the second line. The first line and the second line extend in a same direction.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: June 14, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Derek C. Tao, Jacklyn Chang, Kuoyuan (Peter) Hsu, Yukit Tang
  • Patent number: 9336865
    Abstract: A multi-port SRAM module includes a cell array comprising a plurality of cells, each having a first port and a second port; a first word line which is coupled to a plurality of cells of a target row to open and close the first port; a second word line which is coupled to the cells of the target row to open and close the second port; and a switch, which is coupled to the first word line and the second word line and couples the second word line to a reference voltage level according to a voltage level of the first word line.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: May 10, 2016
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventors: Li-Wei Chu, Nan-Chun Lien
  • Patent number: 9304693
    Abstract: Systems and methods for writing data to a data storage structure are provided. A data storage structure includes an array of storage locations. A plurality of write ports are configured to write a number of elements to the array simultaneously. The array of storage locations is arranged logically into N groups. Each group of the N groups is associated with a single multiplexer of a plurality of multiplexers. The single multiplexer is configured to receive inputs from the plurality of write ports and to select a single input to be written to a storage location of the associated group.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 5, 2016
    Assignee: Marvell International Ltd.
    Inventor: Kim Schuttenberg
  • Patent number: 9280479
    Abstract: A memory system having increased throughput is disclosed. Specifically, the memory system includes a first level write combining queue that reduces the number of data transfers between a level one cache and a level two cache. In addition, a second level write merging buffer can further reduce the number of data transfers within the memory system. The first level write combining queue receives data from the level one cache. The second level write merging buffer receives data from the first level write combining queue. The level two cache receives data from both the first level write combining queue and the second level write merging buffer. Specifically, the first level write combining queue combines multiple store transactions from the load store units to associated addresses. In addition, the second level write merging buffer merges data from the first level write combining queue.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: March 8, 2016
    Assignee: Applied Micro Circuits Corporation
    Inventors: David A. Kruckemyer, John Gregory Favor, Matthew W. Ashcraft
  • Patent number: 9281024
    Abstract: A write block read apparatus for a memory device includes a dynamic read address decoder that receives static read address bits as inputs thereto and having an output used to implement a read operation of a memory location corresponding to the read address bits; a dynamic write address decoder that receives static write address bits as inputs thereto and having an output used to implement a write operation of a memory location corresponding to the write address bits; and a static write address decoder, configured in parallel with the dynamic write address decoder, the static write address decoder configured to receive a portion of the static write address bits as inputs thereto, and wherein the static write address decoder is coupled to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Paul A. Bunce, Yuen H. Chan, John D. Davis, Diana M. Henderson
  • Patent number: 9281025
    Abstract: A method of implementing a write block read function for a memory device includes configuring a dynamic read address decoder to receive static read address bits as inputs thereto and to generate an output used to implement a read operation of a memory location corresponding to the read address bits; configuring a dynamic write address decoder to receive static write address bits as inputs thereto and to generate an output used to implement a write operation of a memory location corresponding to the write address bits; and configuring a static write address decoder, in parallel with the dynamic write address decoder, to receive a portion of the static write address bits as inputs thereto, and coupling the static write address decoder to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Paul A. Bunce, Yuen H. Chan, John D. Davis, Diana M. Henderson
  • Patent number: 9275704
    Abstract: The disclosure provides an asynchronous FIFO circuit that includes a data memory which is coupled to a write data path and a read data path. The data memory receives a write clock and a read clock. A FIFO write pointer counter receives a write enable signal and the write clock. The FIFO write pointer counter provides a FIFO write pointer signal to the data memory. A FIFO read pointer counter receives a read enable signal and the read clock. The FIFO read pointer counter provides a FIFO read pointer signal to the data memory. A control circuit receives the write enable signal, the read enable signal, the FIFO write pointer signal, the FIFO read pointer signal, the write clock and the read clock. The control circuit generates a memory full signal when the data memory is full and a memory empty signal when the data memory is empty.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: March 1, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rakesh Channabasappa Yaraduyathinahalli, Shekhar Dinkar Patil
  • Patent number: 9268718
    Abstract: An exemplary signal collection system includes a signal transmitting module and a computer. The signal transmitting module outputs a high-speed signal with a high frequency. The signal collection system further includes a data collection module interconnecting the signal transmitting module and the computer. The data collection module includes a frequency reduction unit. The frequency reduction unit reduces the frequency of the high-speed signal output from the signal transmitting module and outputs the high-speed signal with a reduced frequency to the computer. A signal collection method based upon the signal collection system is also disclosed.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 23, 2016
    Assignee: ScienBziP Consulting(Shenzhen)Co., Ltd.
    Inventor: Li-Wen Guo
  • Patent number: 9262349
    Abstract: A memory content access interface may include, but is not limited to: a read-path memory partition; a write-path memory partition; and a memory access controller configured to regulate access to at least one of the read-path memory partition and the write-path memory partition by an external controller.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: February 16, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Herjen Wang, Lei Chen, Ngok Ning Chu, Johnson Yen
  • Patent number: 9256430
    Abstract: A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: February 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juergen Koehl, Jens Leenstra, Philipp Panitz, Hans Schlenker
  • Patent number: 9230690
    Abstract: Embodiments of a register file test circuit are disclosed that may allow for determining write performance at low power supply voltages. The register file test circuit may include a decoder, a multiplexer, a frequency divider, and a control circuit. The decoder may be operable to select a register cell within a register file, and the control circuit may be operable to controllably activate the read and write paths through the selected register cell, allowing data read to be inverted and re-written back into the selected register cell.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: January 5, 2016
    Assignee: Apple Inc.
    Inventors: Greg M Hess, James E Burnette, II
  • Patent number: 9230622
    Abstract: A method includes generating a first and a second internal clock signal from a clock signal, wherein a first internal clock signal edge of the first internal clock signal and a second internal clock signal edge of the second internal clock signal are generated from a same edge of the clock signal. A first one of the first and the second internal clock edges is used to trigger a first operation on a six-transistor (6T) Static Random Access Memory (SRAM) cell of a SRAM array. A second one of the first and the second internal clock edges is used to trigger a second operation on the 6T SRAM cell. The first and the second operations are performed on different ports of the 6T SRAM. The first and the second operations are performed within a same clock cycle of the clock signal.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wei Wu, Chia-Cheng Chen, Kuang Ting Chen, Wei-Shuo Kao, Jui-Che Tsai
  • Patent number: 9224446
    Abstract: A memory circuit includes first and second word lines, a plurality of memory cells and a timing controller. Each memory cell includes a first access port and a second access port. The first access port is coupled to the first word line and configured to be enabled by a first word line signal on the first word line. The second access port is coupled to the second word line and configured to be enabled by a second word line signal on the second word line. The timing controller is configured to receive a timing select signal and to control a time delay between the first word line signal and the second word line signal to be different in response to different first and second states of the timing select signal.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: December 29, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Adrian Earle
  • Patent number: 9218871
    Abstract: To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: December 22, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Yasushi Takahashi, Toru Ishikawa
  • Patent number: 9214222
    Abstract: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the read word line WLB corresponding to the selected memory cell 3. A write operation activates the write word line WLA corresponding to the selected memory cell 3. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: December 15, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichiro Ishii, Yoshikazu Saito, Shinji Tanaka, Koji Nii
  • Patent number: 9171849
    Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: October 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Min Chan, Wei-Cheng Wu, Yen-Huei Chen
  • Patent number: 9171594
    Abstract: A multiport memory having an array of storage cells for storing data; a plurality of data access ports; and access control circuitry to assign each data access port to one of the sets of access control lines and corresponding data lines. The control circuitry has collision detection circuitry to detect a colliding data access request received at a second data access port that requests access to a row of storage cells currently being accessed by a data access request received at a first data access port. The control circuitry is responsive to the detected collision to assign the set of access control lines and corresponding data lines currently assigned to the first data access port to the second data access port and to subsequently assign the first data access port to the set of access control lines and corresponding data lines previously assigned to the second access port.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: October 27, 2015
    Assignee: ARM Limited
    Inventor: Vivek Dhogale
  • Patent number: RE46272
    Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: January 10, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koji Nii
  • Patent number: RE47207
    Abstract: The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes a first and second inverters cross-coupled for data storage, each inverter includes a pull-up device (PU) and a plurality of pull-down devices (PDs); a plurality of pass gate devices configured with the two cross-coupled inverters; and at least two ports coupled with the plurality of pass gate devices (PGs) for reading and writing, wherein each of PU, PDs and PGs includes a fin field-effect transistor (FinFET), a ratio between a number of PDs in the SRAM cell and a number of PGs in the SRAM cell is greater than 1, and a number of FinFETs in the SRAM cell is equal to or greater than 12.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: January 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw