Multiple Port Access Patents (Class 365/230.05)
  • Patent number: 11556162
    Abstract: A processor utilizes instruction based sampling to generate sampling data sampled on a per instruction basis during execution of an instruction. The sampling data indicates what processor hardware was used due to the execution of the instruction. Software receives the sampling data and generates an estimate of energy used by the instruction based on the sampling data. The sampling data may include microarchitectural events and the energy estimate utilizes a base energy amount corresponding to the instruction executed along with energy amounts corresponding to the microarchitectural events in the sampling data. The sampling data may include switching events associated with hardware blocks that switched due to execution of the instruction and the energy estimate for the instruction is based on the switching events and capacitance estimates associated with the hardware blocks.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: January 17, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shijia Wei, Joseph L. Greathouse, John Kalamatianos
  • Patent number: 11550722
    Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric; a first root port and a second root port, each of the first and second root ports coupled to a corresponding IOMMU of the first and second IOMMUs; and a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports, wherein each of the first and second root ports comprises hardware control logic operative to: synchronize the first and second root ports.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: January 10, 2023
    Assignees: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.
    Inventors: Philip Ng, Nippon Raval, BuHeng Xu, Rostislav S. Dobrin, Shawn Han
  • Patent number: 11262939
    Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller and an operating method, which allocate one or more of a plurality of buffer slots in a buffer pool to a write buffer as write buffer slots or to a read buffer as read buffer slots, configures initial values of count information on the respective write buffer slots and the respective read buffer slots, which indicate remaining allocation periods respectively, and updates the count information on each of at least some of the write buffer slots when data is written to the write buffer or updates the count information on each of at least some of the read buffer slots when data is read out from the read buffer, thereby providing optimal data read and write performance and minimizing overhead caused in the process of dynamically changing the buffer size.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: March 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Joung Young Lee
  • Patent number: 11257540
    Abstract: A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: February 22, 2022
    Assignee: GSI Technology, Inc.
    Inventors: Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
  • Patent number: 11170845
    Abstract: Certain aspects of the present disclosure are directed to a memory system. The memory system generally includes a word line (WL) driver circuit comprising a transistor coupled between a WL of a memory and a reference potential node. The memory system also includes a clamping circuit having logic configured to generate a control signal to drive a gate of the transistor such that the control signal is floating when the first head switch is open, and a first head switch coupled between a voltage rail and a supply input of the logic.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 9, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Arun Babu Pallerla, Derek Yang, Chulmin Jung, Changho Jung
  • Patent number: 11169953
    Abstract: A data processing system including a shared memory; a host processor configured to possess an ownership of the shared memory, and process a first task by accessing the shared memory; a processor configured to possess the ownership transferred from the host processor, and process a second task by accessing the shared memory; and a memory controller coupled among the host processor, the processor, and the shared memory, and configured to allow the host processor or the processor to access the shared memory according to the ownership.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: November 9, 2021
    Assignee: SK hynix inc.
    Inventors: Ji Hoon Nam, Eui Cheol Lim
  • Patent number: 11150835
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: October 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Patent number: 11152046
    Abstract: A memory array that provides an internal retention voltage without a voltage regulator is disclosed. The memory array includes a first group of bit cells coupled between the power supply rail and a ground switch and a second group of bit cells coupled to a retention select circuit. The retention select circuit is coupled to the ground for the first group of bit cells and the power supply rail. The ground switch and the retention select circuit may be operated to switch the bit cells between a nominal operating voltage and a retention voltage. The retention voltage is provided during inactive periods of the memory array to maintain data in the bit cells during the inactive periods.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: October 19, 2021
    Assignee: Apple Inc.
    Inventors: Jaroslav Raszka, Shahzad Nazar, Jaemyung Lim, Mohamed H. Abu-Rahma, Victor Zyuban
  • Patent number: 11133049
    Abstract: A memory architecture for 3-dimensional thyristor cell arrays is disclosed. Thyristor memory cells are connected in a 3-dimensional cross-point array to form a bit line cluster. The bit line clusters are connected in parallel to sense amplifier and write circuits through multiplexer/demultiplexer circuits. Control circuits select one of the bit line clusters during a read or write operation while the non-selected bit line clusters are not activated to avoid disturbs and power consumption in the non-selected bit line clusters. The bit line clusters, multiplexer/demultiplexer circuits, and sense amplifier and write circuits from a memory array tile (MAT).
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 28, 2021
    Assignee: TC Lab, Inc.
    Inventor: Bruce L. Bateman
  • Patent number: 11126402
    Abstract: A multiply-accumulate (MAC) operation in a deep neural network (DNN) consists of multiplying each input signal to a node by a respective numerical weight data and summing the products. Using ternary values for the input signals and weight data reduces memory and processing resources significantly. By representing ternary values in two-bit binary form, MAC operations can be replaced with logic operations (e.g., XNOR, popcount) implemented in logic circuits integrated into individual memory array elements in which the numerical weight data are stored. In this regard, a ternary computation circuit (TCC) includes a memory circuit integrated with a logic circuit. A memory array including TCCs performs a plurality of parallel operations (e.g., column or row elements) and determines a popcount. A TCC array in which logic circuits in columns or rows employ a single read-enable signal can reduce routing complexity and congestion of a metal layer in a semiconductor device.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 21, 2021
    Assignee: QUALCOMM Incorporated
    Inventor: Xia Li
  • Patent number: 11080047
    Abstract: The number of registers required is reduced by overlapping scalar and vector registers. This allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are reduced by restricting read access. Dedicated predicate registers reduce requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 3, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy David Anderson, Due Quang Bui, Mel Alan Phipps, Todd T. Hahn, Joseph Zbiciak
  • Patent number: 11030128
    Abstract: A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 8, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Yoram Betser, Cliff Zitlaw, Stephan Rosner, Kobi Danon, Amir Rochman
  • Patent number: 10998040
    Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: May 4, 2021
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Lee-Lean Shu, Eli Ehrman
  • Patent number: 10930341
    Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: February 23, 2021
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Bob Haig, Chao-Hung Chang
  • Patent number: 10892008
    Abstract: A memory macro system may be provided. The memory macro system may comprise a first segment, a second segment, a first WL, and a second WL. The first segment may comprise a first plurality of memory cells. The second segment may comprise a second plurality of memory cells. The first segment may be positioned over the second segment. The first WL may correspond to the first segment and the second WL may correspond to the second segment. The first WL and the second WL may be configured to be activated in one cycle.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: January 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei-Chang Zhao
  • Patent number: 10886120
    Abstract: An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: January 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Alan West, Adrian Salinas, Elizabeth C. Stewart, Dhanoop Varghese, Thomas D. Bonifield
  • Patent number: 10867642
    Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsin-Cheng Chen, Jung-Rung Jiang, Yen-Hao Huang
  • Patent number: 10847212
    Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability for selected write data in a bit line section to be logically combined (e.g. logically ANDed) with the read result on a read bit line, as if the write data were the read data output of another computational memory cell being read during the read operation. When accumulation logic is implemented in the bit line sections, the implementation and utilization of additional read logic circuitry provides a mechanism for selected write data in a bit line section to be used as the data with which the read result on the read bit line accumulates, before the newly accumulated result is captured and stored in the bit line section's read register.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: November 24, 2020
    Assignee: GSI Technology, Inc.
    Inventors: Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
  • Patent number: 10748911
    Abstract: An integrated circuit structure includes a semiconductor substrate, an active area, a gate electrode, and a butted contact. The active area is oriented in a first direction and has at least one tooth portion extending in a second direction in the semiconductor substrate. The gate electrode overlies the active area and extends in the second direction. The butted contact has a first portion above the gate electrode and a second portion above the active area. A portion of the second portion of the butted contact lands on the tooth portion.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gulbagh Singh, Shun-Chi Tsai, Chih-Ming Lee, Chi-Yen Lin, Kuo-Hung Lo
  • Patent number: 10725777
    Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: July 28, 2020
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Chao-Hung Chang, Avidan Akerib
  • Patent number: 10656615
    Abstract: A received-data writer of a network unit records first data in a first data area when a flag is set indicating that a write is allowed, and records second data in a second data area. The first data are data for which data consistency is to be guaranteed among received data that is received from the first slave station and a second slave station, and the second data are data for which real-timeliness is to be guaranteed among the received data. A first transferrer of a CPU transfers the first data recorded in the first data area to a first storage at an interval of a first transfer period when the flag is set indicating that a read is allowed. A second transferrer of the CPU transfers the second data recorded in the second data area to a second storage at an interval of a second transfer period.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: May 19, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Katsuhiro Annen
  • Patent number: 10649849
    Abstract: A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Hun Kim, Su-Yeon Doo, Dong-Seok Kang, Hye-Jung Kwon, Young-Ju Kim
  • Patent number: 10628255
    Abstract: A method for multi-dimensional decoding, the method may include receiving a multi-dimensional encoded codeword that comprises a payload and a redundancy section; wherein the payload comprises data and an error detection process signature; evaluating, during a multi-dimensional decoding process of the multi-dimensional encoded codeword, an hypothesis regarding a content of the payload; applying on the hypotheses an error detection process to provide an indication about a validity of the hypotheses; and proceeding with the multi-dimensional decoding process and finding a next hypothesis to be error detection process validated when the hypothesis is invalid.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: April 21, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Avi Steiner, Hanan Weingarten
  • Patent number: 10622078
    Abstract: A memory circuit that is organized into memory pages includes control circuitry for (a) associating a designated one or more memory pages to a data file and associating with the data file a unique identifier index number generated by a system controller; and associating a time-stamp with the unique identifier index number every time the data file is stored or updated in the memory circuit, wherein all unique identifier index numbers for all files stored in the memory circuit are stored in a lookup table in the memory circuit with the latest time-stamp and the location in the memory circuit at which the file is stored.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: April 14, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Robert D. Norman, Eli Harari
  • Patent number: 10553285
    Abstract: An apparatus includes a first single-port memory, a second single-port memory, and one or more control circuits in communication with the first single-port memory and in communication with the second single-port memory. The one or more control circuits are configured to initiate a read of stored data on a clock cycle from a physical location of the stored data in the first or second single-port memory and to initiate a write of fresh data on the clock cycle to whichever of the first single-port memory or the second single-port memory does not contain the physical location of the stored data.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ran Zamir, David Avraham, Eran Sharon, Idan Alrod
  • Patent number: 10541237
    Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: January 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hoon Baek, Sun-Young Park, Sang-Kyu Oh, Ha-Young Kim, Jung-Ho Do, Moo-Gyu Bae, Seung-Young Lee
  • Patent number: 10529434
    Abstract: Devices and techniques for detecting power loss in NAND memory devices are disclosed herein. A memory controller may calibrate a first read level for a first physical page of a number of physical pages from an initial first read level position to a calibrated first read level position. The first read level may be between a first threshold voltage distribution corresponding to a first logical state of the at least four logical states and a second threshold voltage distribution corresponding to a second logical state of the at least four logical states. Also, the first threshold voltage distribution may be a highest threshold voltage distribution for the first physical page. The memory controller may calibrate a second read level for the first physical page that is lower than the first read level from an initial second read level position to a calibrated first read level position.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish Reddy Singidi, Ting Luo, Ashutosh Malshe, Preston Thomson, Jianmin Huang
  • Patent number: 10515672
    Abstract: A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 24, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinji Tanaka, Yuichiro Ishii, Masaki Tsukude, Yoshikazu Saito
  • Patent number: 10515135
    Abstract: Methods and apparatus are described for performing data-intensive compute algorithms, such as fast massively parallel general matrix multiplication (GEMM), using a particular data format for both storing data to and reading data from memory. This data format may be utilized for arbitrarily-sized input matrices for GEMM implemented on a finite-size GEMM accelerator in the form of a rectangular compute array of digital signal processing (DSP) elements or similar compute cores. This data format solves the issue of double data rate (DDR) dynamic random access memory (DRAM) bandwidth by allowing both linear DDR addressing and single cycle loading of data into the compute array, avoiding input/output (I/O) and/or DDR bottlenecks.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: December 24, 2019
    Assignee: XILINX, INC.
    Inventors: Jindrich Zejda, Elliott Delaye, Aaron Ng, Ashish Sirasao, Yongjun Wu
  • Patent number: 10476505
    Abstract: A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 12, 2019
    Assignee: Altera Corpoartion
    Inventor: Tony K. Ngai
  • Patent number: 10388330
    Abstract: Memory devices connected in a chain topology to a host controller that communicate using Low Voltage Differential Signaling (LVDS) and out-of-band signaling.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Mark Leinwander
  • Patent number: 10332590
    Abstract: Static random access memory (SRAM) bit cells employing current mirror-gated read ports for reduced power consumption are disclosed. In one aspect, an SRAM bit cell includes a read port employing a first transistor electrically coupled to a current sum line and to a current mirror circuit. A level of current that flows through the first transistor in response to voltage applied by the current mirror circuit correlates to a magnitude of the voltage. The read port includes a second transistor electrically coupled to the first transistor, to a driver circuit, and to an output node of a first inverter. Connecting the first and second transistors of the read port in this manner allows a voltage applied to the second transistor to generate a current that flows to the first transistor if the second transistor is activated. The current level depends on the voltage applied by the current mirror circuit.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Jianguo Yao
  • Patent number: 10224091
    Abstract: A system includes multiple memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address input circuit coupled to the address path that refreshes a first set of memory banks via the address path and, when the command address input circuit refreshes the first set of memory banks, activates a row of a second set of memory banks to store the data or read the data from the row of the second set of memory banks via the address path.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: March 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Joosang Lee
  • Patent number: 10210947
    Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: February 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Sano, Shunya Nagata, Shinji Tanaka
  • Patent number: 10163497
    Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Min Chan, Wei-Cheng Wu, Yen-Huei Chen
  • Patent number: 10141046
    Abstract: A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 27, 2018
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 10068647
    Abstract: A semiconductor memory device includes a first block that includes a first set of word lines, a second block that includes a second set of word lines and is adjacent to the first block in a first direction, a first transistor group adjacent to the first and second blocks in a second direction crossing the first direction, and a second transistor group adjacent to the first transistor group in the second direction. Each of the word lines in the first set is electrically connected to a transistor in the first transistor group, and each of the word lines in the second set is electrically connected to a transistor in the first transistor group.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: September 4, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Nobuaki Okada, Toshiki Hisada
  • Patent number: 10061542
    Abstract: Aspects of a memory and method for accessing the memory are disclosed. The memory includes a plurality of memory cells configured to support a read and write operation in a memory cycle in a first mode and a write only operation in the memory cycle in a second mode. The memory further includes a control circuit configured to generate a read clock for the read operation and a write clock for the write operation. The timing of the write clock is a function of the timing of the read clock in the first mode, and the timing of the memory cycle in the second mode.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 28, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Tony Chung Yiu Kwok, Nishith Nitin Desai, Changho Jung
  • Patent number: 10043571
    Abstract: SRAM structures are provided. A SRAM structure includes multiple SRAM cells arranged in multiple rows and multiple columns. The SRAM cells in the same row are divided into multiple groups. Each group includes a first SRAM cell and a second SRAM cell adjacent to the first SRAM cell. The first and second Vss lines and the first and second word-line landing pads are formed in a first metallization layer and extend parallel to a first direction. The third Vss line and the first word line are formed in a second metallization layer and extend parallel to a second direction. The first word-line landing pad is positioned within the rectangular shape of the first or second SRAM cell, and the second word-line landing pad is positioned within the rectangular shape of the second SRAM cell. The second metallization layer is positioned on the first metallization layer.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10043581
    Abstract: A memory circuit capable of implementing calculation operations, including: memory cells arranged in rows and in columns, each cell including: a data bit storage node, a read-out transistor connected by its gate to the storage node, and a selection transistor series-connected with the read-out transistor between a reference node and a conductive output track common to all the cells of a same column; and a control circuit configured to simultaneously activate the selection transistors of at least two cells of a same column of the circuit, and to read from the conductive output track of the column a value representative of the result of a logic operation having as operands the data of the two cells.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 7, 2018
    Assignee: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventors: Jean-Philippe Noel, Kaya Can Akyel
  • Patent number: 9972401
    Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: May 15, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Sano, Shunya Nagata, Shinji Tanaka
  • Patent number: 9905292
    Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: February 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Min Chan, Wei-Cheng Wu, Yen-Huei Chen
  • Patent number: 9881667
    Abstract: A memory cell includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: January 30, 2018
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 9876017
    Abstract: Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: January 23, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Stanley Seungchul Song, Zhongze Wang, Kern Rim, Choh Fei Yeap
  • Patent number: 9836404
    Abstract: Systems and techniques are disclosed for the mirroring of cache data from a storage controller to a storage class memory (“SCM”) device. The storage controller receives a write request, caches the write data, and mirrors the write data to the SCM device instead of to a cache of another storage controller. The SCM device stores the mirrored data in the SCM device. The storage controller acknowledges the write to the host. If the storage controller later fails, an alternate controller assumes ownership of storage volumes associated with the failed controller. Upon receipt of a new read request to the failed controller, the alternate controller checks the SCM device for a cache hit. If there is, the data is read from the SCM device; otherwise, it is read from the storage volume(s). The read data is cached at the alternate controller and then sent on to the requesting host.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: December 5, 2017
    Assignee: NetApp, Inc.
    Inventors: Sandeep Kumar R. Ummadi, Brian McKean, Gregory Friebus, Pradeep Ganesan
  • Patent number: 9824024
    Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, an arithmetic circuit, and a control circuit. The control circuit may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement first-in first-out modules, shift registers, or delay-line modules in addition to implementing memory modules with random access.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: November 21, 2017
    Assignee: Altera Corporation
    Inventors: Carl Ebeling, Jeffrey Christopher Chromczak, David Lewis
  • Patent number: 9812189
    Abstract: An apparatus is provided which comprises: a memory array; first logic to detect whether first and second word-lines (WL) for a row of the memory array are active; and second logic to deactivate one of the first and second WLs such that one of the first and second WLs is active for the row.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventors: Pramod Kolar, Wei-Hsiang Ma, Gunjan H. Pandya
  • Patent number: 9806083
    Abstract: Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: October 31, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Stanley Seungchul Song, Zhongze Wang, Kern Rim, Choh Fei Yeap
  • Patent number: RE47207
    Abstract: The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes a first and second inverters cross-coupled for data storage, each inverter includes a pull-up device (PU) and a plurality of pull-down devices (PDs); a plurality of pass gate devices configured with the two cross-coupled inverters; and at least two ports coupled with the plurality of pass gate devices (PGs) for reading and writing, wherein each of PU, PDs and PGs includes a fin field-effect transistor (FinFET), a ratio between a number of PDs in the SRAM cell and a number of PGs in the SRAM cell is greater than 1, and a number of FinFETs in the SRAM cell is equal to or greater than 12.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: January 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: RE47831
    Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: January 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koji Nii