Abstract: Disclosed herein is a multi-bank type semiconductor memory device which reduces current consumption of data lines. In the multi-bank type semiconductor memory device according to the present invention, the data lines between each memory bank and an input/output buffer are divided into horizontal data lines and vertical data lines. In addition, a high impedance driver is provided to drive horizontal local data of the horizontal data line to provide the horizontal local data as vertical local data of the vertical data line. Therefore, in the multi-bank type semiconductor memory device according to the present invention, even when the horizontal local data and the vertical local data are controlled at a low power voltage, degradation in overall operating speed hardly occurs. In addition, in the multi-bank type semiconductor memory device according to the present invention, current consumption in the data lines is significantly reduced.

Abstract: An image sensor includes a pixel array including pixels that are arranged in a matrix and respectively generate pixel signals, a row driver to drive the plurality of pixels row by row, a timing generator to generate a clock signal and address signals, a column driver to generate a plurality of column selection signals sequentially activated in response to the clock signal and the address signals, and a column array to receive the pixel signals through a plurality of column lines, perform an analog-to-digital conversion on the pixel signals, and sequentially output pixel data values through an output buffer. The column driver may include a clock tree including first delay elements and second delay elements to generate a plurality of delay clock signals, and a decoding circuit to generate the plurality of column selection signals.

Abstract: A memory in-pixel (MIP) circuit, a driving method of the MIP circuit, and an LCD panel fabricated using the MIP circuit. The MIP circuit comprising an input circuit, a control circuit and an output circuit. The input circuit brings the first input terminal and the second input terminal into conduction with a first node and a second node respectively in response to the first control signal of the first control terminal being active. The control circuit is configured to set and maintain the potential of a third node or a fourth node active based on the potential of the first node and the second node. The output circuit is configured to bring the output terminal into conduction with the first or second input terminal according to the potential of the third and the fourth node in response to the second control signal of the second control terminal being active.

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

Abstract: Apparatuses and methods for controlling driving signals are disclosed herein. Word drivers may be included in a memory device for driving hierarchical structured main word lines and subword lines. The subword lines may be driven by subword drivers that are activated by main word drivers and word drivers. In driving the word lines, driving signals are driven between an active state having an active voltage and an inactive state having an inactive voltage. The active voltage may be a voltage of a power supply and the inactive voltage may be an intermediate voltage between the active voltage and a reference voltage, such as ground. Driving the driving signals in such a manner may reduce current consumption of the memory device in some operations, for example, such as refresh operations.

Abstract: A method for manufacturing a three-dimensional (3D) memory structure and a 3D memory structure are disclosed. A recess is formed on a substrate, a 3D memory component is formed with a bottom in the recess, and then, a peripheral circuit is formed on the substrate outside the recess.

Abstract: A semiconductor device is provided. The semiconductor includes a plurality of memory cells arranged in rows and columns. The device further includes a plurality of primary word lines, each being connected to a first plurality of memory cells arranged in a row and a plurality of bit line pairs, each being connected to a second plurality of memory cells arranged in a column. The device further includes a word line driver circuit operative to select a first primary word line of the plurality of primary word lines and charge the selected first primary word line from a first end and a secondary word line operative to charge the selected first primary word line from a second end.

Abstract: A pixel circuit and a display device are provided. The pixel circuit includes: a first inverter circuit having an input terminal connected to a first node and an output terminal connected to a second node; a second inverter circuit having an input terminal connected to the second node and an output terminal connected to a third node; a first switching circuit configured to disconnect a connection between the first node and the third node when a first scanning signal is at an active level; and a control circuit configured to control a level of at least one of the first node and the second node according to a level control signal when the first scanning signal is at an active level. Based on this, it can help to avoid the output signal abnormality of the latch inside the pixel and enhance the working stability of the pixel circuit.

Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines.

Abstract: An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.

Abstract: A clock circuit includes a set of level shifters, and adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle, and is coupled to the adjustment circuit. The adjustment circuit is configured to generate a first clock output signal responsive to a first phase clock signal and a second phase clock signal of the first set of phase clock signals, and adjust the first clock output signal and a second duty cycle of the first clock output signal responsive to a set of control signals. The calibration circuit is coupled to the adjustment circuit, and configured to perform a duty cycle calibration of the second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration.

Abstract: A layout structure of a sub word line driver for use in a semiconductor memory device may be disclosed. The sub word line driver may include a first active region through which first and second main word lines pass. The sub word line driver may include first gates arranged in the first active region, and configured to receive word line selection signals.

Abstract: An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line.

Abstract: Aspects of the present disclosure eliminating the need for a memory device to have both a shifter that shifts input pin values from an input domain into a parity domain and another shifter that shifts a decoded command from the input domain into the parity domain. A memory device can achieve this by, when parity is being performed, shifting the input from the input pins into the parity domain prior to decoding the command. Using a multiplexer, the decoder can receive the command pin portion of the shifted input when parity checking is being performed and can receive the un-shifted command pin input when parity checking is not being performed. The decoder can use the command pin portion of the shifted input to generate shifted and decoded commands or can use the un-shifted command pin input to generate decoded commands.

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

Abstract: Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

Abstract: A non-volatile memory includes a memory array, a selecting circuit, a reference current generator and a sensing circuit. The memory array includes a top main array, a top corresponding array, a bottom main array and a bottom corresponding array. The top main array includes plural top bit lines. The top corresponding array includes plural inverted top bit lines. The bottom main array includes plural bottom bit lines. The bottom corresponding array includes plural inverted bottom bit lines. The selecting circuit is connected with the top main array, the top corresponding array, the bottom main array and the bottom corresponding array. The reference current generator and the sensing circuit are connected with the selecting circuit.

Abstract: Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.

Abstract: Methods and apparatuses are provided for driver circuits without voltage level shifters. An example apparatus includes a semiconductor device including a row decoder circuit that includes a driver circuit and a switching circuit. The driver circuit is configured to receive an input signal having a first logical value, a first voltage signal, and a configurable power signal. The driver circuit is further configured to provide an output signal having the first logical value based on the first signal having the first logical value. A voltage level of the input signal is based on the first voltage signal and a voltage level the output signal is based on the configurable voltage signal. The switching circuit is configured to receive the first voltage signal and a second voltage signal and to provide the configurable voltage signal having a voltage level of one of the first voltage signal or the second voltage signal.

Abstract: The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described.

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.

Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.

Abstract: Methods of operating a memory include reading a particular grouping of memory cells using a read voltage having a particular voltage level, determining a number of memory cells of a subset of memory cells of the particular grouping of memory cells having a particular data state, and, if the number of memory cells of the subset of memory cells having the particular data state is less than a particular threshold, adjusting a voltage level of the read voltage in response to the number of memory cells of the subset of memory cells having the particular data state and reading the particular grouping of memory cells using the read voltage having the adjusted voltage level.

Abstract: A memory device includes a memory cell array, a row decoder, a multi-column decoder, a gating circuit, and an input/output data driving circuit. The memory cell array includes a plurality of memory cells arranged to form a plurality of rows and a plurality of columns. The row decoder generates a row selection signal based on a row address to select a target row from the rows. The multi-column decoder generates a multi-column selection signal based on a column address and column selection information to select a plurality of target columns from columns included in the target row at a time. The gating circuit selects the target columns at a time based on the multi-column selection signal. The input/output data driving circuit writes input data to the target columns at a time or outputs data stored in the target columns at a time as output data through the gating circuit based on the multi-column selection signal and a data mask signal.

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

Abstract: Systems and methods using a three-dimensional memory device with a number of memory cells disposed vertically in a number of pillars arranged along a horizontal direction can be used in a variety of applications. In various embodiments, pillars of memory cells may be disposed between lower and upper digitlines respectively coupled to different sense amplifiers to provide read/write operations and refresh operations. In various embodiments, a three-dimensional memory device having an array of memory cells vertically arranged in pillars may include a sense amplifier and digitline with a static random access memory cache, where the static random access memory cache is disposed below the array of memory cells in the same die. Additional apparatus, systems, and methods are disclosed.

Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.

Abstract: A semiconductor memory device suppressing a shift between data output from a plurality of memory chips and a DQS signal. A flash memory device of the disclosure includes memory chips, a plurality of IO terminals capable of inputting and outputting data, and a DQS terminal. Each of the memory chips includes an output circuit used to output data and a DQS output circuit. The DQS output circuit is used to output the DQS signal for defining a timing of the data output from the output circuit. The DQS signal output from each of the DQS output circuits of the memory chips is supplied to the DQS terminal.

Abstract: Apparatuses and methods for providing driving signals in semiconductor devices are described. An example apparatus includes a plurality of memory cell mats including a plurality of word lines and a word line driver coupled to the plurality of word lines of the plurality of memory cell mats. The word line driver is configured, responsive to a row active command, to provide a first voltage to a selected word line of the plurality of the word lines of a selected memory cell mat of the plurality of memory cell mats, provide a second voltage different from the first voltage to each of unselected word lines of the plurality of the word lines of the selected memory cell mats of the plurality of memory cell mats, and provide no voltage to each of the plurality of word lines of each of unselected memory cell mats of the plurality of memory cell mats.

Abstract: To provide a programmable logic device in which the number of elements per bit in a memory array can be reduced and with which power consumption or operation frequency can be estimated accurately at a testing stage. Provided is a programmable logic device including a plurality of programmable logic elements and a memory array which stores configuration data that determines logic operation executed in the plurality of programmable logic elements. The memory array includes a plurality of memory elements. The memory element includes a node which establishes electrical connection between the programmable logic element and the memory array, a switch for supplying charge whose amount is determined by the configuration data to the node, holding the charge in the node, or releasing the charge from the node, and a plurality of wirings. Capacitance is formed between the node and the wiring.

Abstract: A memory device is provided. The memory device includes at least one memory bank, at least one first address decoder set, and at least one second address decoder set. Each of the at least one memory bank includes a plurality of memory cell arrays. Each of the at least one second address decoder set includes a plurality of second address decoders. The at least one second address decoder set receives a plurality of column select lines to perform an access operation on memory cells of the memory cell arrays. The column select lines are divided into a plurality of column select line groups, and each of the column select line groups is assigned to the second address decoder corresponding thereto, wherein the number of the column select lines allocated to each of the column select line groups is less than a total number of the column select lines.

Abstract: Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

Abstract: A memory system includes: a first cell array including a plurality of memory cells; and a second cell array including a plurality of memory cells; and an address operation circuit suitable for generating a first cell array address, the first cell array address used for accessing at least one first cell in the first cell array, by adding a first value to an address, and generating a second cell array address, the second cell array address used for accessing at least one second cell in the second cell array, by adding a second value to the address.

Abstract: A semiconductor device may include a power supply circuit, a word line control circuit, and a memory circuit. The power supply circuit may drive a pre-charge voltage to a level of an external voltage based on a write initialization signal which is enabled if a command has a predetermined level combination. The word line control circuit may generates two or more word line selection signals that are sequentially counted based on the write initialization signal. The memory circuit may sequentially select a plurality of word lines based on the word line selection signals. The memory circuit may drive bit lines of memory cells connected to the selected word line to the pre-charge voltage. The memory circuit may store data, which are loaded on the bit lines to have a level of the pre-charge voltage, into the memory cells connected to the selected word line.

Abstract: Some embodiments relate to a memory device including first and second conductive lines extending generally in parallel with one another within over a row of memory cells. A centerline extends generally in parallel with the first and second conductive lines and is spaced between the first and second conductive lines. A first plurality of conductive line segments is over the first conductive line. Conductive line segments of the first plurality of conductive line segments are coupled to different locations on the first conductive line. A second plurality of conductive line segments are disposed over the second conductive line, and are coupled to different locations on the second conductive line.

Abstract: A transmitting device includes an output node, at least one driver circuit and transition equalization circuitry. The driver circuit drives an output data signal including a data transition onto the output node. The output of the transition equalization circuitry is coupled to the output node. The transition equalization circuitry begins to drive the output node at the data transition and ends driving of the output node a pre-determined delay after beginning to drive the output node. The transition equalization circuitry drives the output node by injecting current onto the output node if the data transition is a positive transition, and sinking current from the output node if the data transition is a negative transition.

Abstract: A time-of-flight (TOF) sensor includes a light source, a plurality of avalanche photodiodes, and a plurality of pulse generators. Control circuitry is coupled to the light source, the plurality of avalanche photodiodes, and the plurality of pulse generators, and the control circuitry includes logic that when executed by the control circuitry causes the time-of-flight sensor to perform operations. The operations include emitting the light from the light source, and receiving the light reflected from an object with the plurality of avalanche photodiodes. A plurality of pulses is output from the individual pulse generators corresponding to the individual avalanche photodiodes that received the light, and a timing signal is output when the plurality of pulses overlap temporally. A time is calculated when a first avalanche photodiode in the plurality of avalanche photodiodes received the light.

Abstract: A layout structure of a sub word line driver for use in a semiconductor memory device is disclosed. The sub word line driver may include a first active region through which first and second main word lines pass. The sub word line driver may include first gates arranged in the first active region, and configured to receive word line selection signals. Each of the first gates is formed to have a substantially square shape.

Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.

Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines.

Abstract: A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.

Abstract: A semiconductor memory apparatus includes a write control circuit suitable for generating a write cancel signal and a rewrite signal in response to a voltage level of a write voltage in a write operation, and a driving circuit suitable for transferring data to a data storage region in response to the write cancel signal and the rewrite signal in the write operation.

Abstract: According to one general aspect, an apparatus may include a global bit line, and a plurality of memory banks. The global bit line may be configured to facilitate a memory access. Each memory bank may include a local keeper-precharge circuit coupled between a power supply and the global bit line, and a control circuit configured to control, at least in part, the local keeper-precharge circuit.

Abstract: The present invention discloses a mixed three-dimensional memory (3D-Mx). It comprises memory arrays (or, memory blocks) of different sizes. In a 3D-Mx with mixed memory blocks, the memory blocks with different sizes are formed side-by-side. In a 3D-Mx with mixed memory arrays, a plurality of small memory arrays are formed side-by-side underneath a single large memory array.

Abstract: A method and an apparatus are provided for selecting between a plurality of instruction sets available to a microprocessor. An instruction fetch address is supplied. At least one predetermined bit of the instruction fetch address is used to select between the instruction sets. Once an instruction set has been selected, instructions may be fetched and decoded with a decoding scheme appropriate to the instruction set.