Abstract: The present invention is a means and method for constructing and operating a 3-D array and, more particularly, a 3-D memory array. This array can be manufactured as a monolithic integrated circuit at low cost by virtue of the limited number of steps per layer of memory elements. The low number of steps results by having the storage elements separated by a resistive component as opposed to an active component. The 3-D array is in essence, an array of 2-D resistive arrays (row-planes) having a long dimension (typically along the rows) and a short dimension (typically in the direction of the stacked layers). Any one row-plane can be isolated from the rest and be accessed independently from all of the other row-planes in the 3-D array. This makes it possible to operate and analyze a single row-plane as a mostly stand-alone circuit. The present invention lends itself to single bit accesses as well as simultaneous multiple bit accesses.

Abstract: A semiconductor apparatus includes a first memory die; a second memory die; and a processor configured to provide an external command, an external start address and an external end address which are associated with a read operation, to the first memory die, and provide an external command, an external start address and an external end address, which are associated with a write operation, to the second memory die, in the case where data stored in the first memory die is to be transferred to and stored in the second memory die.

Abstract: Circuits and systems for concurrently programming a plurality of OTP cells in an OTP memory are disclosed. Each OTP cell can have an electrical fuse element coupled a program selector having a control terminal. The control terminals of a plurality of OTP cells can be coupled to a plurality of local wordlines, and a plurality of the local wordlines can be coupled to at least one global wordline. A plurality of banks of bitlines can have each bitline coupled to a plurality of the OTP cells via the control terminal of the program selector. A plurality of bank selects can enable turning on the wordlines or bitlines in a bank. A plurality of the OTP cells can be configured to be programmable concurrently into a different logic state by applying voltages to at least one selected global wordline and at least one selected bitline to a plurality of the selected OTP cells in a plurality of banks, if a plurality of banks are enabled.

Abstract: The semiconductor device includes an internal command generator and an internal address generator. The internal command generator generates first and second command latch signals from first and second internal clock signals in response to an external control signal and latches a command signal in response to the first and second command latch signals to generate a synthesized internal command signal. The internal address generator generates first and second address latch signals from the first and second internal clock signals in response to the external control signal and latches an address signal in response to the first and second address latch signals to generate a synthesized internal address signal.

Abstract: Systems and methods of memory and memory operation are disclosed, such as providing a circuit including a local address driver voltage source for memory decoding. In one exemplary implementation, an illustrative circuit may comprise a first buffer and a capacitor. The first buffer may comprise a power input and a ground input. The capacitor may comprise a first terminal connected to the power input of the first buffer and a second terminal connected to the ground input of the first buffer. When the first buffer draws a current from the power input, at least a portion of the current may be supplied by the capacitor.

Abstract: Embodiments of the present invention include a NOR-type flash memory device capable of reducing or eliminating program malfunctions. In some embodiments, the device includes a memory array, row selection circuit, column selection circuit, and program driver circuit. The memory array includes a memory sector having a first sector bit line and a second sector bit line. The memory array also includes a plurality of flash memory cells disposed on a matrix structure having a plurality of cell bit lines and a plurality of word lines arranged sequentially. The cell bit lines are alternately defined as first cell bit lines and second cell bit lines in sequential order. The first cell bit lines are connected to the first sector bit line in response to column selection signals thereof, and the second cell bit lines are connected to the second sector bit line in response to column selection signals thereof.

Abstract: A semiconductor memory comprises a plurality of sub banks each including one or more rows of memory bit cells connected to a set of local bit lines, wherein the sub banks share a same set of global bit lines for reading/writing data from/to the memory bit cells of the sub banks. The semiconductor memory chip further comprises a plurality of switch elements for each of the sub banks, wherein each of the switch elements connects the local bit line and the global bit line of a corresponding one of the memory bit cells in the sub bank for data transmission between the local bit line and the global bit line. The semiconductor memory chip further comprises a plurality of bank selection signal lines each connected to the switch elements in a corresponding one of the sub banks, wherein the bank selection signal lines carry a plurality of bank selection signals to select one of the sub banks for data transmission between the local bit lines and the global bit lines.

Abstract: The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable.

Abstract: An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.

Abstract: A method comprises selecting a memory cell included in a memory cell array in which data is to be stored. The memory cell array is connected with a logic gate array. The memory cells of the memory cell array are individually coupled with a corresponding logic gate of the logic gate array by a separate word line output. The method also comprises communicating a write row output signal to the logic gate array. The write row output signal is communicated from a write address row decoder to the logic gate array. The write address row decoder has a plurality of write row outputs coupled with the logic gate array. The method further comprises communicating a write column output signal to the logic gate array. The write column output signal is communicated from a write address column decoder to the logic gate array.

Abstract: A method includes causing, by a first circuit, a first signal transition at a first node based on a clock signal. A first edge, from a first level to a second level, of a word line signal is generated responsive to the first signal transition. A second signal transition at a second node is caused by a second circuit based on the clock signal. The second circuit and the first circuit are configured to cause the second signal transition to occur later than the first signal transition by a delay time. A first edge, from a third logic level to a fourth level, of a tracking word line signal is generated responsive to the second signal transition.

Abstract: Disclosed herein is an apparatus that includes: a first terminal configured to receive a serial write data signal that includes at least four bits transferred in series with each other; a second terminal configured to receive a data strobe signal; a control circuit configured to produce a plurality of internal data strobe signals in response to the data strobe signal; and a serial-to-parallel conversion circuit configured to respond to the data strobe and internal data strobe signals to convert the serial write data signal into a parallel write data signal that includes at least four bits produced in parallel to each other.

Abstract: A system for using selectable-delay bipolar logic circuitry within the address decoder of a MOS-based memory includes a MOS-based memory, which includes an array of a plurality of memory cells configured to store data; an address decoder including bipolar logic circuitry, where the address decoder is configured to accept a word including a plurality of bits and access the array of memory cells using the word; where the bipolar logic circuitry includes a plurality of bipolar transistor devices, where at least one bipolar transistor device has an adjustable gate bias and is configured to accept an input, wherein the gate bias is adjusted based on the input, where the gate bias determines a selectable gate delay.

Abstract: A display device having a particular power controller circuit is disclosed. In one aspect, the display includes a plurality of pixels, and a power controller for supplying a first power source voltage and a second power source voltage for providing a driving current of the plurality of pixels wherein the power controller connects at least one of a first high level voltage, a ground, and a capacitor to a first node connected to the first power source voltage, and connects one of a second high level voltage and the ground to a second node connected to the second power source voltage.

Abstract: A memory circuit includes at least one bit cell that receives a word line, complementary bit lines and an array supply voltage and a word line suppression circuit. The word line suppression circuit includes two PFETs with their drains connected to the word line and their sources connected to the array supply voltage and an NFET with its source connected to ground and its drain connected to the word line. The NFET is inactivated before the PFETs are activated. One of the PFETs is activated before the other PFET is activated so as to control the slew rate of the word line and improve the static noise margin of the at least one bit cell.

Abstract: A system, method, and memory device embodying some aspects of the present invention for remapping external memory addresses and internal memory locations in stacked memory are provided. The stacked memory includes one or more memory layers configured to store data. The stacked memory also includes a logic layer connected to the memory layer. The logic layer has an Input/Output (I/O) port configured to receive read and write commands from external devices, a memory map configured to maintain an association between external memory addresses and internal memory locations, and a controller coupled to the I/O port, memory map, and memory layers, configured to store data received from external devices to internal memory locations.

Abstract: According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.

Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.

Abstract: Disclosed herein a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, and the device further includes a driver configured to drive a selected one of the word lines from an inactive level to an active and to drive the selected one of the word lines from the active level to an intermediate level at a first rate and from the intermediated level to the inactive level at a second rate. The intermediate level is between the active and inactive levels, and the first rate is greater than the second rate.

Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.

Abstract: A key holder for holding a variety of different physical keys and wireless key devices can comprise a container for holding insert components that are selectively removable and addable to the container. The insert components can comprise one or more key blades that are attached to the container such that a portion of each of the one or more key blades angularly rotates out of the container when in use. Additionally, one or more buttons can be integrated into the container. The buttons are configured to lock one or more of the insert components into place. The holder can also comprise a wireless module that is in communication with a processing unit disposed within the key container.

Abstract: Disclosed herein is a semiconductor device comprising local bit lines, a global bit line, local switch control lines, main switch control lines, hierarchical switches controlling electrical connections between the local bit lines and the global bit line in response to potentials of the local switch control lines, local switch drivers driving the local switch control lines in response to potentials of the main switch control lines, and main switch drivers selectively activating the main switch control lines.

Abstract: A latch circuit may include a plurality of latches configured to operate in response to power supplied to a pull-up power supply node and a pull-down power supply node, a delay unit configured to generate a 1st delayed reset signal and a 2nd delayed reset signal by delaying a 1st reset signal and a 2nd reset signal, a power supply unit configured to supply identical power to the pull-up power supply node and the pull-down power supply node in response to the activated 1st reset signal or the activated 2nd reset signal, a 1st reset unit configured to reset a plurality of latches to a 1st level in response to the 1st delayed reset signal and a 2nd reset unit configured to reset the plurality of latches to a 2nd level in response to the 2nd delayed reset signal.

Abstract: A write-assisted memory. The write-assisted memory includes a word-line decoder that is implemented within a low VDD power domain. The write-assisted memory also includes a write-segment controller that is partially implemented within the low VDD power domain and is partially implemented within a high VDD power domain. The write-assisted memory further includes a local write word-line decoder that is implemented within the high VDD power domain.

Abstract: Voltage balancing for a memory cell array is provided. One example method of voltage balancing for a memory array can include activating an access node coupled to a row of a memory array to provide voltage to the row of the memory array, activating a stabilizing transistor coupled to the row of the memory array to create a feedback loop, and activating a driving node coupled to a column of the memory array, wherein activating the driving node deactivates the stabilizing transistor once the column reaches a particular voltage potential.

Abstract: The present invention discloses a three-dimensional offset-printed memory (3D-oP). Compared with a conventional three-dimensional mask-programmed read-only memory (3D-MPROM), it has a lower data-mask count and thereby a lower data-mask cost. The mask-patterns for different memory levels/bits-in-a-cell are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to said data-mask. Accordingly, data-patterns are printed into different memory levels/bits-in-a-cell from a same data-mask.

Abstract: Embodiments of the present disclosure include an emitter driver configured to be capable of addressing substantially 2N nodes with N cable conductors configured to carry activation instructions from a processor. In an embodiment, an address controller outputs an activation instruction to a latch decoder configured to supply switch controls to activate particular LEDs of a light source.

Abstract: A resistance changing memory array architecture includes an array of resistance changing memory unit cell arranged in rows and column, wherein at least two adjacent columns share a sense bit line, and a control line individually associated with each column, wherein a current control component within each unit cell along a respective column is coupled to a respective control line. The architecture further includes a plurality of word lines each associated with a respective row, wherein a resistance changing element associated with each unit cell along a respective row is coupled to a respective word line.

Abstract: Among other things, techniques and systems are provided for activating a memory cell of a memory arrangement in preparation for at least one of a read operation or write operation. The memory arrangement comprises a word-line driver comprising at least a first input terminal and a second input terminal. The first input terminal is operably coupled to a first decoder and the second input terminal is operably coupled to a second decoder. When the word-line driver senses a first voltage at the first input terminal and a second voltage at the second input terminal, the word-line driver outputs a gate voltage signal which activates the memory cell.

Abstract: Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include self-timed pulse generator circuitry, first input latch circuitry, read/write control circuitry, and second input latch circuitry. According to further implementations herein, fast address access for read and write may be provided in the same cycle via a self-timed pulse in the input latch circuit and/or via associated control/scheme from the control circuit.

Abstract: A memory structure and a method for forming the same are provided. The memory structure comprises: a substrate; a plurality of channel structures formed on the substrate, in which the plurality of channel structures are parallel with each other, each channel structure comprises a plurality of single crystal semiconductor layers and a plurality of oxide layers alternately stacked in a direction perpendicular to the substrate, and at least one of the plurality of oxide layers is a single crystal oxide layer; and a plurality of gate structures matched with the plurality of channel structures, in which each gate structure comprises a gate dielectric layer immediately adjacent to the plurality of channel structures and a gate electrode layer immediately adjacent to the gate dielectric layer.

Abstract: Some aspects of the present disclosure a method. In this method, a wordline voltage is provided to a wordline, which is coupled to a plurality of memory cells. A boost enable signal is provided. The state of the boost enable signal is indicative of whether the wordline voltage at a predetermined position on the wordline has reached a non-zero, predetermined wordline voltage. The wordline voltage is selectively boosted to a boosted wordline voltage level based on the boost enable signal.

Abstract: Techniques are generally described related to a flash-based buffer management strategy. One example method for managing a buffer for a computer system may include monitoring, by a buffer management module, a plurality of operations being executed on the computer system and utilizing a plurality of buffer pages of the buffer. The example method may also include, upon a determination that the buffer is full, identifying a specific buffer page from the plurality of buffer pages for eviction, wherein the specific buffer page is selected based on a page state of the specific buffer page and a page hotness prediction for the specific buffer page. The example method may further include evicting the specific buffer page from the buffer.

Abstract: A three-dimensional (3-D) nonvolatile memory device includes a channel layer protruded from a substrate, a plurality of memory cells stacked along the channel layer, a source line coupled to the end of one side of the channel layer, a bit line coupled to the end of the other side of the channel layer, a first junction interposed between the end of one side of the channel layer and the source line and configured to have a P type impurity doped therein, and a second junction interposed between the end of the other side of the channel layer and the bit line and configured to have an N type impurity doped therein.

Abstract: An SRAM bit cell comprises a first inverter including a PMOS transistor and an NMOS transistor, and a second inverter including a PMOS transistor and an NMOS transistor. The first and second inverters are cross-coupled to each other. A plurality of pass transistors couple the inverters to bit lines. Approximately one-half of a supply voltage is provided to the bit lines during pre-charge operations.

Abstract: A semiconductor memory device may include a memory cell array, a plurality of first sub word line drivers, and a plurality of second sub word line drivers. The memory cell array may comprise a plurality of sub cell arrays, a plurality of first word lines and a plurality of second word lines, wherein a loading of each of the first word lines is greater than a loading of each of the second word lines. Each of the plurality of first sub word line drivers may be connected to drive a corresponding one of the plurality of first word lines, wherein each of the first sub word line drivers has a first driving capability. Each of the plurality of second sub word line drivers may be connected to drive a corresponding one of the plurality of second word lines, wherein each of the second sub word line drivers has a second driving capability different from the first driving capability.

Abstract: In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.

Abstract: The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data output portion receives an input control signal, a latch pulse signal, and a first output control signal. The data output portion receives an input clock signal in response to the input control signal and the latch pulse signal to generate a shift clock signal, and the data output portion also shifts the first output control signal in response to the shift clock signal to generate a second output control signal.

Abstract: A method and circuit for implementing sense amplifiers for sensing local write driver with bootstrap write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a sense amplifier used in both read and write operations with a write assist boost circuitry. The sense amplifier captures and amplifies write data at a selected SRAM cell column and drives the write data onto local bit lines. The write assist boost circuitry temporarily supplies an increased device voltage differential to the SRAM cell during write operations to significantly increase SRAM cell write ability.

Abstract: A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other.

Abstract: A membrane electrode assembly comprises an ion-conducting membrane; a first electrocatalyst layer having a surface facing the membrane; a first electronically-conducting porous gas diffusion substrate facing the other surface of the first electrocatalyst layer; and a first film member interposed between the membrane and the first electrocatalyst layer. The first electrocatalyst layer has an edge region and a central region, and the first film member contacts the edge region and not the central region. A first adhesive layer is present on the surface of the first film member facing the first electrocatalyst layer, and the first adhesive layer adheres the first film member to the first electrocatalyst layer, impregnates through the first electrocatalyst layer, and impregnates into the first gas diffusion substrate.

Abstract: A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays.

Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

Abstract: In a flash memory, erase blocks containing shorted or broken word lines may be used, at least in part, to store user data. Such blocks may use different parameters to those used by non-defective blocks, may be subject to different wear leveling, and may store data selected to reduce the number of access operations.

Abstract: A word line driver includes a first transistor electrically connected to a first voltage supply node and a word line, a second transistor electrically connected to a second voltage supply node and the word line, a first switch electrically connected to the first voltage supply node and a bulk electrode of the second transistor, and a second switch electrically connected to the second voltage supply node and the bulk electrode of the second transistor.

Abstract: A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry.

Abstract: A method for accessing a semiconductor device having a memory array, the method includes receiving a mode register command to set a command latency value in a mode register, receiving a chip select signal, activating a command receiver in response to the chip select signal, receiving, with the command receiver, an access command with a first latency from the chip select signal equal to the command latency value, accessing the memory array in response to the access command, and deactivating the command receiver with a second latency from the chip select signal equal to a deactivation latency value.

Abstract: A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the semiconductor substrate and a body region and a second source/drain region are formed within the semiconductor pillar. A first gate is coupled to a first side of the semiconductor pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region.

Abstract: Devices, methods, and circuits for row driver architectures that can improve an existing row driver circuit including a boosting capacitor and a level shifter circuit. For example, the improvement can include a decoupling inverter that decouples the level shifter from the boosting capacitor, which can reduce the time for the row driver to turn on and drive appropriate voltages to the matrix array.

Abstract: A system including a state set module to arrange states of a memory cell in three sets. The memory cell stores three bits when programmed to a state. Each set includes three rows of bits. In a set, a row includes one of the three bits of the states. The first, second, and third rows of the first, second, and third sets include a first number of state transitions. The second, third, and first rows of the first, second, and third sets include a second number of state transitions. The third, first, and second rows of the first, second, and third sets include a third number of state transitions. A write module writes first, second, and third portions of data to a plurality of memory cells, each memory cell storing the three bits when programmed to a state, using states selected respectively from the first, second, and third sets.