Using Selective Matrix Patents (Class 365/231)
  • Patent number: 10770127
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Shore, Jiyun Li
  • Publication number: 20150103613
    Abstract: The present disclosure includes memory devices and methods of operating the same. One such device includes an array of groups of memory cells, a group selector configured to select a particular group of memory cells from within the array, and a cell selector configured to select a particular memory cell from within the selected particular group of memory cells.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Scott E. Sills
  • Patent number: 8982605
    Abstract: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: March 17, 2015
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Se Ho Lee
  • Publication number: 20150071021
    Abstract: A method of accessing rows and columns stored in a memory system that include memory chips that can be individually addressed and accessed is described. In order to leverage this capability, prior to performing a row-write request on the memory system, a computer system may transform the rows and the columns in a matrix. In particular, in response to receiving a row-write request to write to a row N in the matrix, the computer system rotates the row right by N elements, and writes the row in parallel to address N of the memory chips in the memory system. Similarly, in response to receiving a column-write request to write to column M in the matrix, the computer system rotates the column right by M elements, and writes the column in parallel to the memory chips in the memory system.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: Oracle International Corporation
    Inventors: Philip Amberg, Alex Chow, Robert David Hopkins, II
  • Patent number: 8842461
    Abstract: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: September 23, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hae Chan Park, Se Ho Lee
  • Patent number: 8814792
    Abstract: A vital-signs patch for a patient monitoring system that includes a housing containing a sensor that makes physiological measurements of a patient, a transmitter, a receiver, a memory, and a processor. The processor periodically takes a measurement from the sensor, converts the measurement to a data record, and stores the data record in the memory. Upon receipt of a signal from another device, the processor retrieves at least a portion of the data record, converts the retrieved portion of the data record to a vital-sign signal, and causes the transmitter to transmit the vital-sign signal to the other device.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: August 26, 2014
    Assignee: CareFusion 303, Inc.
    Inventors: Mark Raptis, Amir Jafri, Ganesh Kathiresan, Alison Burdett
  • Patent number: 8811082
    Abstract: A semiconductor memory device includes word lines stacked over a substrate having a plurality of memory block regions, select lines arranged over the word lines, vertical channel layers formed to penetrate through the select lines and the word lines and extending to the substrate, and a charge trap layer disposed between the word lines and the vertical channel layers, wherein the stacked word lines are separated by memory block groups that each include two or more memory block regions.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: August 19, 2014
    Assignee: SK Hynix Inc.
    Inventors: Tae Heui Kwon, You Sung Kim
  • Patent number: 8797822
    Abstract: A method for accessing a plurality of DRAM devices each having a plurality of banks, includes determining an operating mode for the plurality of DRAM devices, providing a chip selection address and a bank address with an active command to activate a first bank in a first one of the plurality of DRAM devices and, while the first bank in the first one of the plurality of DRAM devices is activated, one or more first banks in remaining DRAM devices of the plurality of DRAM devices are: not activated if the operating mode is determined to be a logical rank address mode, and possibly activated if the operating mode is determined to be a physical rank address mode, and subsequently providing at least a bank address with a column command to access the first bank in the first one of the plurality of DRAM devices.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: August 5, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Homare Sato
  • Patent number: 8723878
    Abstract: A graphics memory device includes a memory array configured to store data for a display device comprising b*y rows by a*x columns of pixels, where b>a. The memory array is arranged in a*y rows by b*x columns of memory locations. Each memory location is adapted to store n-bit image data for one of the pixels of the display device. A memory location remapping circuit is adapted to map image data stored in the b*x columns of memory locations in the memory device to the a*x columns of the display device.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongkon Bae, Kyuyoung Chung
  • Patent number: 8699294
    Abstract: A nonvolatile memory device includes a plurality of memory blocks vertically arranged, first and second row decoder groups configured to couple first and second local global word lines and the word lines of upper memory blocks among the plurality of memory blocks, third and fourth row decoder groups configured to couple third and fourth local global word lines and the word lines of lower memory blocks among the plurality of memory blocks, a first local decoder switch configured to couple a plurality of global lines and the first or second local global word lines, a second local decoder switch configured to couple the plurality of global lines and the third or fourth local global word lines, and a high voltage generator configured to supply operating voltages to the plurality of global word lines.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: April 15, 2014
    Assignee: SK Hynix Inc.
    Inventor: Sang Hwa Chung
  • Patent number: 8670275
    Abstract: The apparatuses and methods described herein may comprise a memory array formed on a semiconductor substrate and including a plurality of cells associated with a plurality of word lines. The memory array may comprise a plurality of sub-blocks including a first sub-block and a second sub-block. Each sub-block may comprise a memory cell portion of the plurality of memory cells associated with a corresponding word line portion of the plurality of word lines. The memory cell portions in the first and second sub-blocks may be independently addressable with respect to each other such that a second operation can be performed on at least one memory cell of the memory cell portion of the second sub-block responsive to suspending a first operation directed to at least one memory cell of the memory cell portion of the first sub-block.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: March 11, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Emanuele Confalonieri
  • Patent number: 8625381
    Abstract: Provided is a stacked semiconductor device including n stacked chips. Each chip includes “j” corresponding upper and lower electrodes, wherein j is a minimal natural number greater than or equal to n/2, and an identification code generator including a single inverter connecting one of the j first upper electrode to a corresponding one of the j lower electrodes. The upper electrodes receive a previous identification code, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code. The current identification code is applied through the j lower electrodes and corresponding TSVs to communicate the current identification code to the upper adjacent chip.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho-Cheol Lee
  • Patent number: 8593858
    Abstract: A driving method by which stored data can be retained even with no power supply and the number of writing operations is not limited is provided. The variation of a writing potential to a memory element is suppressed to improve the reliability according to a new driving method. According to the driving method of a semiconductor device, in writing data, the writing potential is increased step-by-step while verifying the reading current, and the result of the reading current is used for the writing current. That is, data writing is performed while verifying whether data writing is performed with an accurate potential. Accordingly, data writing can be performed with high reliability.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: November 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koichiro Kamata
  • Patent number: 8537622
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells provided in a matrix and having a charge storage layer, a plurality of word lines provided on the charge storage layer, and an application section. When reading data from a selected memory cell selected from the plurality of memory cells, the application section applies a voltage having an opposite polarity to the voltage applied to a selected word line to non-selected word lines arranged on both adjacent sides of the selected word line.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: September 17, 2013
    Assignee: Spansion LLC
    Inventors: Fumiaki Toyama, Yukihiro Utsuno
  • Patent number: 8526264
    Abstract: A memory includes memory cells, data lines, block select lines, and selection circuitry. The data lines provide data to and from the memory cells and may be grouped into blocks. Each block includes data lines. Each of the block select lines is associated with a respective one of the blocks. The selection circuitry is select a block in response to a respective block select line and the memory performs a memory operation using the selected bit line block.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 3, 2013
    Assignee: STMicroelectronics International N.V.
    Inventors: Anuj Parashar, Marc Vernet
  • Patent number: 8477555
    Abstract: Asymmetric select and deselect drivers are provided for select lines driven to a resistive cross-point memory array. An address may be fully decoded to determine the active select driver, but a partial decode may be performed for the deselect drivers. Some embodiments may manage the odd and even deselect drivers as two sets of drivers and some embodiments may use sub-optimal transistors as the deselect drivers to save die area. Some embodiments may implement the deselect drivers as modified memory elements to reduce die area further.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 2, 2013
    Assignee: Intel Corporation
    Inventor: Hernan A. Castro
  • Patent number: 8379428
    Abstract: A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: February 19, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Ogawa, Akihisa Yamaguchi
  • Patent number: 8355270
    Abstract: When an I/O number is 8 bit, a semiconductor device includes a first memory mat that is selected when X13 is (0) and X11 and X12 are (0, 0), a second memory mat that is selected when X13 is (1) and X11 and X12 are (0, 0), and a third memory mat that is selected irrespective of a value of X13 when X11 and X12 are (0, 0). When the I/O number is 16 bit, X13 is ignored, and the first to third memory mats are selected when X11 and X12 are (0, 0). In this manner, because the third memory mat is shared between so-called upper side and lower side, control is prevented from becoming complicated and an area is prevented from increasing.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: January 15, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Yuji Nakaoka, Hiroshi Ichikawa
  • Patent number: 8203903
    Abstract: A main decoding circuit includes a shared column selection signal generating unit and a switching unit. The shared column selection signal generating unit receives a column decoding signal to generate a shared column selection signal. The switching unit selectively provides the shared column selection signal to one of a column selection line of a first memory bank and a column selection line of a second memory bank in response to a bank selection signal.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: June 19, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung Wook Kwak, Kae Dal Kwak
  • Patent number: 8194490
    Abstract: Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: June 5, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hung Chen, Chin-Huang Wang, Yen-Chieh Huang, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
  • Patent number: 8130550
    Abstract: A non-volatile memory comprising a NOR block with a first sub-block independently addressable from a second sub-block, the two sub-blocks sharing a physical substrate of the NOR block, and a first memory to store execution status information to reflect an erase status of the first sub-block. A method to selectively erase the first sub-block while inhibiting the second sub-block from erasing, comprising updating execution status information associated with the first sub-block and resuming erasing upon an occurrence of an interruption event depending on the indication of the execution status information.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: March 6, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Emanuele Confalonieri
  • Patent number: 8027209
    Abstract: A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation.
    Type: Grant
    Filed: September 20, 2009
    Date of Patent: September 27, 2011
    Assignee: SanDisk 3D, LLC
    Inventors: Tianhong Yan, Luca Fasoli
  • Patent number: 8004901
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells that are provided in a matrix and that have a charge storage layer made of an insulating film that is provided on a semiconductor substrate and a plurality of word lines that are provided on the charge storage layer. A plurality of memory cells that are arranged in a single line among the plurality of memory cells arranged in the matrix are coupled to the same word line. The semiconductor device further includes an application section that when reading data from a selected memory cell selected from the plurality of memory cells, applies a voltage to a selected word line to be coupled to the selected memory cell among the plurality of word lines. The application section applies a voltage that has a polarity that is opposite to the voltage applied to the selected word line to non-selected word lines arranged on both adjacent sides of the selected word line.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: August 23, 2011
    Assignee: Spansion LLC
    Inventors: Fumiaki Toyama, Yukihiro Utsuno
  • Patent number: 8000158
    Abstract: A semiconductor memory device includes a plurality of memory cell matrixes each of which contains plural memory cell arrays whose number is lager than 2n and smaller than 2n+1, n being a natural number. The semiconductor memory device includes normal memory cell arrays including 2m numbers of memory cell arrays of the plurality of memory cell matrixes, m being a bit of addresses, wherein a data access operation is performed on normal memory cells in the normal memory cell arrays as normal word lines corresponding to the normal memory cells are activated in response to the addresses, and additional redundancy memory cell arrays in the plurality of memory cell matrixes, wherein repair-expected memory cells in the normal memory cell arrays are replaced with the additional redundancy memory cell arrays as redundancy word lines corresponding to the additional redundancy memory cells are activated in response to the addresses corresponding to the repair-expected memory cells.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: August 16, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Joong-Ho Lee
  • Patent number: 7974138
    Abstract: A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier with a sub-bit line to which the memory cell being read is connected, a selector line for connecting the first main bit line with a sub-bit line of at least one sector different from the sector to which the memory cell being read belongs, a selector line for connecting a second main bit line connected to the sense amplifier with a sub-bit line to which the reference cell is connected, and a selector line for connecting the second main bit line with a sub-bit line of at least one sector different from the sector to which the memory cell being read belongs.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: July 5, 2011
    Assignee: Panasonic Corporation
    Inventor: Kazuyuki Kouno
  • Patent number: 7852705
    Abstract: A method of configuring a plurality of memory elements having selectable dimensions, the method comprising the steps of selecting a width of a data word to be output by a circuit having the plurality of memory elements; selecting a width for memory locations of the plurality of memory elements, the width for the memory location being less than the width of a data word; configuring the plurality of memory elements to have the selected width; and concatenating the outputs for the plurality of memory elements to generate a concatenated output comprising a data word. A circuit for configuring a plurality of memory elements having selectable dimensions is also disclosed.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: December 14, 2010
    Assignee: Xilinx, Inc.
    Inventor: Tony Viet Nam Le
  • Patent number: 7729152
    Abstract: A pin configuration changing circuit of a base chip includes pin configuration changing register (PCCR) and a pin configuration changing logic unit (PCCLU). The PCCR stores and provides a pin connection assignment value indicating a first connection order of a plurality of pins included in a memory connected to the base chip, based on a type of the memory when the memory is changed. The PCCLU receives the pin connection assignment value and changes a second connection order of a plurality of inner pins of the base chip. Various memories can be connected to the base chip without extra wiring or a printed circuit board (PCB).
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: June 1, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jin-Kwon Park
  • Patent number: 7715271
    Abstract: A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory array. The dedicated read output paths bypass the width decoding logic and provide data from the memory array directly to a data bus, thereby providing improved memory performance when width decoding is not needed. The memory unit can be incorporated in programmable devices and a programmable device configuration can select either the read bypass paths or the width decoding logic. Hardware applications that require width decoding and improved memory access speed can utilize additional programmable device resources outside the memory unit to register the full width data from the memory unit and convert it to a different data width.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: May 11, 2010
    Assignee: Altera Corporation
    Inventors: Haiming Yu, Wei Yee Koay
  • Patent number: 7715254
    Abstract: The data output circuit for a semiconductor memory apparatus includes a first control signal generating unit configured to generate a first control signal according to a row address and a read command; and a data selecting unit configured to select data from a data line corresponding to a presently selected unit data output mode among data lines according to the first control signal or a second control signal, and output the data.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: May 11, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dae Han Kwon
  • Patent number: 7692952
    Abstract: Methods for obtaining codes to be implemented in coding nanoscale wires are described. The methods show how to code a reduced number of nanoscale wires through the use of rotation group codes. The methods further show how to generate different code permutations through random misalignment and how to promote uniform code probability selection.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: April 6, 2010
    Assignee: California Institute of Technology
    Inventor: André DeHon
  • Patent number: 7599218
    Abstract: An integrated circuit includes a non-volatile memory having memory cells, a memory cell selection circuit having selection blocks, a first device supplying a first voltage applicable to memory cells, a second device supplying a second voltage applicable to memory cells. Each memory cell selection block includes a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device. The first sub-block includes MOS transistors of a first type of conductivity, and the second sub-block includes MOS transistors of a second type of conductivity. Application may be particularly but not exclusively to phase change memories.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: October 6, 2009
    Assignee: STMicroelectronics SA
    Inventors: Christophe Rodat, Thierry Giovinazzi
  • Patent number: 7583524
    Abstract: A nonvolatile semiconductor memory device includes a plurality of 3-dimensional cell arrays to reduce the chip size. The nonvolatile semiconductor memory device includes a unit block cell array including a plurality of vertically multi-layered cell arrays each including a plurality of unit cells arranged in row and column directions, a column address decoder configured to decode a column address to activate a bit line of the selected cell array from the plurality of cell arrays, a sense amplifier unit configured to sense and amplify data of the bit line of the plurality of cell arrays and shared by the unit block cell array, and a vertical address decoding unit configured to decode a vertical address to select one of the plurality of cell arrays and to connect an output signal from the sense amplifier to the bit line of the selected cell array.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: September 1, 2009
    Assignee: Hynix Semicodnuctor Inc.
    Inventor: Hee Bok Kang
  • Publication number: 20090052271
    Abstract: An internal signal generator for use in a semiconductor memory device includes an internal read address generation unit and an internal write address generation unit. The internal read address generation unit generates a plurality of read delay addresses by delaying an external address for a predetermined latency shorter than an additive latency set by the semiconductor memory device and selects one of the read delay addresses to thereby output an internal read address. The internal write address generation unit generates a plurality of write delay addresses by delaying the internal read address for a preset latency shorter than a column address strobe (CAS) latency set by the semiconductor memory device and selects one of the write delay addresses to thereby output an internal write address.
    Type: Application
    Filed: October 21, 2008
    Publication date: February 26, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Jee-Yul KIM, Beom-Ju Shin
  • Patent number: 7489583
    Abstract: Various embodiments of the present invention include methods for determining nanowire addressing schemes and include microscale/nanoscale electronic devices that incorporate the nanowire addressing schemes for reliably addressing nanowire-junctions within nanowire crossbars. The addressing schemes allow for change in the resistance state, or other physical or electronic state, of a selected nanowire-crossbar junction without changing the resistance state, or other physical or electronic state, of the remaining nanowire-crossbar junctions, and without destruction of either the selected nanowire-crossbar junction or the remaining, non-selected nanowire-crossbar junctions. Additional embodiments of the present invention include nanoscale memory arrays and other nanoscale electronic devices that incorporate the nanowire-addressing-scheme embodiments of the present invention.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: February 10, 2009
    Inventors: Philip J. Kuekes, J. Warren Roblnett, Ron M. Roth, Gadlel Seroussl, Gregory S. Smider, R. Stanley Williams
  • Patent number: 7414916
    Abstract: A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory array. The dedicated read output paths bypass the width decoding logic and provide data from the memory array directly to a data bus, thereby providing improved memory performance when width decoding is not needed. The memory unit can be incorporated in programmable devices and a programmable device configuration can select either the read bypass paths or the width decoding logic. Hardware applications that require width decoding and improved memory access speed can utilize additional programmable device resources outside the memory unit to register the full width data from the memory unit and convert it to a different data width.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: August 19, 2008
    Assignee: Altera Corporation
    Inventors: Haiming Yu, Wei Yee Koay
  • Patent number: 7388802
    Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: June 17, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Sylvie Wuidart, Mathieu Lisart, Nicolas Demange
  • Publication number: 20080117710
    Abstract: A look-up table cascade circuit having N look-up tables connected in cascade for implementing a desired logic function, comprising: N memory cell arrays for storing data of the look-up table in memory cells; N input select circuits for selecting a word line and bit lines to specify memory cells based on an input variable to the look-up table; N output circuits for selectively coupling data in the memory cells selected by the input select circuit to an input/output path and for outputting the data as an output variable of the look-up table; and N?1 connection circuits arranged between each preceding output circuit and each subsequent input select circuit, for receiving an external input variable and the output variable output from each preceding output circuit, and for selectively distributing all or part of an external output variable and the input variable based on connection information.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 22, 2008
    Applicant: Elpida Memory, Inc.
    Inventor: Kazuhiko KAJIGAYA
  • Patent number: 7349267
    Abstract: In a memory cell array, source lines are provided so that each of the source lines is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. In an active period, the source bias control circuits perform potential control so that one or more of the source lines selected by row predecoders which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: March 25, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Naoki Kuroda
  • Patent number: 7336547
    Abstract: A memory device has a memory array for storing memory data, a conditioning data storage unit for storing conditioning data, and data lines for transferring data. During a memory operation, the memory device transfers both of the condition data and the memory data to the same data lines at different time intervals. The condition data is transferred at one time interval. The memory data is transferred at another time interval. Transferring the conditioning data to the data lines improves the accuracy of the transfer of the memory data at the data lines.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: February 26, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Ebrahim H Hargan
  • Patent number: 7266036
    Abstract: A semiconductor memory device is provided with a plurality of memory blocks including a plurality of word lines and a plurality of bit line pairs intersecting the individual word lines, a plurality of memory cells provided at each of intersections where the individual word lines intersect the bit line pairs, and a plurality of sense amplifiers respectively provided in correspondence with the bit line pairs. The semiconductor memory device further comprises common data bus line pairs each connected via switch transistors to the corresponding memory blocks, a read/write amplifier for performing a data read/write operation through the common data bus line pairs on the memory blocks, and an SRAM cell electrically connected via switch transistors to each common data bus line pair.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: September 4, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Emi Hayashi, Kiyoto Ohta, Yuji Yamasaki
  • Patent number: 7209376
    Abstract: A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: April 24, 2007
    Assignees: NEC Corporation, Elpida Memory, Inc.
    Inventors: Hideaki Saito, Yasuhiko Hagihara, Muneo Fukaishi, Masayuki Mizuno, Hiroaki Ikeda, Kayoko Shibata
  • Patent number: 7106639
    Abstract: A defect management enabled PIRM including a data storage medium providing a plurality of cross point data storage arrays. Each array provides a plurality of memory cells. The arrays are allocated into separate super arrays, the separate super arrays virtually aligned as sets. A controller is also provided, capable of establishing the selection of a virtually aligned set of arrays and a virtually aligned set of memory cells. The controller is operable during a write operation to receive a word of data bits and detect a defective array in the selected virtually aligned set of memory arrays. The controller is further capable of directing the allocation of at least one data bit from the defective memory array to a spare memory array.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: September 12, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Carl P. Taussig, Richard E. Elder
  • Patent number: 7003622
    Abstract: A semiconductor memory includes a redundant RAM disposed independently of at least one regular RAM, the redundant RAM having redundant memory elements by which defective memory elements of the regular RAM can be replaced, and a control block for selecting either at least the regular RAM or the redundant RAM according to an address applied thereto, and for reading data from a memory cell of the selected RAM specified by the address. A plurality of regular RAMs can be disposed and the redundant RAM includes redundant memory elements by which defective memory elements of an arbitrary one of the plurality of regular RAMs can be replaced. The control block selects either one of the plurality of regular RAMs or the redundant RAM according to an address applied thereto, and reads data from a memory cell of the selected RAM specified by the address.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: February 21, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hirofumi Shinohara, Yoshiki Tsujihashi, Takeshi Hashizume
  • Patent number: 6982920
    Abstract: A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: January 3, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Christophe Chevallier
  • Patent number: 6975553
    Abstract: Memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes, a log2(N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offsets) to bits of the byte-bank with an address conversion operator, and an adder in operative communication with the address offset bus and the log2(N) bit address bus, the adder operative to add addresses of the byte-bank with the offset generated by the address conversion operator and output a result to the log2(N) bit address. A random access memory array may include a plurality of the byte-banks.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: December 13, 2005
    Assignee: NeoMagic Israel Ltd.
    Inventor: Georgiy Shenderovich
  • Patent number: 6958745
    Abstract: A selection-addressing-type liquid crystal display selectively addresses a signal line of a pixel unit using groups of three selectors of a selector circuit in a time-division manner. A level converter level shifts selector pulses having a voltage swing corresponding to the external-circuit power supply to selector pulses having a voltage swing corresponding to the internal-circuit power supply. In a non-display region in partial display mode, the level converter is deactivated under the control of a control signal to reduce direct current consumption therein.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: October 25, 2005
    Assignee: Sony Corporation
    Inventors: Masaki Murase, Yoshiharu Nakajima
  • Patent number: 6940780
    Abstract: A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: September 6, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Christophe Chevallier
  • Patent number: 6909636
    Abstract: A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: June 21, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Christophe Chevallier
  • Patent number: 6862243
    Abstract: A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: March 1, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Christophe Chevallier
  • Patent number: RE45000
    Abstract: Memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes, a log2(N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offsets) to bits of the byte-bank with an address conversion operator, and an adder in operative communication with the address offset bus and the log2(N) bit address bus, the adder operative to add addresses of the byte-bank with the offset generated by the address conversion operator and output a result to the log2(N) bit address. A random access memory array may include a plurality of the byte-banks.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: July 8, 2014
    Assignee: Faust Communications Holdings, LLC
    Inventor: Georgiy Shenderovich