Abstract: A transmission circuit includes: an upper-layer clock bonding pad configured to transmit a clock signal; M upper-layer data bonding pads configured to transmit data signals; a lower-layer clock bonding pad electrically connected with the upper-layer clock bonding pad, and an area of the lower-layer clock bonding pad is smaller than that of the upper-layer clock bonding pad; and M lower-layer data bonding pads electrically connected with the M upper-layer data bonding pads in a one-to-one correspondence, and an area of a lower-layer data bonding pad is smaller than that of an upper-layer data bonding pad. The upper-layer clock bonding pad and the upper-layer data bonding pads are located on a first layer, the lower-layer clock bonding pad and the lower-layer data bonding pads are located on a second layer.

Abstract: A memory system includes: a semiconductor storage device including a memory cell array that includes memory cells and a temperature counter configured to increase a count value thereof at a rate that depends on a temperature of the memory cell array; and a memory controller configured to acquire the count value from the semiconductor storage device and reserve a refresh operation for a written memory cell of the memory cell array when a cumulative value of the count value, which is accumulated from when data was written to the memory cell to when the count value is acquired, exceeds a predetermined value.

Abstract: A method optimizing DQ calibration patterns for a memory device including data input/output (I/O) pins. The method includes; communicating a training command to the memory device, performing a training operation on each of the data I/O pins using a first training pattern having a first condition and a second training pattern having a second condition to generate a training operation result, wherein the first condition is characterized by adjacent data I/O pins among the data I/O pins providing data signals with different phases, and the second condition is characterized by adjacent data I/O pins providing data signals having a same phase, and aligning a data strobe signal with data signals provided from the data I/O pins in response the training operation result.

Abstract: A touch device with the FPR function includes a plurality of sensing regions, a plurality of first switch sets, a plurality of first shift register circuits, a plurality of second switch sets, and a plurality of second shift register circuits. The first switch sets are coupled to transmitting electrodes and to transmit a first signal. The first shift register circuits are to control the first switch sets according to a plurality of first reset signals and a plurality of first control signals respectively. The second switch sets are coupled to receiving electrodes and to receive a second signal. The second shift register circuits are to control the second switch sets according to a second reset signal and a plurality of second control signals. The first signal and the second signal are for a touch operation and a FPR operation.

Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.

Abstract: Embodiments of the present disclosure relate to a touch display apparatus and a gate driving circuit, and more particularly, provide a touch display apparatus including: two or more signal lines that transmit clock signals having the same frequency and different phases; and a multiplexer including input nodes through which clock signals transmitted through the two or more signal lines are input and an output node outputting any one of clock signals input to the input nodes. According to the embodiments of the present disclosure, touch sensing accuracy and display quality are possible to be improved.

Abstract: A display device includes a display panel including pixels connected to scan lines and data lines, and connection line connected to the scan lines, and a scan driver which drives scan lines. The scan driver includes a scan signal output circuit which outputs a first output signal as a scan signal to a first output line and outputs a second output signal to a second output line, a signal distribution circuit which outputs the first output signal to a first or third connection line and outputs the second output signal to a second or fourth connection line in response to first and second distribution control signals, and a scan-off circuit which outputs gate-off level to at least one of the scan lines in response to first and second scan-off control signals.

Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.

Abstract: A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.

Abstract: At least one processing device comprises a processor and a memory coupled to the processor. The at least one processing device is configured to implement adaptive flow control in conjunction with processing of input-output operations in a storage system. The adaptive flow control comprises a first feedback loop in which a window size defining an amount of concurrent processing of the input-output operations in the storage system is adjusted responsive to a measured latency for processing of one or more of the input-output operations. The adaptive flow control further comprises a second feedback loop in which at least one latency threshold used to control adjustment of the window size in the first feedback loop is adjusted. The at least one processing device illustratively comprises at least one processing core of a multi-core storage node of a distributed storage system.

Abstract: A do-not-disturb processing method, apparatus and a storage medium are provided. The method includes: receiving a first request message for a sleeping request; generating a query instruction according to first time information carried in the first request message; determining a restricted time period based on the first time information, in response to the query instruction; acquiring at least one first task within the restricted time period, from multiple interaction tasks to be executed; and closing the first task. In embodiments of the present application, efficiency of an interaction process is improved.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a channel surrounding a dielectric tube and a gate surrounding the channel. The dielectric tube comprises a high dielectric constant material that has or conducts few to no carriers, such as electrons or holes. The presence of the dielectric tube confines carriers to the channel, which is in close proximity to the gate. The proximity of the channel, and the carriers therein, to the gate affords greater control to the gate over the carriers, thus allowing a length of the channel to be decreased while experiencing little to no short channel effects, such as current leakage through the channel.

Abstract: The present disclosure includes apparatuses and methods for performing data restore operations in memory. An embodiment includes a memory, and a controller configured to perform a data restore operation on data stored in the memory using a first table and a second table stored in the controller, wherein the first table includes a current mapping of the data stored in the memory that is based on a previous assessment of previous error rates associated with the data stored in the memory, and the second table includes a new mapping of the data stored in the memory that is based on a current assessment of current error rates associated with the data stored in the memory.

Abstract: A finFET semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first fin formed in a first semiconducting layer, a second fin formed in a second semiconductor layer, and an insulating layer disposed between the first fin and the second fin. The first fin, the second fin, and the insulating layer form a stacked structure above a substrate. Sidewalls of the first fin are substantially more vertical than sidewalls of the second fin.

Abstract: A semiconductor device includes a shift control circuit and a synthesis pre-charge signal generation circuit. The shift control circuit generates a shift signal and a shift read signal based on a read command and controls a reset status of the shift read signal based on the shift signal and an auto-pre-charge command. The synthesis pre-charge signal generation circuit generates a synthesis pre-charge signal for an auto-pre-charge operation of a bank selected by an address based on the shift read signal and the address.

Abstract: A content addressable memory (CAM) structure is provided. The CAM comprises a plurality of CAM cells communicatively coupled to processing circuitry. A plurality of threshold switching (TS) memristors are included, each configured to connect to a one of the plurality of CAM cells, with the first end connected to the CAM cell and the second connected to a match line. A discharge transistor is included and configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.

Abstract: Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Abstract: A semiconductor device includes a repeater configured to output latch data as aligned data when the operation control signal is disabled and configured to interrupt the input of the latch data when the operation control signal is enabled for performing a data masking operation of internal data. The operation control signal is enabled according to logic levels of the internal data when a flag signal is enabled and a write data control signal is enabled.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

Abstract: A method and a system for diagnosing remaining lifetime of storages in a data center are disclosed. The method includes the steps of: a) sequentially and periodically collecting operating attributes of failed storages along with time-to-fail records of the failed storages in a data center; b) grouping the operating attributes collected at the same time or fallen in a continuous period of time so that each group has the same number of operating attributes; c) sequentially marking a time tag for the groups of operating attributes; d) generating a trend model of remaining lifetime of the storages from the operating attributes and time-to-fail records by ML and/or DL algorithm(s) with the groups of operating attributes and time-to-fail records fed according to the order of the time tags; and e) inputting a set of operating attributes of a currently operating storage into the trend model to calculate a remaining lifetime therefor.

Abstract: A fingerprint image recognition method is provided. The method includes: acquiring a target image from a captured texture image; acquiring a target shape feature corresponding to the target image, the target shape feature being configured to represent a shape feature of the target image; and when the target shape feature matches with a preset finger shape feature, determining to perform a fingerprint recognition on the texture image. Also provided in the present invention are a fingerprint image recognition apparatus and a terminal.

Abstract: Provided is a semiconductor device comprising a device region on a substrate, an interlayer dielectric layer on the device region, a first interface layer on a side of the interlayer dielectric layer, a low-k dielectric layer spaced apart from the interlayer dielectric layer across the first interface layer and having a dielectric constant less than that of the interlayer dielectric layer, and a conductive line in the low-k dielectric layer. The first interface layer comprises a first sub-interface layer in contact with the low-k dielectric layer, and a second sub-interface layer in contact with the interlayer dielectric layer. The second sub-interface layer has hydrogen permeability less than that of the first sub-interface layer.

Abstract: A computing device includes an interface configured to interface and communicate with a communication system, a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory that is configured to execute the operational instructions to perform various operations. The computing device determines to de-stage information stored in a cache memory to a nonvolatile memory device. The computing device determines whether the de-stage is based on a power interruption and when the de-stage is not based on a power interruption the computing device updates access counters associated with the information and the target location for the information in the nonvolatile memory, updates a data access tracking module and initiates a data relocation function to transfer the information to the nonvolatile memory device.

Abstract: The present disclosure relates to a touch driving circuit, a touch panel and a display device. A touch driving circuit, comprising: an input subcircuit, configured to receive an input signal which scans forward or backward; a shift register subcircuit, configured to shift register the input signal to generate an output control signal; an enable signal input subcircuit, configured to control an output of the output enable signal of the integrated circuit according to the output control signal; and an output subcircuit, configured to output a corresponding output signal according to the output enable signal. An embodiment of the present disclosure realizes the touch driving circuit with reduced usage of the integrated circuit.

Abstract: The present disclosure includes apparatuses and methods for performing data restore operations in memory. An embodiment includes a memory, and a controller configured to perform a data restore operation on data stored in the memory using a first table and a second table stored in the controller, wherein the first table includes a current mapping of the data stored in the memory that is based on a previous assessment of previous error rates associated with the data stored in the memory, and the second table includes a new mapping of the data stored in the memory that is based on a current assessment of current error rates associated with the data stored in the memory.

Abstract: A combination storage and processing device is disclosed. A large scale integrated circuit which incorporates both random access memory storage for individual data elements and circuits which process data elements according to a fixed set of instructions is disclosed. When directed by controlling software or hardware, a plurality of the individual data elements stored in the random access memory storage are pushed through the circuits which perform fixed operations upon the data elements and return them to random access memory storage. This allows operations to be performed on the plurality of data elements without sending them through a data bus to the central processing unit of a general purpose computing device, increasing efficiency and overall computing speed.

Abstract: The present disclosure relates to a solid-state imaging element and an electronic apparatus, in which the number of wires controlling readout can be reduced in a case where a pixel signal of each pixel is read out in a predetermined order for each unit pixel region. The unit pixel region is configured by a plurality of pixels arranged in an array. A readout circuit is provided for each unit pixel region and reads out, in a predetermined order, pixel signals of the plurality of pixels configuring the unit pixel regions. Pixel drive wires, which control readout of the pixels configuring the unit pixel regions adjacent in the vertical direction and having the same readout order, are shared. The present disclosure can be applied to, for example, a CMOS image sensor and the like.

Abstract: The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wiring, power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer, and at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer.

Abstract: A flash controller and a control method for the flash controller. The flash controller comprises an instruction bus interface, a data bus interface, a configuration register, an erase access filter module, a read/write access filter module and a flash control module. The read/write access filter module is configured to receive control information and determine whether the read/write access is sent to the flash control module or not. The erase access filter module is configured to receive control information and determine whether the erase access is sent to the flash control module or not. The flash control module is configured to complete an access to a flash memory. The present disclosure is used to protect programs from being stolen by a client, and also protect against a situation where companies collaboratively developing a program are able to steal programs from one another.

Abstract: Systems and methods are disclosed to delete a command queue, in accordance with certain embodiments of the present disclosure. An apparatus may comprise a circuit configured to receive a queue deletion indicator from a host device, including a queue identifier for a selected command queue to be deleted. The circuit may abort each command associated with the selected command queue and pending at the apparatus based on the queue identifier. Commands associated with the selected queue may be identified in a command table and flagged with an abort bit, which may signal an I/O processing pipeline to abort the command when encountered. The circuit may verify that no commands associated with the selected command queue remain pending at the apparatus, and send a completion indicator to notify the host device that the selected command queue is deleted.

Abstract: Magnetic tunnel junction (MTJ) structures, spin transfer torque magnetic random access memory (STT MRAM) structures, and methods for fabricating integrated circuits including such structures are provided. In an embodiment, an MTJ structure includes a cobalt iron carbon (CoFeC) fixed reference layer. Further, the MTJ structure includes a cobalt iron carbon (CoFeC) free storage layer. Also, the MTJ structure includes a tunnel barrier layer between the fixed reference layer and the free storage layer.

Abstract: Memory packages, memory modules, and circuit boards are described. In an embodiment, single channel memory packages are mounted on opposite sides of a circuit board designed with a first side also designed to accept dual channel memory packages. Alternatively, dual channel memory packages may be mounted on a first side of a circuit board that is also designed to accept single channel packages on opposite sides.

Abstract: A finFET semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first fin formed in a first semiconducting layer, a second fin formed in a second semiconductor layer, and an insulating layer disposed between the first fin and the second fin. The first fin, the second fin, and the insulating layer form a stacked structure above a substrate. Sidewalls of the first fin are substantially more vertical than sidewalls of the second fin.

Abstract: A silicon nitride film forming method for forming a silicon nitride film on a substrate to be processed, includes forming a silicon nitride film doped with a predetermined amount of titanium by repeating, a predetermined number of times, forming a silicon nitride film by repeating, a first number of times, a process of causing a silicon source gas to be adsorbed onto the substrate and a process of nitriding the adsorbed silicon source gas with plasma of a nitriding gas, and forming a titanium nitride film by repeating, a second number of times, a process of causing a titanium source gas containing chlorine to be adsorbed onto the substrate and a process of nitriding the adsorbed titanium source gas with the plasma of the nitriding gas.

Abstract: A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.

Abstract: A liquid mixture for etching a substrate includes a first liquid comprising one of: (i) percarboxylic acid comprising 3 to 70 mass. % of the liquid mixture; or (ii) carboxylic acid comprising 3 to 70 mass. % of the liquid mixture and at least one liquid selected from a group consisting of hydrogen peroxide comprising 3 to 30 mass. % of the liquid mixture and ozone comprising 0.5 to 5 mass. % of the liquid mixture; a water drawing agent comprising 2 to 40 mass. % of the liquid mixture; hydrofluoric acid comprising 0.05 to 3 mass. % of the liquid mixture; and water comprising 0 to 60 mass. % of the liquid mixture. The liquid mixture may be used to etch silicon germanium relative to silicon, silicon dioxide and silicon nitride.

Abstract: A finFET semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first fin formed in a first semiconducting layer, a second fin formed in a second semiconducting layer, and an insulating layer disposed between the first fin and the second fin. The first fin, the second fin, and the insulating layer form a stacked structure above a substrate.

Abstract: The present embodiments relate to regulating the supply voltage of an integrated circuit. The integrated circuit may implement a circuit design. The circuit design implementation may meet timing constraints with timing margins when operated with the integrated circuit at a nominal supply voltage level. The integrated circuit may further include a voltage identification controller. The voltage identification controller may determine a reduced voltage level based at least on the timing margins such that operating the circuit design implementation with the integrated circuit meets timing constraints. The voltage identification controller may direct a voltage regulator, which may be included in the integrated circuit or located outside the integrated circuit, to reduce the supply voltage level from the nominal supply voltage level to the reduced voltage level, thereby reducing the power consumption of the integrated circuit.

Abstract: Some embodiments of the present disclosure relate to an integrated chip having a vertical transistor device. The integrated chip may have a semiconductor body with a trench extending along first sides of a source region, a channel region over the source region, and a drain region over the channel region. A gate electrode is arranged along a first sidewall of the trench, and a metal contact is arranged on the drain region. An isolation dielectric material is disposed within the trench. The isolation dielectric material is vertically over a top surface of the gate electrode and is laterally adjacent to the gate electrode.

Abstract: An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.

Abstract: A direct-current fan control chip comprises a magnetoresistive sensor, a controller, a driver and a substrate. The magnetoresistive sensor, the controller and the driver are integrated on the substrate. The sensing direction of the magnetoresistive sensor is perpendicular to or parallel to the surface of the direct-current fan control chip. The magnetoresistive sensor provides the controller with a rotor position signal, a rotor speed signal, and rotor a rotation direction signal for the controller. The controller outputs a control signal to the driver according to the received signals. After receiving the control signals, the driver outputs a drive signal. This control chip has the advantages of good temperature stability, good frequency response and so on.

Abstract: A single poly NVM cell includes a first N-type well region and a second N-type well region spaced apart from each other by a P-type semiconductor layer, a first active region and a second active region disposed in the first N-type well region and the second N-type well region, respectively, a P-channel floating gate transistor including a floating gate disposed in the first active region, a P-type drain region disposed in the first active region, and a P-type junction region disposed in the first active region, wherein the floating gate extends to over the second active region, a P-channel read selection transistor including a read selection gate electrode disposed in the first active region, the P-type junction region disposed in the first active region, and a P-type source region disposed in the first active region, and an interconnection line connecting the first N-type well region to the P-type source region of the P-channel read selection transistor.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a channel surrounding a dielectric tube and a gate surrounding the channel. The dielectric tube comprises a high dielectric constant material that has or conducts few to no carriers, such as electrons or holes. The presence of the dielectric tube confines carriers to the channel, which is in close proximity to the gate. The proximity of the channel, and the carriers therein, to the gate affords greater control to the gate over the carriers, thus allowing a length of the channel to be decreased while experiencing little to no short channel effects, such as current leakage through the channel.

Abstract: A scan driver includes scan-driving blocks, each including a first transistor having a gate coupled to a first node to supply a first power to an output terminal, a second transistor having a gate coupled to a second node to couple a second clock to the output terminal, a third transistor having a gate coupled to a first input to supply the first power to the first node, a fourth transistor having a gate coupled to a second input to supply a second power to the first node, and a fifth transistor having a gate coupled to a first clock to couple the first input to the second node. A first scan-driving block further includes a sixth transistor coupled between the second input and the fourth transistor gate, and a NOT gate configured to invert the first input signal and to supply the inverted signal to the sixth transistor gate.

Abstract: Embodiments of systems and methods that ensure integrity of data during unexpected power interruption of loss are disclosed. In some embodiments, critical data is saved quickly and efficiently using backup power. Data integrity is ensured even when the reliability of backup power sources is an issue. In some embodiments, by skipping the updating and saving of system data while operating on backup power, significant reduction of time for saving critical data can be achieved. System data can be restored next time the data storage system is restarted. Improvements of data storage system reliability are thereby attained.

Abstract: A memory module includes at least two rows of memory device packages on a substrate and coupled to a control signal line. A first memory device package in a first row is connected to the control signal line at a first point closest to the proximal end of the control signal line and a second memory device in a second row is connected to the control signal line at a second point next closest to the first point. A signal trace length between the first memory device and the second memory device may be greater than a signal trace length between the first memory device package and a third memory device package immediately adjacent the first memory device package in the first row or a signal trace length between the second memory device package and a fourth memory device package immediately adjacent the second memory device package in the second row.

Abstract: Disclosed are a method and a system for transmitting a file folder from the sending end to the receiving end. The system uses a file folder transmission unit at the sending end side to generate a directory structure file of the file folder. The directory structure file may have properties such as the size of the file folder, paths and path lengths of the files in the file folder. The sending end then sends the directory structure file to the receiving end through the file folder transmission unit to allow the system to determine which files in the file folder need to be transmitted. The needed files in the file folder are then transmitted to the receiving end according to the determination. The sending end and the receiving end may communicate using an instant messaging tool. The disclosed method and system allow a faster and more convenient file folder network transmission.

Abstract: A memory system may include a memory module accessed by a first address, a memory controller configured to provide a read or write command for the memory module according to a host request, and a memory buffer accessed by a second address. The memory buffer may include a register file having two or more entry spaces corresponding to interleaving units of the memory module, and the two or more entry spaces may be positioned in different address areas which are accessible at the same time.