Abstract: A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.

Abstract: A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208t) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208t) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: An acquisition process for signal sampling includes high-speed analog signal sampling, storing the samples of the analog signal in a matrix of memory cells, and re-reading the samples from the cells at low speed. Two identical memory devices are provided in each memory cell. One sample of an analog signal is stored in one memory device, and one sample of that signal that is out of phase is stored in the other memory device.

Abstract: A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

Abstract: A multi-counter based system having a counter array. Each counter of the array having a memory cell. The system also includes an address decoder coupled to the counter array to select at least one of the memory cells within the counter array and read/write circuitry coupled to the counter array to pass data with the counter array.

Abstract: A column decoder circuit for page reading of a semiconductor memory includes a first level decoder stage, a second level decoder stage, and a plurality of bit selection stages, each comprising a plurality of selection branches; wherein each selection branch is connected to a respective input of a multiplexer and has a plurality of first level selector stages and a second level selector stage. Each second level selector stage comprises a first addressing selector for addressing a first group of bit lines. Each bit selection stage further comprises a second addressing selector for addressing a second group of bit lines, current and next page selectors for selecting one of the first and second groups of bit lines.

Abstract: A redundancy architecture for a memory includes an array of memory cells divided into at least a pair of semi-arrays that are singularly addressable. Each semi-array is organized into rows and columns. The redundancy architecture includes a number of packets each including redundancy columns. The packets are divided into two subsets of packets. Each packet is addressable independently from the other by respective address circuits. Each packet also provides redundancy columns exclusively for a respective semi-array.

Abstract: The external intelligent component (3) connected with a microprocessor system (2) is described for essentially automatic control of a control element (1) without burdening the microprocessor system operation. The control parameters for the control element (1) are written into a data memory (6) of the external component (3) from the microprocessor system (2) and are read out internally from the data memory (6) during normal operation of the external component (3). Control of the external component (3) is possible by the microprocessor system (2) without blocking the system bus (5,7) of the microprocessor system (2) using a control line from the microprocessor to a reset input (RESET) of a controller (13) of the external component (3).

Abstract: The number of apparently independently operating memory sets can be changed by providing the same number of address setting circuits as that of memory cell arrays. Since the number of mounted address setting circuits increases compared with a case where the number of memory sets is fixed, the problem arises that the layout area in a semiconductor memory device increases. However, by providing a switching circuit for switching the correspondence relationship between memory cell arrays and address setting circuits in response to a signal selecting the number of memory sets, a semiconductor memory device capable of changing the number of memory sets which seemingly independently operate without providing the same number of address setting circuits as that of memory cell arrays.

Abstract: A memory device includes a memory array and a configurable decoder circuit operatively associated with the memory array and configurable to one of a first state or a second state. In the first state, the configurable decoder circuit is operative, responsive to receipt of an address associated with a portion, e.g., a block, of the memory array, to select the portion while producing a first status signal. In the second state, the configurable decoder circuit is operative, responsive to receipt of an address associated with the portion of the memory array, to prevent selection of the portion while producing a second status signal. The first status signal may indicate, for example, that the portion is valid, while the second status signal may indicate that the portion is invalid.

Abstract: An address generating device for addressing data stored in an interleaver memory in B rows and F columns, where F is not 2k for a positive integer k. A row counter being responsive to B clock pulses, outputs carry signal when the row counter count to B−1, outputs the 0 value when the first row address is outputting, outputs the added value of offset value F and previous output value of the row counter, and generates a counter reset signal when output the carry signal. The B is the number of rows. A column counter increases a count value in increments of one in response to the carry signal. A mapper permutates the output of the counter according to a predetermined permutation rule. An adder generates a read address by using the output of the row counter as the most significant bits(MSB) of the read address and by using the output of the mapper as the least significant bits(LSB) of the read address.

Abstract: When a cell of a memory cell array (C0 and C1) located at a position further from the word select line driver is selected, data that is read from the memory cell array (C0, C1) is sent via only sense amplifier circuits (S0, S1) to the output buffer circuit (OB), while data from the other memory cell array (C2˜C7) are sent via the sense amplifier circuits (S2˜S7), the error detection circuit (ECC1), the syndrome decoder circuit (ECC2) and the error correction circuits (CR2˜CR7) to the output buffer circuit (OB). Data are output while bypassing the ECC circuits for the memory cells (C0, C1) of which word select lines have larger resistance and capacitance that cause a significant delay in the reading by the sense amplifier compared to reading of the memory cells located near the start point of the word select line (critical read cell).

Abstract: A semiconductor memory device includes a memory cell array divided into a plurality of sub-arrays. The number of memory cells per bit line in at least one of the sub-arrays differs from the number of memory cells per bit line in other sub-arrays. When the sense amplifiers can accommodate a bit line loading of (2M+2M/N) memory cells per bit line, the size and bit line loading of one of more of the sub-arrays can be increased. This can provide sub-arrays of different sizes and can reduce the number of the sub-arrays and the number of the sense amplifier regions. Accordingly, the chip efficiency is improved. Maximum current for sensing during simultaneous accesses of multiple arrays can access two sub-arrays with different bit line loadings and avoid simultaneously accessing two sub-arrays having high bit-line loadings.

Abstract: A word line driving circuit drives four word lines in response to a signal supplied from a main row decoder through a main word line and in response to a word line driving voltage supplied from a sub-row decoder. When the word line driving circuit is not selected by the main word line, a first reset circuit allows each word line to be short-circuited. When the word line driving circuit is selected by the main word line, second to fifth reset circuits allow the non-selected word line to bear a ground potential by using a signal of the selected word line.

Abstract: A video chip includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register. There is a circuit for the column lines and for the row lines. A bit pattern is driven onto the column or the row lines and received in the corresponding test circuitry. The pattern is read out and compared against the input pattern to detect faulty lines.

Abstract: In a semiconductor memory, four bit line diffused interconnections 1 connected to two bit line terminals D0 and D1 through bank selection transistors BT1 and BT2 are connected to drains of memory cells of four column pairs, respectively, and four bit line diffused interconnections 2 connected to one virtual ground line terminal VG1 through bank selection transistors BT3 to BT6 are connected to sources of memory cells of the four column pairs. The bank selection transistors BT1 to BT6 are so located that each of the bit line diffused interconnections 1 is connected to a corresponding one of the bit line terminals D0 and D1 through only one bank selection transistor and each of bit line diffused interconnections 2 is connected to the virtual ground line terminal VG1 through only one bank selection transistor. Thus, data can be surely read from a selected memory cell at a high speed.

Abstract: Disclosed is a method for controlling a memory address of a digital signal processor in which a memory address is independently managed for each for during parallel processing of a plurality of jobs and no program of the same content as others is stored redundantly. Two bits of a high order A19 and A18 are masked among memory addresses of 20 bits from A0 to A19 which can be accessed for internal and external memories by a digital signal processor. In an address setting and an address computation performed on a program for executing each of jobs of the digital signal processor, only an address space of 18 bits from A0 to A17 can be accessed by an address pointer. The masked two bits of A19 and A18 are accessed by an address area register.

Abstract: A circuit for implementing a substitutional compressor. Comparators compare a current input pixel against a large number of previous pixels, the "history", stored in a series of shift registers. Each register and associated comparator constitutes a cell. If one or more matches are found the history data is shifted one pixel, the non-matching cells are disabled, and the next input pixel is compared against the contents of the same cells that had the previous matches. The matching is terminated when the longest series of matching pixels is found. The output code is then the length of the matching series of pixels, and the displacement of the first input pixel from the first matching pixel. An encoder generates an initialize signal that resets all of the disabled cells on the same clock cycle on which the output code word is generated. To make the circuit more compact, the cells can be arranged into a square format with one output line for each row and column from the cells to the encoder.

Abstract: A memory interface unit comprising a bus interface unit, a buffer which can store multiple data burst subsets in transit to or from a digital memory, and a switch which includes an externally accessible master data path for the transfer data to or from the bus interface unit and which includes an externally accessible slave data path for the transfer of data to or from the buffer and which includes a direct data path for the transfer data between the bus interface unit and the buffer.

Abstract: A memory interface unit comprising a bus interface unit, a buffer which can store multiple data burst subsets in transit to or from a digital memory, and a switch which includes an externally accessible a master data path for the transfer data to or from the bus interface unit and which includes an externally accessible slave data path for the transfer of data to or from the buffer and which includes a direct data path for the transfer data between the bus interface unit and the buffer.

Abstract: A semiconductor memory device, including a memory cell array having a plurality of memory cells arranged in rows and columns, the memory cells storing data and being selected according to address signals. The device includes a control unit which receives a clock signal and a first control, or trigger, signal for outputting a plurality of the data in synchronism with the clock signal after the first control signal is asserted. The output of the data beginning after a number of clock cycles (N) of the clock signal (N being a positive integer .gtoreq.2) after the first control signal is asserted, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output.

Abstract: An efficient technique or providing ROM memory on a microprocessor local bus is described whereby a ROM and all necessary address decoding and control circuitry is incorporated in a single integrated circuit. By doing this, only one chip is required to add ROM to a microprocessor local bus, saving considerable space and power over discrete implementations. The ROM is implemented in a wide memory format, matching the bus width of the microprocessor to which it is connected. This permits full-speed access to the local bus ROM, and eliminates any need for such techniques as ROM "shadowing".

Abstract: A FIFO memory system exhibits data processing capabilities by the inclusion therein of a digital signal processor and an associated dynamic random access memory. The digital signal processor provides significant data processing on the fly while the dynamic random access memory array provides additional buffering capability. Input and output FIFOs are connected to the data and address bussed of the digital signal processor. The control of the digital signal processor is via a host processor connected to the digital signal processor by a serial communication link.

Abstract: In a semiconductor memory apparatus having a cell array structure wherein occurrence of leak current is reduced and a margin at the time of sensing is increased, a plurality of memory transistors arranged in a matrix and having any one of four thresholds constitute banks in a column direction. The banks constitute memory cell arrays. A main bit line of Al is connected to three sub-bit lines via first selection transistors. A main ground line of Al is connected to two sub-ground lines via second selection transistors. Bank selection lines and word lines are formed to cross the main bit line and main ground line. Gates of the selection transistors are connected to the selection lines, and one selection line is connected to one selection transistor. Each of the sub-bit lines and sub-ground lines has a column of memory transistors which constitute a bank. A separation region (not shown) of a silicon oxide film, etc. is formed between the memory cell arrays to prevent leak current.

Abstract: A memory system, wherein the respective byte memories 1 to 4 is configured so that data of word unit which are the targets of the parity calculation done by the parity calculation circuits 5 to 8 occupy respectively the same bit positions as those of the 4-word data of word unit, is provided with multiplexers 41 to 44 for connecting selectively to the data bus 29 the bit positions of the data of word unit selected by the word select control circuit 23 in such byte memories 1 to 4. The memory system is capable of improving the flexibility of the memory configuration by being eased of the limitation of the arrangement of bits which are the targets of parity calculation, and reducing the occupied areas of the write/read circuit on a chip as well as the electric power consumption.

Abstract: An efficient technique for providing ROM memory on a microprocessor local bus is described whereby a ROM and all necessary address decoding and control circuitry is incorporated in a single integrated circuit. By doing this, only one chip is required to add ROM to a microprocessor local bus, saving considerable space and power over discrete implementations. The ROM is implemented in a wide memory format, matching the bus width of the microprocessor to which it is connected. This permits full-speed access to the local bus ROM, and eliminates any need for such techniques as ROM "shadowing".

Abstract: A data compressor generates codewords representative of the location and length of a string match between an input data stream and a CAM array vocabulary table. A data decompressor looks up the codewords for a string match in its vocabulary table. The CAM array is arranged in a serpentine configuration to reduce track layout. A column priority encoder reverses the priority of alternate rows to maintain the logical flow through the CAM array. The CAM array uses a flipflop with a common control circuit to transfer and refresh data through the flipflop.

Abstract: A multi-port shared memory system is provided which includes multiple ports for transfering data; a plurality of memory access buffers; and an interconnection matrix circuit for distributing subsets of data between the ports and the buffers.

Abstract: A semiconductor integrated circuit device constituted by a plurality of sets each of which having a pair of memory mats and each memory mat having a plurality of memory cells arranged in a matrix and a sense amplifier, I/O lines for transmitting signals provided by the sense amplifiers, selecting circuitry for selecting either a condition for sending out the signals provided by the sense amplifiers on the I/O lines or a condition for not sending out the same on the I/O lines, and Y-selection lines for transmitting the selection signals. A decoder connected with selection is disposed substantially at the middle of the Y-selection lines. X- and Y-address buffers are disposed close to each other nearer to the center of the chip than X- and Y-redundant circuits. A reference voltage generating circuit is disposed nearer to the edge of the chip than an output buffer circuit. A relief selecting circuit of each memory mat is formed adjacent to a redundant line selecting circuits included in the same memory mat.

Abstract: A non-volatile memory element comprising a control gate formed by a diffusion layer, a floating gate comprising a conductive layer, the floating gate being partly overlapping with the control gate through a thin insulating layer, and a barrier layer formed to cover a part or the entire part of the floating gate is used as a defect remedy circuit for the memory circuit having read-only memory elements arranged in the form of a matrix for storing defective addresses corresponding to the word lines and bit lines and storing data corresponding thereto respectively.

Abstract: A semiconductor memory device divided into a number of main blocks each main block having a number of subblocks selects a single main block and enables the subblocks of the selected main block, so as to reduce the power consumptions. The semiconductor memory device includes a block selector for selecting one of the main blocks in response to row address signals, a number of first boost circuits for selecting the subblocks of the selected main block in response to the row address signals, and a number of second boost circuits adapted to be disabled in response to the row address signals.

Abstract: A multiport memory device includes first and second memory cell arrays divided by a shared sense amplifier circuit, a first serial data register capable of transferring data with a row in the first memory array through a first data bus, a second serial data register capable of transferring data with a row in the second memory array through a second data bus. The multiport memory device activates both the first and second data bus for transferring data of a row in the first or second memory array both to the first and second serial data registers in the same data transfer cycle in response to a dual read transfer instructions.

Abstract: A dual-port memory device provides for a memory array which is divided approximately in half. Between the two halves of the array, a bit line crossover scheme is provided which minimizes stray capacitance and cross-coupling capacitance between bit lines for the two different ports. A bit line layout plan which minimizes such capacitances causes the data for one of the ports to be inverted in one-half of the array. When data from this half of the array is read or written by such port, the data being read or written must be inverted.

Abstract: An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to the first stage branch portion. The second stage output portion, to which the selecting signal is applied, outputs a selecting signal on one of two output portions in response to the second bit information of the address signal, in accordance with the selecting signal. Thereafter, each branch portion of the third to last stages outputs a selecting signal on one of two output portions in response to respective contents of the third bit to last bit of the address signal in accordance with the selecting signal applied from the preceding stage. By this selecting signal, a memory cell as a functional block portion is selected and is activated.

Abstract: The disclosure concerns integrated memories and their redundancy circuits. The described redundancy concerns the memories organized in k groups of p columns (for example k=8 and p=64) to give words of k bits, when one column address out of p is chosen. The addresses of defective columns are memorized. In certain cases, the pad position (p0, p1, p2, p3) corresponding precisely to the defective column is also memorized. It is proposed to reduce the space occupied by the pad position determining logic circuits for which a redundancy has to be activated. This reduction is obtained by organizing a matrix EPROM to contain, for each defective column address, a memorized corresponding pad position. If there are N possibilities of repairs and r possible pad positions, the memory includes N lines and r columns. This is more than necessary, but that makes it possible to gain more space in avoiding the use of bulky logic decoders.

Abstract: The present invention provides a memory addressing system that can accommodate multiple size DRAMS. DRAMS of various sizes can be mixed in a variety of ways. The present invention provides a hardware register associated with each pair of banks of DRAMS. This hardware register is programmable to indicate the type of DRAMS that have been inserted in the particular memory banks and to indicate the starting address of the particular set of memory banks. Using this technique, it is necessary to insert the largest memory chips in the first memory bank. Memory chips of either size can be inserted in either set of memory banks and the information in the programmable register is used to control circuitry which appropriately modifies the accessing signals which are sent to the memory system.

Abstract: An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to the first stage branch portion. The second stage output portion, to which the selecting signal is applied, outputs a selecting signal on one of two output portions in response to the second bit information of the address signal, in accordance with the selecting signal. Thereafter, each branch portion of the third to last stages outputs a selecting signal on one of two output portions in response to respective contents of the third bit to last bit of the address signal in accordance with the selecting signal applied from the preceding stage. By this selecting signal, a memory cell as a functional block portion is selected and is activated.

Abstract: The present invention provides a memory addressing system that can accommodate multiple size DRAMS. DRAMS of various sizes can be mixed in a variety of ways. The present invention provides a hardware register associated with each pair of banks of DRAMS. This hardware register is programmable to indicate the type of DRAMS that have been inserted in the particular memory banks and to indicate the starting address of the particular set of memory banks. Using this technique, it is not necessary to insert the largest memory chips in the first memory bank. Memory chips of either size can be inserted in either set of memory banks and the information in the programmable register is used to control circuitry which appropriately modifies the accessing signals which are sent to the memory system.

Abstract: A stack with a unary encoded stack pointer which uses the position of a single bit to point to the top of the stack. A number of multi-bit latches are used to store the data elements in the stack. A serial, bidirectional shift register is loaded with all digital zeros except for a position having a digital one (the pointer) which is coupled to the register containing the top of the stack. As new data elements are pushed onto or popped off of the top of the stack, the pointer is shifted right or left accordingly.

Abstract: A single plane dynamic decoder wherein a typical decoder row comprises a P-channel transistor connected between a positive supply and a first node, a second N-channel transistor connected between ground potential and a second node, and a plurality of series-connected devices connected between the first node and the second node. The gates of the intermediate N-channel devices are connected to a corresponding input signal such that the intermediate devices are enabled or disabled depending on the state of the associated input. The gate of the P-channel device is connected to a clock signal such that it is enabled by a first clock phase and disabled by a second clock phase. The N-channel device is connected to the clock signal such that it is enabled by the second clock phase and disabled by the first clock phase. Thus, the first node is precharged when the P-channel device is enabled. This precharge activity occurs serially and hierarchically down the row depending on the state of the respective input signals.

Abstract: An integrated circuit memory includes processing capability on the same chip, on one or both of an address path and data path between a set of access registers and a memory array so that an address can be generated, checked or manipulated and/or data can be manipulated or compared with a reference pattern of data.

Abstract: In a one-directional internal circuit such as a first-in first-out (FIFO), switchover switches are provided between the internal input/output ports and external ports thereof, and the switches are controlled by a mode signal, thereby enabling a bidirectional data transmission within one chip.

Abstract: A translator is organized to include at least a pair of content addressable memories (CAMs), each for storing a different portion of the total number of bits of each of the words to be translated. The outputs from each CAM are logically combined within a multiple input random access memory (RAM). Both CAMs are interrogated simultaneously and deliver the results of comparing the word portions of an input word and the CAM contents to the RAM in substantially less time then required for a single CAM memory. The results are logically combined with in the RAM which, in response to a match condition, delivers the results of the translation as an output.

Abstract: A decoder circuit for decoding different combinations of supplied original input address bits, comprising at least one predecode circuit responsive to the original input address bits for producing predecoded signal bits from the input address bits, and a plurality of decoder units including at least one decoder unit responsive to at least two different combinations of the original input address bits, wherein the decoder units comprises a decoder unit responsive to selected ones of the predecoded signal bits alone and a decoder unit responsive to at least one of the predecoded signal bits and at least one of the original input address bits.

Abstract: A programmable logic device of a single semiconductor chip includes a plurality of programmable AND-OR logic blocks, each block including an AND gate array and an OR gate array and at least a pair of input and output lines; a plurality of input/output buffer blocks, each block including at least one input and output lines; and a plurality of interconnection lines across which the input and output lines extend. A programmable switch is provided at each of the intersections between the input and output lines and the interconnection lines, so that each of the input and output lines are selectively connected to a desired one of the interconnection lines. Preferably, each of the interconnection lines further includes at least one programmable switch so that each of the interconnection lines may be divided into a desired number of segments which are electrically isolated from one another.

Abstract: An oscilloscope to sequentially store, process and display an electrical input signal according to various signal events and characteristics. The oscilloscope is physically and functionally modular having both selectable hardware configurations from among various "plug-in" modules and selectable processing and display features chosen from among a predetermined selection by software control contained, in part, within the plug-in modules. The particular control settings, as well as a representation of the signal itself, is recorded on a removable storage device, such as a magnetic disc. High frequency signals are sampled, digitized and stored in a high speed intercascaded signal memory, independent from the program and data memory associated with the oscilloscope signal processing.

Abstract: A memory apparatus is managed by two-dimensional addresses consisting of X and Y addresses and is divided into a plurality of memory banks. One of the memory banks is selected by lower significant bits including the least significant bit in each of the X and Y addresses. A different memory bank is selected by the updating of the X address or by the updating of the Y address.

Abstract: Search apparatus is described for locating an item which satisfies a predetermined criterion e.g. an instruction ready for execution or a free block of data. The apparatus uses a tree structure where each terminal node represents one of the items and is set if that item satisfies the criterion. A non-terminal node is set if any of its subordinate nodes is set. In order to locate an item, a path is traced through the tree, starting at the root node and passing through a series of set nodes until a set terminal node is reached.

Abstract: A decoder circuit for decoding different combinations of supplied original input address bits, comprising at least one predecode circuit responsive to the original input address bits for producing predecoded signal bits from the input address bits, and a plurality of decoder units including at least one decoder unit responsive to at least two different combinations of the original input address bits, wherein the decoder units comprises a decoder unit responsive to selected ones of the predecoded signal bits alone and a decoder unit responsive to at least one of the predecoded signal bits and at least one of the original input address bits.