Magnetic Patents (Class 365/232)
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Patent number: 9583057Abstract: Provided are a pixel circuit and a display device which support multi-gradation display and can prevent display quality from deteriorating with low power consumption. A pixel circuit (3) includes a first switch circuit (22) provided between a pixel node Np of a display element unit (21) and a data signal line SL, and a memory circuit (23) which restores the pixel node to an initial voltage state, based on a hold voltage stored in a storage node Nm.Type: GrantFiled: December 14, 2012Date of Patent: February 28, 2017Assignee: SHARP KABUSHIKI KAISHAInventor: Yoshimitsu Yamauchi
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Patent number: 9583193Abstract: Integrated non-volatile memory device includes an integrated memory cell of the EEPROM type with a floating-gate transistor and a selection transistor connected in series between a source line and a bit line, and a programming circuit for the memory cell. The selection transistor is connected between the floating-gate transistor and the source line. The programming circuit is configured for programming the at least one memory cell with a programming voltage split between a positive voltage and a negative voltage.Type: GrantFiled: September 24, 2015Date of Patent: February 28, 2017Assignee: STMicroelectronics (Rousset) SASInventor: François Tailliet
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Patent number: 9558819Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.Type: GrantFiled: August 13, 2015Date of Patent: January 31, 2017Assignee: ARM Ltd.Inventors: Robert Campbell Aitken, Lucian Shifren
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Patent number: 9543357Abstract: An MRAM device comprises an insulating interlayer comprising a flat first upper surface on a first region and a second region of a substrate. A pattern structure comprising pillar-shaped magnetic tunnel junction (MTJ) structures and a filling layer pattern between the MTJ structures is formed on the insulating interlayer of the first region. The pattern structure comprises a flat second upper surface that is higher than the first upper surface. Bit lines are formed on the pattern structure that contact top surfaces of the MTJ structures. An etch-stop layer is formed on the pattern structure between the bit lines of the first region and the first upper surface of the first insulating interlayer of the second region. A first portion of an upper surface of the etch-stop layer on the first region is higher than a second portion of the upper surface of the etch-stop layer on the second region.Type: GrantFiled: July 20, 2015Date of Patent: January 10, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Pil Ko, Myoung-Su Son, Kil-Ho Lee
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Patent number: 9523996Abstract: A method for controlling an electronic circuit, characterised in that it comprises a step of feedback control of a current voltage-frequency operating point relative to a reference curve of a voltage-frequency domain of operation associated with the circuit, to bring the circuit from a first operating point to a second operating point, said reference curve linking said first and second operating points in an optimal trajectory relative to a boundary of said domain.Type: GrantFiled: December 20, 2012Date of Patent: December 20, 2016Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Carolina Albea Sanchez, Suzanne Lesecq, Diego Puschini Pascual
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Patent number: 9507756Abstract: A network device includes a memory and a counter update logic module. The memory is configured to store a plurality of bits. The counter update logic module is configured to estimate a count of quanta within a plurality of data units in a data flow based on statistical sampling of the plurality of data units, and to store the estimated count of quanta in the memory as m mantissa bits and e exponent bits. Them mantissa bits represent a mantissa value M and the e exponent bits represent an exponent value E.Type: GrantFiled: January 17, 2013Date of Patent: November 29, 2016Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Carmi Arad, Gil Levy
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Patent number: 9443583Abstract: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.Type: GrantFiled: October 11, 2011Date of Patent: September 13, 2016Assignee: Infineon Technologies AGInventors: Christian Pacha, Tim Schönauer, Michael Kund
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Patent number: 9444033Abstract: Magnetic memory devices and methods of manufacturing the same are disclosed. A method may include forming a magnetic tunnel junction layer on a substrate, forming mask patterns on the magnetic tunnel junction layer, and sequentially performing a plurality of ion implantation processes using the mask patterns as ion implantation masks to form an isolation region in the magnetic tunnel junction layer. The isolation region may thereby define magnetic tunnel junction parts that are disposed under corresponding ones of the mask patterns. A magnetic memory device may include a plurality of magnetic tunnel junction parts electrically and magnetically isolated from each other through the isolation region.Type: GrantFiled: June 20, 2014Date of Patent: September 13, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoonchul Cho, Ken Tokashiki
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Patent number: 9425798Abstract: A semiconductor device capable of reconfiguration, including: a plurality of logic units which configure an array and are connected to each other, wherein each logic unit includes a pair of a first and a second memory cell units, each of the first and the second memory cell units operates as a logic element when truth value table data is written in, which is configured so that a logic calculation of an input value specified by a plurality of addresses is output to a data line, and/or operates as a connection element when truth value table data is written in, which is configured so that an input value specified by a certain address is output to a data line to be connected to an address of another memory cell unit, a latter stage of the first memory cell unit includes a sequential circuit which synchronizes with a clock, and the logic units include, for each pair of the first and the second memory cell units, a selection unit which selectively outputs an address to the first or the second memory cell unit in acType: GrantFiled: February 14, 2013Date of Patent: August 23, 2016Assignee: TAIYO YUDEN CO., LTD.Inventors: Masayuki Satou, Koshi Sato
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Patent number: 9423970Abstract: A method and system are disclosed for improved block erase cycle life prediction and block management in a non-volatile memory. The method includes the storage device tracking information relating to a first erase cycle count at which the block erase time exceeded a predetermined threshold relative to a first erase cycle at which this occurred in other blocks. Blocks having a later relative erase cycle at which the erase time threshold is exceeded are assumed to have a greater erase cycle life than those that need to exceed the erase time threshold at an earlier erase cycle. This information is used to adjust wear leveling in the form of free block selection, garbage collection block selection and other block management processes. Alternatively or in combination, the predicted erase cycle life information is used to adjust program and/or erase parameters such as erase voltage and time.Type: GrantFiled: December 30, 2013Date of Patent: August 23, 2016Assignee: SanDisk Technologies LLCInventor: Neil Richard Darragh
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Patent number: 9424182Abstract: An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type.Type: GrantFiled: November 17, 2014Date of Patent: August 23, 2016Assignee: Mobile Semiconductor CorporationInventors: Louis Cameron Fisher, Stephen V. R. Hellriegel, Mohammad S. Ahmadnia
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Patent number: 9379716Abstract: An electronic circuit includes a plurality of delay elements configured to delay a clock signal by a delay time and to supply the delayed clock signal as a delay signal, the delay time being shorter with a higher power source voltage; a delay time acquisition unit configured to acquire the delay time based on a value of the delay signal; and a voltage controller configured to perform a voltage control process in which the power source voltage is controlled to be high in a case where the acquired delay time is longer than a predetermined desired value and the power source voltage is controlled to be low in a case where the acquired delay time is shorter than the predetermined desired value.Type: GrantFiled: February 19, 2015Date of Patent: June 28, 2016Assignee: Sony CorporationInventors: Takeshi Matsubara, Masahisa Tamura
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Patent number: 9378803Abstract: A method includes measuring a temperature of a sensor associated with a memory array. The method also includes calculating, at a voltage regulating device, an operating voltage based on the temperature and based on fabrication data associated with the memory array. The method further includes regulating, at the voltage regulating device, a voltage provided to the memory array based on the operating voltage.Type: GrantFiled: March 15, 2013Date of Patent: June 28, 2016Assignee: Qualcomm IncorporatedInventors: Stanley Seungchul Song, Zhongze Wang
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Patent number: 9312477Abstract: According to one embodiment, a semiconductor storage device is disclosed. The device includes first magnetic layer, second magnetic layer, first nonmagnetic layer between them. The first magnetic layer includes a structure in which first magnetic material film, second magnetic material film, and nonmagnetic material film between the first and second magnetic material films are stacked. The first magnetic material film is nearest to the first nonmagnetic layer in the first magnetic layer. The nonmagnetic material film includes at least one of Ta, Zr, Nb, Mo, Ru, Ti, V, Cr, W, Hf. The second magnetic material film includes stacked materials, including first magnetic material nearest to the first nonmagnetic layer among the stacked materials, and second magnetic material which is same magnetic material as the first magnetic material and has smaller thickness than the first magnetic material.Type: GrantFiled: December 17, 2014Date of Patent: April 12, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Watanabe, Katsuya Nishiyama, Toshihiko Nagase, Koji Ueda, Tadashi Kai
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Patent number: 9293209Abstract: An operating method of a semiconductor memory device includes performing a first read operation on main cells of a first page with an initial read voltage, performing a second read operation on the main cells of the first page with a read voltage corresponding to a read retry number when the number of error bits generated as results of performing the first read operation exceeds the number of error-correctable bits, and storing the read retry number in spare cells of the first page while the second read operation is performed, and repeatedly performing the second read operation and repeatedly storing the read retry number until the number of error bits generated as results of performing the second read operation becomes the number of error-correctable bits or less.Type: GrantFiled: March 13, 2013Date of Patent: March 22, 2016Assignee: SK Hynix Inc.Inventors: Jung Ryul Ahn, Seung Hwan Baik
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Patent number: 9263456Abstract: A semiconductor device comprises a semiconductor substrate, a first transistor including a gate insulating film and a gate electrode sequentially formed on the semiconductor substrate, a sidewall, an interlayer insulating film formed on the semiconductor substrate, and a contact plug which penetrates through the interlayer insulating film and reaches the semiconductor substrate. The sidewall is formed on a side surface of the gate electrode, and includes a first insulating film and a second insulating film formed on the first insulating film and containing a metal oxide different from the first insulating film.Type: GrantFiled: June 26, 2012Date of Patent: February 16, 2016Assignee: PS4 Luxco S.a.r.l.Inventor: Kanta Saino
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Patent number: 9224448Abstract: A non-volatile memory arrangement comprising a plurality of cells is disclosed. In one aspect, each cell comprises a memory element and a read selector in series. Further, the memory element is a nano-electro-mechanical switch comprising an anchor, a beam fixed to the anchor, a first and second control gate, for controlling the position of the beam, a first output node against which the beam can be positioned. The cell also comprises a read selector comprising a first selector terminal, a second selector terminal, the first selector terminal connected to the first output node. The first respectively second control gates of switches of a same word are connected together by a first respectively second write word line serving as control gate.Type: GrantFiled: December 2, 2014Date of Patent: December 29, 2015Assignees: IMEC vzw, Katholieke Universiteit LeuvenInventors: Stefan Cosemans, Ann Witvrouw, Maliheh Ramezani
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Patent number: 8996376Abstract: Techniques for improved text-to-speech processing are disclosed. The improved text-to-speech processing can convert text from an electronic document into an audio output that includes speech associated with the text as well as audio contextual cues. One aspect provides audio contextual cues to the listener when outputting speech (spoken text) pertaining to a document. The audio contextual cues can be based on an analysis of a document prior to a text-to-speech conversion. Another aspect can produce an audio summary for a file. The audio summary for a document can thereafter be presented to a user so that the user can hear a summary of the document without having to process the document to produce its spoken text via text-to-speech conversion.Type: GrantFiled: April 5, 2008Date of Patent: March 31, 2015Assignee: Apple Inc.Inventors: Christopher Brian Fleizach, Reginald Dean Hudson
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Patent number: 8897061Abstract: An MTJ cell includes a first metal layer elongated in the X-direction; a second metal layer separated from the first metal layer and elongated in the Y-direction; a magnetic tunnel junction (MTJ) interposed between the overlapping parts of the first and second metal layers and having extended parts not covered by the second metal layer, the MTJ including a pinned layer, a barrier layer, and a storage layer sequentially laminated; and a yoke spanning across the second metal layer, with both ends in the X-direction contacting the top surface of the extended parts of the storage layer not covered by the second metal layer, either directly or through an insulator. The planar shapes of the MTJ and the yoke possess a quantum easy axis in the X-direction and Y-direction, respectively.Type: GrantFiled: January 29, 2013Date of Patent: November 25, 2014Assignee: QuantuMag Consultancy Corp.Inventor: Joichiro Ezaki
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Patent number: 8814792Abstract: A vital-signs patch for a patient monitoring system that includes a housing containing a sensor that makes physiological measurements of a patient, a transmitter, a receiver, a memory, and a processor. The processor periodically takes a measurement from the sensor, converts the measurement to a data record, and stores the data record in the memory. Upon receipt of a signal from another device, the processor retrieves at least a portion of the data record, converts the retrieved portion of the data record to a vital-sign signal, and causes the transmitter to transmit the vital-sign signal to the other device.Type: GrantFiled: July 27, 2010Date of Patent: August 26, 2014Assignee: CareFusion 303, Inc.Inventors: Mark Raptis, Amir Jafri, Ganesh Kathiresan, Alison Burdett
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Patent number: 8724377Abstract: According to one embodiment, a memory device includes: a first signal line; a second signal line; a transistor; a first memory region; and a second memory region. The transistor controls a conduction of each of a current flowing between the first and the second signal lines and an opposite current. The first memory region has a first magnetic tunnel junction element. A magnetization direction thereof becomes parallel when a current flows in one direction, and the magnetization direction becomes antiparallel when a current in another direction. The second memory region has a second magnetic tunnel junction element. A magnetization direction thereof becomes parallel when a current flows in one direction, and becomes antiparallel when a current flows in another first direction.Type: GrantFiled: March 19, 2012Date of Patent: May 13, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takaya Yamanaka, Susumu Shuto, Yoshiaki Asao
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Patent number: 8688554Abstract: An architecture for a contactless smart card or payment device, where the smart card is intended for use in both commerce transaction payment and transit fare payment (or other venue access) environments. The payment device may function as both an electronic wallet for commerce transactions and as a transit system card, for access to and fare payment of transit services. Implementation of both functions may be achieved by use of a dynamic memory management system that permits data for both the payment and transit applications to be stored on the card, with the transit data and storage locations isolated from those used to store data intended for use in paying for commerce transactions. The transit application specific data may include access control data (keys, passwords, identification data) or data required for fare calculations (rates, historical data on system use), for example.Type: GrantFiled: March 23, 2009Date of Patent: April 1, 2014Assignee: Visa U.S.A. Inc.Inventors: Ayman Hammad, Phil Dixon, Brian Triplett
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Patent number: 8495354Abstract: Systems and methods of securely updating BIOS are disclosed. One such system comprises a reprogrammable memory, a first and a second register, and comparison logic. The reprogrammable memory comprises a first portion and a protect input. The protect input is configured to disallow writes to at least the first portion when the memory protect input is at a first level, and to allow writes to at least the first portion when the protect input is at a second level; The comparison logic is configured to drive a comparison output to a third level responsive to the first and second registers having equal values, and to drive the comparison output to a fourth level responsive to the first and second registers having different values. The comparison output is electrically coupled to the memory protect input.Type: GrantFiled: September 24, 2008Date of Patent: July 23, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Louis B. Hobson, Mark A. Piwonka, Gregory P. Ziarnik
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Patent number: 8374052Abstract: An information storage device includes a first portion comprising at first at least one magnetic track, each of the at least one magnetic track in the first portion including a first plurality of magnetic domains and being configured to store a first type of data therein and a second portion comprising a second at least one magnetic track, each of the at least one magnetic track in the second portion including a second plurality of magnetic domains and being configured to store a second type of data therein, the second type of data being related to the first type of data.Type: GrantFiled: May 6, 2010Date of Patent: February 12, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ho Jung Kim, Sang Beom Kang, Chul Woo Park, Hyun Ho Choi, Jong Wan Kim, Young Pill Kim, Sung Chul Lee
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Patent number: 8159871Abstract: A magnetoresistive memory cell includes an MTJ device and a select transistor. The select transistor includes a first conduction-type semiconductor layer, a gate electrode formed by disposing a gate insulating layer on top of the semiconductor layer, and first and second diffusion regions formed in the semiconductor layer to be spaced apart from each other and to have a second conduction type. A part of the semiconductor layer between the first and second diffusion regions is formed as an electrically floating body region. By using a high-performance select transistor with a floating body effect, high integration of a magnetoresistive memory device may be achieved.Type: GrantFiled: July 22, 2009Date of Patent: April 17, 2012Assignee: Hynix Semiconductor Inc.Inventor: Sung Woong Chung
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Patent number: 7960713Abstract: A vertical device geometry for a carbon-nanotube-based field effect transistor has one or multiple carbon nanotubes formed in a trench.Type: GrantFiled: December 30, 2008Date of Patent: June 14, 2011Assignee: Etamota CorporationInventors: Brian Hunt, James Hartman, Michael J. Bronikowski, Eric Wong, Brian Y. Lim
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Patent number: 7864564Abstract: Between the value of an electric current and the supply duration for which the electric current is supplied that cause magnetization reversal, there is the relation of monotonous decrease. This means that, as the supply duration is shortened, the threshold current value for causing the magnetization reversal is larger. Therefore, in terms of suppressing occurrence of read disturb, the read current supply duration may be shortened to increase the threshold value of the current causing the magnetization reversal and thereby ensure a sufficient read disturb margin. Therefore, the read current supply duration may be shortened relative to the write current supply duration ensure the read disturb margin and suppress occurrence of read disturb.Type: GrantFiled: December 14, 2009Date of Patent: January 4, 2011Assignee: Renesas Electronics CorporationInventor: Hideto Hidaka
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Patent number: 7852687Abstract: A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register.Type: GrantFiled: June 30, 2008Date of Patent: December 14, 2010Assignee: Hynix Semiconductor Inc.Inventor: Seung-Lo Kim
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Patent number: 7701701Abstract: A computer system has an internal mounting unit in which a device supporting a predetermined interface is mounted. The computer system includes an external mounting unit supporting the interface; a device controller comprising a plurality of communication channels, which can communicate with the device, for communicating with the device mounted in the internal mounting unit through a first communication channel of the plurality of communication channels and communicating with an external apparatus mounted in the external mounting unit through a second communication channel of the plurality of communication channels; and a switching controller for selectively connecting the external apparatus mounted in the external mounting unit to one of the second communication channel of the device controller and the device mounted in the internal mounting unit according to power-on/off of the system.Type: GrantFiled: January 17, 2007Date of Patent: April 20, 2010Assignee: Samsung Electronics, Co., Ltd.Inventor: Ja-goun Koo
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Patent number: 7675791Abstract: A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.Type: GrantFiled: June 8, 2009Date of Patent: March 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Youn-cheul Kim
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Patent number: 7672573Abstract: A system includes an integrated encoder comprising an optical storage controller for coupling to an optical storage medium, and a data encoder for coding input data coupled to the optical storage controller, a first external memory coupled to a first memory controller in the integrated encoder, and a second external memory coupled to a second memory controller in the integrated encoder. In one aspect, the integrated encoder further comprises a first memory arbiter for selectively directing access to the first external memory by the optical storage controller and the data encoder, and a second memory arbiter for selectively directing access to the second external memory by the optical storage controller and the data encoder.Type: GrantFiled: May 13, 2004Date of Patent: March 2, 2010Assignee: Sunplus Technology Co., Ltd.Inventor: Tzu-Hsin Wang
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Patent number: 7627733Abstract: A method and system for reading data from a non-volatile mass storage device is provided. The method includes, performing logical configuration for the non-volatile mass storage device, wherein file data is allocated addresses in a virtual logical address space; and data identified by virtual logical addresses is read by a host system. The system includes a file storage segment that reads and writes data on a file-by-file basis, allowing a host system to access data from the non-volatile mass storage device using a file interface format; and a logical interface segment that allows the host system to access data using logical addressing, wherein the host system is unaware of a storage format under which data is stored on a file-by-file basis.Type: GrantFiled: August 3, 2005Date of Patent: December 1, 2009Assignee: SanDisk CorporationInventor: Alan W. Sinclair
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Patent number: 7603592Abstract: A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.Type: GrantFiled: July 31, 2006Date of Patent: October 13, 2009Assignees: Hitachi, Ltd., Elpida Memory, Inc.Inventors: Tomonori Sekiguchi, Riichiro Takemura, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya
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Patent number: 7570455Abstract: Embodiments of the present invention provide a data storage device and a magnetic disk drive capable of maintaining the inside of a base in a hermetically sealed condition. In one embodiment, a data storage device includes a recording disk, a base having a through hole, a top cover having a tapping hole aligned with the through hole and a depressed portion with the tapping hole formed in a bottom thereof, and a screw inserted through the through hole into threaded engagement with the tapping hole and having a head which comes into close contact with an outer surface of the base. The top cover is fitted inside the base in a state in which the depressed portion is positioned on the base side, and the bottom of the depressed portion comes into close contact with the base in the threadedly engaged state of the screw and in an area which surrounds the through hole.Type: GrantFiled: May 25, 2005Date of Patent: August 4, 2009Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Takaaki Deguchi, Mutsuro Ohta, Kanako Abe, Akira Morita
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Patent number: 7554878Abstract: A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.Type: GrantFiled: August 29, 2006Date of Patent: June 30, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Youn-cheul Kim
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Patent number: 7449710Abstract: A memory device including a phase change element and a vacuum jacket. The device includes a first electrode element; a phase change element in contact with the first electrode element; an upper electrode element in contact with the phase change element; a bit line electrode in contact with the upper electrode element; and a dielectric fill layer surrounding the phase change element and the upper electrode element, spaced from the same and sealed by the bit line electrode to define a vacuum jacket around the phase change element and upper electrode element.Type: GrantFiled: April 21, 2006Date of Patent: November 11, 2008Assignee: Macronix International Co., Ltd.Inventor: Hsiang Lan Lung
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Patent number: 7443707Abstract: A method of using an MTJ MRAM cell element having two magnetization states of greater and lesser stability. During switching, the free layer is first placed in the less stable state by a word line current, so that a small bit line current can switch its magnetization direction. After switching, the state reverts to its more stable form as a result of magnetostatic interaction with a SAL (soft adjacent layer), which is a layer of soft magnetic material formed on an adjacent current carrying line, which prevents it from being accidentally rewritten when it is not actually selected and also provides stability against thermal agitation.Type: GrantFiled: April 2, 2007Date of Patent: October 28, 2008Assignees: Headway Technologies, Inc., Applied Spintronics, Inc.Inventors: Yimin Guo, Po-Kang Wang, Xizeng Shi, Tai Min
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Patent number: 7405958Abstract: According to the semiconductor memory device of this invention, an XP type MRAM cell array and an STr type MRAM cell array are formed on a single chip. The XP type MRAM cell array is laid over the STr type MRAM cell array to form a layered structure. The STr type MRAM cell array serves as a work memory area, while the XP type MRAM cell array serves as a data storage area. A cell of the XP type MRAM cell array and a cell of the STr type MRAM cell array may be connected to a same bit-line. By passing predetermined current through the bit-line, and passing current through a first word-line connected to the cell of the XP type MRAM cell array, and through a second word-line connected to the cell of the STr type MRAM cell array, it is possible to simultaneously write data into the cells of the XP and STr type MRAM cell arrays.Type: GrantFiled: June 18, 2003Date of Patent: July 29, 2008Assignee: NEC Electronics CorporationInventor: Takeshi Okazawa
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Patent number: 7358520Abstract: A semiconductor memory cell, a method for fabricating it and a semiconductor memory device. A phase change material region of a storage element of the semiconductor memory cell has been or is formed as a lining region of a wall region of a contact recess which passes all the way through an insulation region between a first electrode device and a second electrode device. Furthermore, the space or region of the contact recess which is not taken up by the material region of the storage element has been or is made substantially electrically insulating.Type: GrantFiled: March 9, 2005Date of Patent: April 15, 2008Assignee: Infineon Technologies AGInventors: Cay-Uwe Pinnow, Klaus-Dieter Ufert
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Patent number: 7336556Abstract: A non-volatile magnetic memory device is proposed, which provides sufficient magnetic shielding performance for external magnetic fields. A first magnetic shield layer 60a and a second magnetic shield layer 60b, both made of a soft magnetic metal, are formed respectively on the bottom surface of the transistor section 20, which is the mounting side of the MRAM device 10, and on the top surface of the bit line 50, which is opposite to the bottom surface of the mounting side of the MRAM device 10. On the second magnetic shield layer 60a, a passivation film 70 is formed. The magnetic flux penetrated from the external magnetic field, is suppressed below the inversion strength of the MRAM device 10, thereby improving reliability.Type: GrantFiled: July 2, 2003Date of Patent: February 26, 2008Assignee: Sony CorporationInventors: Katsumi Okayama, Kaoru Kobayashi, Makoto Motoyoshi
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Patent number: 7323903Abstract: The present invention is directed to a soft core logic circuit implemented in a PLD that estimates an appropriate phase delay and applies the phase shift to a read strobe signal to align its rising and falling edges at the center of a data sampling window associated with a group of read data signals. The soft core logic circuit dynamically determines an appropriate phase-shift value for the read strobe signal and adjusts the phase-shift to accommodate the environmental changes. The soft core logic circuit also introduces into the PLD various intermediate signals from a phase-shift estimator and a programmable phase delay chain.Type: GrantFiled: September 11, 2006Date of Patent: January 29, 2008Assignee: Altera CorporationInventors: Andy L. Lee, Brian D. Johnson
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Patent number: 7317250Abstract: A high density memory card assembly having application for USB drive storage, flash and ROM memory cards, and similar memory card formats. A cavity is formed through a rigid laminate substrate. First and second digital memory devices (e.g., TSOP packages or bare semiconductor dies) are located within the cavity so as to be recessed relative to the top and bottom of the substrate. The recessed first and second memory devices are arranged in spaced, face-to-face alignment with one another within the cavity. The first and second memory devices are covered and protected by respective first and second memory packages that are located on the top and bottom of the substrate. By virtue of the foregoing, the memory package density of the assembly can be increased without increasing the height or area consumed by the assembly for receipt within an existing external housing.Type: GrantFiled: September 30, 2004Date of Patent: January 8, 2008Assignee: Kingston Technology CorporationInventors: Wei H. Koh, David Chen
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Patent number: 7206239Abstract: Function circuits composing one function macro are divided and mounted on plural chips, plural internal clock signals having different phases with one another are generated based on a clock signal to be a reference, a phase of a clock signal supplied to the function circuits within the chips is adjusted based on a result of a test operation performed by using a selected internal clock signal, a clock signal with an optimal phase is obtained from among the plural internal clock signals having the different phases with one another, and a skew generated by being divided into the plural chips is adjusted automatically to thereby realize a proper operation of the circuits as a whole.Type: GrantFiled: October 28, 2005Date of Patent: April 17, 2007Assignee: Fujitsu LimitedInventors: Kazuhiko Kikuchi, Masaya Kitagawa, Jun Masuko
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Patent number: 7137085Abstract: A system and method for wafer level global bitmap characterization include determining chip level defect data bitmaps from a semiconductor wafer, and consolidating the chip level defect data bitmaps into a global wafer level bitmap that characterizes substantially the entire wafer failure configuration. The global wafer level bitmap is then analyzed and compared with other global wafer level bitmaps to develop correlations thereamong and develop global wafer level bitmap definitions for conducting at least one of wafer-to-wafer, boat-to-boat, and lot-to-lot process analysis based upon the global wafer level bitmap definitions.Type: GrantFiled: June 1, 2004Date of Patent: November 14, 2006Assignee: Advanced Micro Devices, Inc.Inventors: John J. Wang, Siu May Ho, Jeffrey P. Erhardt, Srikanth Sundararajan, David C. Newbury, Shivananda S. Shetty, Paul J. Steffan, Franklyn Shihyu Wu
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Patent number: 7098472Abstract: A two-terminal NDR device can be formed by coupling the gate and drain of an NDR-capable FET, such that the coupled gate and drain form a first terminal and the source of the NDR-capable FET forms the second terminal. By applying an appropriate body bias between the body and source of an NDR-capable FET configured in this manner, the NDR-capable FET can be forced to operate with a negative threshold voltage, thereby allowing the resulting two-terminal device to exhibit the desired NDR characteristics. This two-terminal device can, for example, be used as a load element in a static random access memory (SRAM) cell and various other circuits where the NDR behavior of the device would be beneficial.Type: GrantFiled: September 15, 2005Date of Patent: August 29, 2006Assignee: Progressant Technologies, Inc.Inventor: Tsu-Jae King
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Patent number: 7072207Abstract: For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to write the K-bit write data are connected in series in a single current path. When data having different levels are written through adjacent selected bit lines, the selected bit lines are connected to each other at their one ends or the other ends, so that a bit line write current flowing through the former selected bit line is directly transmitted to the latter selected bit line. On the other hand, when data having the same level are written through adjacent selected bit lines, a bit line write current flowing through the former selected bit line is turned back by the corresponding current return line, and then transmitted to the latter selected bit line.Type: GrantFiled: February 13, 2004Date of Patent: July 4, 2006Assignee: Renesas Technology Corp.Inventor: Tsukasa Ooishi
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Patent number: 7057950Abstract: A semiconductor device performs read or write when read or write command with auto-precharge function is input. The semiconductor device does not carry out the auto-precharge operation until a predetermined auto-precharge delay time passes. Therefore, page mode can be performed while using read or write command with auto-precharge function.Type: GrantFiled: November 13, 2003Date of Patent: June 6, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-Yang Lee
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Patent number: 7054188Abstract: A magnetic memory device includes a memory cell array including MTJ elements provided at the coordinates (x, y). First write lines extend in a direction neither perpendicular nor parallel to the magnetization easy axis direction of the MTJ elements. One and the other end of one first write line pass an upper or lower periphery of the memory cell array and a left or right periphery of the memory cell array, respectively. The first write lines and second write lines sandwich the MTJ elements. First write line drivers are connected to both ends of the first write lines, one and the other end of a pair of the first write line drivers connected to ends of one first write lines are located outside the upper or lower periphery and outside the left or right periphery, respectively. Second write line drivers are connected to both ends of the second write lines.Type: GrantFiled: December 16, 2004Date of Patent: May 30, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Ryousuke Takizawa, Junichi Miyamoto, Yoshihisa Iwata
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Patent number: 6990012Abstract: The present invention provides a magnetic memory. In one embodiment, the magnetic memory includes a first line having a first cross-sectional area. A second line is provided having a second cross-sectional area different from the first cross-sectional area. A magnetic memory cell stack is positioned between the first line and the second line.Type: GrantFiled: October 7, 2003Date of Patent: January 24, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kenneth Kay Smith, Frederick A. Perner
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Patent number: 6956765Abstract: The magneto-resistance effect element includes: a first ferromagnetic layer serving as a magnetization fixed layer; a magnetization free layer including a second ferromagnetic layer provided on one side of the first ferromagnetic layer, a third ferromagnetic layer which is formed on an opposite side of the second ferromagnetic layer from the first ferromagnetic layer and has a film face having an area larger than that of the second ferromagnetic layer and whose magnetization direction is changeable by an external magnetic field, and an intermediate layer which is provided between the second ferromagnetic layer and the third ferromagnetic layer and which transmits a change of magnetization direction of the third ferromagnetic layer to the second ferromagnetic layer; and a tunnel barrier layer provided between the first ferromagnetic layer and the second ferromagnetic layer.Type: GrantFiled: November 19, 2003Date of Patent: October 18, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Saito, Katsuya Nishiyama, Shigeki Takahashi