Abstract: In a memory consisting of a matrix of memory cells, each of which is accessible by rows and columns and is connected to write and read circuits which are used, respectively, to programme them in two states, "1" or "0", depending on the input data, and to read the programmed state, the memory cells being of the type that require a programming current in order to be programmed in a first state or "1" and require no current to be programmed in a second state or "0", the safety device consists of a simulation circuit activated by data corresponding to a "0" programming operation and delivering a current identical to that of a memory cell in the "1" programming condition.

Abstract: An alpha particle resistant memory cell and array with complementary, differential data in, data out and write enable inputs capable of independent, simultaneous read/write operations. During write operations, clocked differential write and data inputs steer cell current to induce differential cell voltages indicative of the stored data. During read operations, a read select input shifts the voltage levels of the selected cell to produce a distinguishable output which dominates over the other cells to appropriately steer current at a sense amplifier to identify the binary cell contents. A 64 row by 12 bit register stack, with split word write, master reset and read enable is also disclosed.

Abstract: A semiconductor memory for storing binary data which may be accessed more rapidly is disclosed which semiconductor memory includes a pair of differential bit lines for receiving signals corresponding to the binary data; a semiconductor memory device for storing binary data is coupled between the differential bit lines to provide signals corresponding to the binary data when reading the semiconductor memory device during the read cycle. A semiconductor clamping device is coupled between the differential bit lines to selectively provide a current path between the differential bit lines during the reading of the semiconductor device.

Abstract: Apparatus and methods are disclosed for providing an increased flexibility and rate in processing data in a random access memory (RAM) system. The apparatus comprises, in a first embodiment, a switching circuit which is coupled to the word lines of the RAM array and which is selectively operable in two modes. The switching circuit operates in a first mode to transmit word line signals to a single row of memory cells in the RAM array in accordance with principles well known in the prior art. The switching circuit is responsive to a control circuit, and operates in a second mode to alter, along the row of memory cells in the RAM array, the word line signal path, to provide simultaneous accessing of portions of at least two adjacent rows of memory cells in the RAM array. Such simultaneous accessing allows the processing of more data through the memory system that was previously possible in accordance with principles known in the prior art.

Abstract: A programming arrangement for programmable matrices which have a plurality of memory elements, input terminals for addressing the elements, input/output terminals for receiving a signal from an addressed element when the matrix is operated in a READ mode, and for receiving programming signals when the matrix is operated in a PROGRAM mode, and a programming current supply source. The arrangement provides for controlling the flow of programming current to any of the memory elements by application of programming signals to less than all of the input/output terminals. A programming decoder is provided having inputs connected to the input/output terminals and outputs connected to apparatus for controlling the flow of programming current. The decoder expands the programming utility of the input/output terminals and, thus, allows for programming of redundant rows of columns, programmable output polarity apparatus, and other special matrix features via the available device pins.

Abstract: An electronically selectable high performance data path switch which allows one input to drive two data buses or to have two inputs drive the two independently.

Abstract: A semiconductor memory circuit including a charge absorbing circuit. The charge absorbing circuit absorbs at least a current induced by a voltage increase in the word line occurring soon after the word line is switched from a selection state to a nonselection state.

Abstract: A memory circuit is provided wherein the speed of the downward transition of the memory cell is increased. A plurality of memory cells are coupled between a select line and a current drain line. A first means is coupled to the select line for providing current to the plurality of memory cells and is responsive to a select signal having first and second states. A first PNP transistor has an emitter coupled to the current drain line for drawing any charge from the plurality of memory cells when the select signal transitions downward. A second means is coupled to the base of the first PNP transistor and is responsive to the select signal for setting the current level in said first PNP transistor. A second embodiment additionally includes a second PNP transistor having an emitter coupled to the select line and a collector coupled to said second supply voltage terminal for removing charge stored on the select line.

Abstract: A current bypass for a microelectric memory, such as a static RAM, diverts word line discharge current such that the current does not flow through the memory cells of a selected word line or along an upper word line conductor. In a first embodiment, the bypass comprises a resistor R1 (R2) and a diode D10 (D20) in series and coupled between an upper word line conductor 50 and word line discharge current source V.sub.CC, and a lower word line conductor 51 and word line discharge current sink 42. In another embodiment of the invention, a transistor Q10 (Q20) is used in lieu of the diode. By bypassing current from the upper word line conductor and word line memory cells, metal migration is eliminated and narrower metal lines may be used to form the word lines. By eliminating a flow of steady state discharge current through the memory cells, memory cell current saturation is eliminated.

Abstract: Circuitry for rapidly discharging a row of RAM cells upon deselection of the word line. The word line switching transistor collector current is sensed and corresponding voltage level signals are applied to a second switching transistor between the bottom word line of the memory row and a large dump current source. The emitter of the second switching transistor is clamped at a level that will permit the switching transistor to turn on only when there is no emitter current through the word line switching transistor to thereby rapidly discharge the capacitive row of memory cells and therefore improve the operating speed of the memory.

Abstract: An adaptive word line pull-down circuit steers a pull-down current only to the word being pulled down and only for the time when that word is being pulled down. The time that it takes for the bottom word line to fall controls how long the pull-down current is steered to the falling word.

Abstract: A word driver in a decoder circuit of a semiconductor device has either a matrix of diodes or a multi-emitter transistor, each of said diodes or emitters of said multi-emitter transistor being connected between one of the decoder lines and a junction of a resistor circuit which is connected to a power source and another transistor which is connected to one of the word lines.

Abstract: A switch for selecting internal circuit options in MOS/LSI circuits without altering the circuit layout on a semiconductor chip by selectively implanting channels of field-effect transistors such that selected circuit-option lines are coupled to a designated line. Switches may be constructed with multiple inputs and a single output, or with multiple outputs and a single input, or with multiple inputs and multiple outputs. A bidirectional switch may also be constructed by controlling the gate potential of each transistor connecting one of the option lines to the designated line with a two-input switch for selecting either a high or a low gate potential.

Abstract: An output circuit having an output switch controlled by a current steering means which steers the emitter current from the selected memory storage location to the output switch as a function of magnitude to provide an appropriate logic voltage output. An enable switch interconnects the storage matrix and the output circuit.A fusing circuit includes a current sink connected in parallel with the output circuit for developing sufficient current through a selected storage location whenever a voltage is applied at the output and the operating voltage for the memory storage matrix is raised.