Current Steering Patents (Class 365/242)
  • Patent number: 8804451
    Abstract: Power sources, backup power circuits, power source control circuits, data storage devices, and methods relating to controlling application of power to a node are disclosed. An example power source includes an input, backup power source, and a backup power source control circuit. The input is configured to be coupled to a primary power source and further configured to couple the primary power source to the output when the input is coupled to the primary power source. The backup power source control circuit is configured to control a current path from the backup power source to the output based at least in part on a voltage applied to the input.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Douglas Todd Hayden
  • Patent number: 8773885
    Abstract: A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a plane; a second memory cell including a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that selects the second variable resistance element; and a second memory layer provided with more than one such second memory cell arranged in a plane; wherein more than one such second memory layer is stacked over the first memory layer.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: July 8, 2014
    Assignee: Spansion LLC
    Inventor: Naoharu Shinozaki
  • Patent number: 8630145
    Abstract: Some embodiments include switches that have a graphene structure connected to a pair of spaced-apart electrodes. The switches may further include first and second electrically conductive structures on opposing sides of the graphene structure from one another. The first structure may extend from one of the electrodes, and the second structure may extend from the other of the electrodes. Some embodiments include the above-described switches utilized as select devices in memory devices. Some embodiments include methods of selecting memory cells.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: January 14, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 8547721
    Abstract: Disclosed is a resistive memory device. In the resistive memory device, at least one variable resistance region and at least one switching device may be horizontally apart from each other, rather than being disposed on the same vertical axis. At least one intermediate electrode, which electrically connects the at least one variable resistance region and the at least one switching device, may be between the at least one variable resistance region and the at least one switching device.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungeon Ahn, Kihwan Kim, Changjung Kim, Myungjae Lee, Bosoo Kang, Changbum Lee
  • Patent number: 8514649
    Abstract: Power sources, backup power circuits, power source control circuits, data storage devices, and methods relating to controlling application of power to a node are disclosed. An example power source includes an input, backup power source, and a backup power source control circuit. The input is configured to be coupled to a primary power source and further configured to couple the primary power source to the output when the input is coupled to the primary power source. The backup power source control circuit is configured to control a current path from the backup power source to the output based at least in part on a voltage applied to the input.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 20, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Todd Hayden
  • Patent number: 8514608
    Abstract: A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate, a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, an emitter contact layer disposed in a second side of the semiconductor substrate, and a base layer separating the plurality of collector contacts from the emitter contact layer. Each collector contact is electrically isolated from each other. A resistive sense memory cells is electrically coupled to each collector contacts and a bit line. The base layer and the emitter contact layer provide an electrical path for the plurality of collector contacts.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: August 20, 2013
    Assignee: Seagate Technology LLC
    Inventor: Maroun Georges Khoury
  • Patent number: 8498141
    Abstract: A memory cell array includes a memory cell having a variable resistance element and disposed between first and second wirings. A control circuit provides a selected first wiring with a first voltage and provide a selected second wiring with a second voltage having a lower voltage value than the first voltage. A current limitation circuit controls a cell current below a first current. It includes a first current generation circuit for storing a cell current at a first point of time and generating a first current of ? times the stored cell current. It also includes a second current generation circuit for generating a second current of (?/?) times the cell current at a second point of time. A determination circuit outputs a control signal when the second current exceeds the stored current. The first current generation circuit newly stores a stored current according to the control signal.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: July 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiko Sasaki, Mizuki Uda
  • Patent number: 8483006
    Abstract: Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. The access transistors may have gates that are controlled by an address signal. The address signal may be asserted during read/write operations to turn on the access transistors so that read/write data can be passed through the access transistors. The voltage level to which the address signal is raised during read/write operations may be adjusted using programmable voltage biasing circuitry. A number of integrated circuits may be tested during device characterization procedures to determine the amount by which the address signal should be adjusted using the programmable voltage biasing circuit so that the memory elements in the integrated circuits satisfy design criteria.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: July 9, 2013
    Assignee: Altera Corporation
    Inventors: Hao-Yuan Howard Chou, Wei Zhang, Haiming Yu
  • Patent number: 8462580
    Abstract: A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: June 11, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Peter Rabkin, George Samachisa, Roy E. Scheuerlein
  • Patent number: 8456947
    Abstract: Some embodiments include switches that have a graphene structure connected to a pair of spaced-apart electrodes. The switches may further include first and second electrically conductive structures on opposing sides of the graphene structure from one another. The first structure may extend from one of the electrodes, and the second structure may extend from the other of the electrodes. Some embodiments include the above-described switches utilized as select devices in memory devices. Some embodiments include methods of selecting memory cells.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: June 4, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 8358531
    Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: January 22, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Gurtej Sandhu
  • Patent number: 8295123
    Abstract: In a current rectifying element (10), a barrier height ?A of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height ?B of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1<X2). Therefore, the barrier layer (11) has a barrier height in which the shape changes in a stepwise manner and the height of the center region 14 is large.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: October 23, 2012
    Assignee: Panasonic Corporation
    Inventors: Takeshi Takagi, Takumi Mikawa, Koji Arita, Mitsuteru Iijima, Takashi Okada
  • Patent number: 8284588
    Abstract: In a non-volatile logic circuit, a first input electrode and a second input electrode are formed on a semiconductor layer and interposed between an electric current source electrode and an output electrode in a plan view. The first input electrode is next to the second input electrode along the a direction orthogonal to the direction between the electric current source electrode and the output electrode. A method of operating the non-volatile logic circuit includes a step of writing one state selected from four states by applying voltages to the first input electrode and the second input electrode, respectively, and a step of measuring current generated by applying the voltage between the electric current power electrode and the output electrode to determine on the basis of the current, which of the high or low resistant state the non-volatile logic circuit has.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: October 9, 2012
    Assignee: Panasonic Corporation
    Inventor: Yukihiro Kaneko
  • Patent number: 8274849
    Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: September 25, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Philippe Bauser
  • Patent number: 8270202
    Abstract: Control circuitry provides control signals to a common X line and a set of Y lines to change a first data storage element of the multiple data storage elements from a first state to a second state by passing a current into the first data storage element from a different Y line through a different storage element. The control circuitry provides control signals to the common X line and the set of Y lines to sequentially change additional data storage elements of the multiple data storage elements from the first state to the second state by passing currents into the additional data storage elements from data storage elements of the multiple data storage elements that were previously changed to the second state and their associated different Y lines.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: September 18, 2012
    Assignee: SanDisk 3D, LLC
    Inventor: Roy E. Scheuerlein
  • Patent number: 8213259
    Abstract: A non-volatile memory cell and associated method of use. In accordance with some embodiments, the memory cell includes a transistor comprising source and drain regions spanned by a gate region, and a resistive sense element (RSE) connected to the drain region of the transistor. The RSE is programmed to a first resistance by flowing a first write current through the RSE and then through the drain and source regions of the transistor. The RSE is programmed to a second resistance by flowing a second write current through the drain region and then through the RSE, the second write current bypassing the source region.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: July 3, 2012
    Assignee: Seagate Technology LLC
    Inventors: Daniel S. Reed, Yong Lu, Andrew John Carter, Hai Li
  • Patent number: 8208285
    Abstract: A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: June 26, 2012
    Assignee: Seagate Technology LLC
    Inventors: Maroun Georges Khoury, Hyung-Kyu Lee, Peter Nicholas Manos, Chulmin Jung, YoungPil Kim
  • Patent number: 8081523
    Abstract: A circuit comprises an array of memory cells (10). A plurality of sensing circuits (20), are coupled to the output (14) of respective memory cells (10), for comparing the output signal of the respective one of the memory cells (10) with a reference signal to form a data signal from the output signal from the respective one of the memory cells (10). A reference generator circuit (24, 26) forms the reference signal from a sum wherein each respective one of the memory cells (10) of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells (10). The contributions are equalized for output signal values at more than a saturating distance above the reference signal, and the contributions are equalized for output signal values at more than the saturating distance below the reference signal.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: December 20, 2011
    Assignee: NXP B.V.
    Inventors: Victor Martinus Van Acht, Nicolaas Lambert, Pierre Hermanus Woerlee
  • Patent number: 7995413
    Abstract: A memory device is a provided that includes memory cells situated at the intersection of lines and columns, and a dummy path including a first dummy column having two bit lines to which there are connected dummy memory cells, and a circuit adapted to select at least one of the dummy memory cells to discharge one of the dummy bit lines. The dummy path also includes at least one second dummy column adapted to generate a dummy leakage current (representing a leakage current of a column of the memory device selected in read mode), and a circuit adapted to copy the dummy leakage current to the one dummy bit line, so that the discharge of the one dummy bit line also depends on the dummy leakage current.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: August 9, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Franck Genevaux, Alban Forichon
  • Patent number: 7969771
    Abstract: Various embodiments of the present invention are generally directed to an apparatus and method associated with a semiconductor device with thermally coupled phase change layers. The semiconductor device comprises a first phase change layer selectively configurable in a relatively low resistance crystalline phase and a relatively high resistance amorphous phase, and a second phase change layer thermally coupled to the first phase change layer. The second phase change layer is characterized as a metal-insulator transition material. A programming pulse is applied to the semiconductor device from a first electrode layer to a second electrode layer to provide the first phase change layer with a selected resistance.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: June 28, 2011
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Michael Xuefei Tang, Yuankai Zheng, Patrick Ryan
  • Patent number: 7957206
    Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: June 7, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Philippe Bauser
  • Patent number: 7920406
    Abstract: A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; configuring a rectifying element in series with each of the resistive memory devices at a second end thereof; configuring an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and forming a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Geoffrey W. Burr, Kailash Gopalakrishnan
  • Patent number: 7760569
    Abstract: A memory device in a semiconductor substrate includes at least one temperature sensor to provide a temperature dependent signal and at least one circuit to dissipate heat in response to a control signal. A control circuit is coupled to the at least one circuit and is operable to generate the control signal in response to the temperature dependent signal.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: July 20, 2010
    Assignee: Qimonda AG
    Inventors: Wolfgang Ruf, Martin Schnell, Rainer Kömmling
  • Patent number: 7649781
    Abstract: A memory device is disclosed. A reference device of the memory includes a trimmable current source and a fixed current source. Currents provided by each source are summed to provide a reference current to a sense amplifier. The sense amplifier senses the state of a bit cell by comparing a current from the bit cell, representative of a logic value, to the reference current. By basing the reference current on both a fixed and a trimmable current source, the reference device can be trimmed to compensate for process and operating characteristics of the device, while maintaining a minimum reference current in the event of a disturb mechanism that results in loss of the current provided by the trimmable current source.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: January 19, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ronald J. Syzdek, Gowrishankar L. Chindalore
  • Patent number: 7613058
    Abstract: Radiation hardening, detection and protection design methods are disclosed. An example write drive circuit is disclosed having radiation hardened analog circuitry. A passive transistor is provided to generate a radiation photo-current to offset any net radiation photo-current of the operational circuitry. Using this technique, a radiation hardened reference-mirror control circuit provides a switched write current for setting the logical state of MRAM bits during a radiation event, for instance. A radiation detector and radiation hardened logic gates are further provided for inhibiting the write current when a radiation level is above a predetermined level.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: November 3, 2009
    Assignee: Honeywell International Inc.
    Inventor: Lance L. Sundstrom
  • Patent number: 7613039
    Abstract: The invention concerns an arrangement for controlling a non-volatile memory arrangement for a circuit comprising: a micromechanical element coupled to a substrate; the micromechanical element being responsive to deflection means arranged on the substrate to control the movement of the micromechanical element between one or more stable states. In addition, the invention concerns a method for controlling a non-volatile memory device arrangement comprising: applying one or more signals to a deflection means for moving a micromechanical element between one or more stable states. To enhance the efficacy of the invention there is further provided a shorting circuit for use in the non-volatile memory arrangement.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: November 3, 2009
    Assignee: Cavendish Kinetics B.V.
    Inventor: Robert Kazinczi
  • Patent number: 7542349
    Abstract: The invention provides a semiconductor memory device where a circuit area is minimized and a voltage drop in a high voltage supply path to a source line is reduced. An output of a high voltage generation circuit is connected to a source line through a first transfer gate, and connected to a word line through a second transfer gate. The first transfer gate is configured of a P-channel type MOS transistor of which on and off are controlled by a write enable signal, and the second transfer gate is configured of a P-channel type MOS transistor of which on and off are controlled by an erase enable signal. A third transfer gate supplying the output of the high voltage generation circuit to the source line without through a high voltage switching circuit is further provided. The third transfer gate is configured of a P-channel type MOS transistor and an inverted output of the high voltage switching circuit is applied to the gate thereof.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: June 2, 2009
    Assignees: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventors: Toshiki Rai, Sadao Yoshikawa
  • Patent number: 7453716
    Abstract: In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: November 18, 2008
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Sung-min Kim, Eun-jung Yun, Jong-soo Seo, Du-eung Kim, Beak-hyung Cho, Byung-seo Kim
  • Publication number: 20080219040
    Abstract: A method of addressing a memory cell includes applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. In addition, a memory includes a memory cell and a control circuit configured to address the memory cell by applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse.
    Type: Application
    Filed: March 8, 2007
    Publication date: September 11, 2008
    Inventor: Jan Boris Philipp
  • Patent number: 7352816
    Abstract: An oversampling delay is provided between clock and data signals by steering a current between first and second nodes. The first node is coupled to an input differential pair of a clock interpolator and a delayed differential pair of a data interpolator. The second node is coupled to an input differential pair of the data interpolator and a delayed differential pair of the clock interpolator. First clock and data signals are provided to a first data sampling element and, respectively, to the clock and data interpolators. Second clock and data signals, respectively output from the clock and data interpolators, are provided to a second data sampling element. Additional data sampling elements may be linked to form a longer chain of data sampling elements.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: April 1, 2008
    Assignee: Agilent Technologies, Inc.
    Inventor: Reed Glenn Wood, Jr.
  • Patent number: 7319625
    Abstract: A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: January 15, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Yeong-Jar Chang, Kun-Lun Luo, Jung-Chi Ho, Cheng-Wen Wu, Chin-Jung Su
  • Patent number: 7272071
    Abstract: The present invention provides systems and methods that utilize inductive current steering to improve logic circuit performance by mitigating propagation delays associated with conventional transistor current steering. The system and methods employ RF transformers, wherein energizing primary windings induce current in associated secondary windings. In one aspect, a single clock bus is employed to induce the current, which is routed via respective ends of the secondary winding to emitter leads of the transistors. This current and voltage is 180 degrees out-of-phase such that one transistor is “on” while the other is “off,” which generates a differential output. In another aspect, a differential clock signal is employed to induce the current in secondary windings and associated transistor emitters.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: September 18, 2007
    Assignee: Northrop Grumman Corporation
    Inventor: Johannes K. Notthoff
  • Patent number: 7071565
    Abstract: A three dimensional circuit structure including tapered pillars between first and second signal lines. An apparatus including a first plurality of spaced apart coplanar conductors disposed in a first plane over a substrate; a second plurality of spaced apart coplanar conductors disposed in a second plane, the second plane parallel to and different from the first plane; and a plurality of cells disposed between one of the first conductors and one of the second conductors, wherein each of the plurality of cells have a re-entrant profile.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: July 4, 2006
    Assignee: Sandisk 3D LLC
    Inventors: Calvin K. Li, N. Johan Knall, Michael A. Vyvoda, James M. Cleeves, Vivek Subramanian
  • Patent number: 7057971
    Abstract: The present invention provides systems and methods that utilize inductive current steering to improve logic circuit performance by mitigating propagation delays associated with conventional transistor current steering. The system and methods employ RF transformers, wherein energizing primary windings induce current in associated secondary windings. In one aspect, a single clock bus is employed to induce the current, which is routed via respective ends of the secondary winding to emitter leads of the transistors. This current and voltage is 180 degrees out-of-phase such that one transistor is “on” while the other is “off,” which generates a differential output. In another aspect, a differential clock signal is employed to induce the current in secondary windings and associated transistor emitters.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: June 6, 2006
    Assignee: Northop Grumman Corporation
    Inventor: Johannes K. Notthoff
  • Patent number: 7012846
    Abstract: A sense amplifier which senses whether current is present on a bit line, and generates one logical value if current is present and another logical value if current is not present. As the sense amplifier can be implemented to generate such logical values with a current signal of low strength, memory arrays with correspondingly low drive strength can be implemented. As a result, memory systems which consume minimal power and having high density can be provided. In addition, as the sense amplifiers can operate without any reference signals, the implementation of sense amplifiers may be simplified.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: March 14, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Suresh Balasubramanian, Stephen Wayne Spriggs, Bryan D. Sheffield, Mohan Mishra
  • Patent number: 6944063
    Abstract: In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in spare cells of only one page or distributed among header regions of multiple pages. The page or pages containing the block cycle count are initially read from each block that is being erased, the cycle count temporarily stored, the block erased and an updated cycle count is then written back into the block location. User data is then programmed into individual pages of the block as necessary. The user data is preferably stored in more than two states per memory cell storage element, in which case the cycle count can be stored in binary in a manner to speed up the erase process and reduce disturbing effects on the erased state that writing the updated cycle count can cause.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: September 13, 2005
    Assignees: SanDisk Corporation, Kabushiki Kaisha Toshiba
    Inventors: Jian Chen, Tomoharu Tanaka
  • Patent number: 6857054
    Abstract: The present disclosure relates to a write-once storage device. In one arrangement, the storage device comprises write-once memory adapted to store data files, re-writable memory that contains a file access table, and a device controller that is configured to control operation of the storage device. In use, the storage device can be used to receive data to be stored from a host device, store the data within write-once memory of the storage device, and update a file access table stored in re-writable memory of the storage device so as to emulate a re-writable storage card.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: February 15, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Mark W. Minne
  • Patent number: 6826112
    Abstract: The invention includes a logic gate. The logic gate includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. A logic gate output is a function of charge on the charge holding device. The logic gate further includes a plurality of inputs. The plurality of inputs are electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of inputs is a first voltage potential. The invention also includes an address decoder. The address decoder includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. An address decoder output is a function of charge on the charge holding device. The address decoder further includes a plurality of address lines.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: November 30, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Joseph Ku, James Robert Eaton
  • Patent number: 6791874
    Abstract: A memory device having a cross point array of memory cells includes a temperature sensor and a reference memory cell. The temperature sensor senses the temperature of the memory device and data from the temperature sensor and the reference memory cell are used to update write currents used to program the array of memory cells. A method of calibrating the memory device involves detecting a temperature of the memory device, determining whether the temperature of the memory device has changed by a threshold value, and updating write current values if the temperature of the memory device changes by the threshold value. The write current values can be updated by data from the reference memory cell, or from write current values stored in a lookup table.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Lung T. Tran, Manoj K. Bhattacharyya
  • Patent number: 6791865
    Abstract: A memory device having a cross point array of memory cells includes a temperature sensor and a reference memory cell. The temperature sensor senses the temperature of the memory device and data from the temperature sensor and the reference memory cell are used to update write currents used to program the array of memory cells. A method of calibrating the memory device involves detecting a temperature of the memory device, determining whether the temperature of the memory device has changed by a threshold value, and updating write current values if the temperature of the memory device changes by the threshold value. The write current values can be updated by data from the reference memory cell, or from write current values stored in a lookup table.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Lung T. Tran, Manoj K. Bhattacharyya
  • Patent number: 6714443
    Abstract: For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to write the K-bit write data are connected in series in a single current path. When data having different levels are written through adjacent selected bit lines, the selected bit lines are connected to each other at their one ends or the other ends, so that a bit line write current flowing through the former selected bit line is directly transmitted to the latter selected bit line. On the other hand, when data having the same level are written through adjacent selected bit lines, a bit line write current flowing through the former selected bit line is turned back by the corresponding current return line, and then transmitted to the latter selected bit line.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: March 30, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Tsukasa Ooishi
  • Patent number: 6608790
    Abstract: A memory device includes a memory array having a substrate, an array of memory cells disposed over the substrate, row conductors coupled to the memory cells, and column conductors coupled to the memory cells. The memory device also includes current sources that generate variable write currents in response to temperature changes in the memory array. The variable write currents are generated to accommodate the change in coercivities of the memory cells as the temperature of the array changes. A current source can include a temperature sensor that provides a continuous, immediate output to the current sensor to ensure accurate adjustment of a write current generated by the current source. There is no need to halt operation of the memory device to calibrate the current source. In addition, the current source provides an accurate adjustment to the write current because the temperature used by the temperature sensor to generate the output may be taken contemporaneously with generation of the write current.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: August 19, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Lung T. Tran, Manoj K. Bhattacharyya
  • Patent number: 6236611
    Abstract: Apparatus and method for reducing peak program current in memories include providing a memory with an array of memory cells arranged in rows and columns and having a plurality of current terminals and sequentially supplying current to each current terminal of the plurality of current terminals. The array is fabricated in a semiconductor chip with connections to a current supply within the semiconductor chip including a plurality of layers of metal connected by vias in the semiconductor chip. In one embodiment, the array includes tunnel junction MRAM cells integrated into a semiconductor chip with current sources.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: May 22, 2001
    Assignee: Motorola, Inc.
    Inventor: Peter K. Naji
  • Patent number: 6222695
    Abstract: A write circuit for facilitating a write head for writing to a memory in a computer is described. The write circuit includes a supply voltage source configured to provide current to the write circuit. The write circuit further includes a current source coupled to the supply voltage source, the current source configured to maintain the current at a predetermined value. The write circuit further includes a switch coupled to the current source, the switch being configured to bypass the current source during a time when the current is changing.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: April 24, 2001
    Assignee: Siemens Microelectronics, Inc.
    Inventor: Ronald A. Canario
  • Patent number: 6034882
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Grant
    Filed: November 16, 1998
    Date of Patent: March 7, 2000
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, Paul Michael Farmwald, James M. Cleeves
  • Patent number: 5604711
    Abstract: A memory circuit with a low power programming voltage switch for reduced leakage current during a read operation. The apparatus includes a high voltage switch which, in a programming mode receives a high (e.g. programming) voltage and in another mode (reading) receives a normal range voltage, and a line driver which drivers a selection or non-selection voltage into word lines or column select lines into a memory array. During a read mode, the deselected line drivers and high voltage switches are operated in a reduced leakage current mode such that leakage current is forced through selected line drivers and their high voltage switches before being forced through the deselected line drivers such that the leakage current is limited to the number of selected line drivers.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: February 18, 1997
    Assignee: Cypress Semiconductor, Corporation
    Inventor: Sammy S. Y. Cheung
  • Patent number: 5506813
    Abstract: In a semiconductor memory apparatus having a cell array structure wherein occurrence of leak current is reduced and a margin at the time of sensing is increased, a plurality of memory transistors arranged in a matrix and having any one of four thresholds constitute banks in a column direction. The banks constitute memory cell arrays. A main bit line of Al is connected to three sub-bit lines via first selection transistors. A main ground line of Al is connected to two sub-ground lines via second selection transistors. Bank selection lines and word lines are formed to cross the main bit line and main ground line. Gates of the selection transistors are connected to the selection lines, and one selection line is connected to one selection transistor. Each of the sub-bit lines and sub-ground lines has a column of memory transistors which constitute a bank. A separation region (not shown) of a silicon oxide film, etc. is formed between the memory cell arrays to prevent leak current.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: April 9, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Mochizuki, Hideo Kato, Nobutake Sugiura
  • Patent number: 5392238
    Abstract: A semiconductor nonvolatile memory device according to the invention comprises a first cell block having with a current path and a plurality of memory cells, a second cell block having with a current path and a plurality of memory cells, the current path of the second cell block has an end connected to a corresponding end of the current path of the first cell block, a first line electrically connected to the other end of the current path of the first cell block, and a second line electrically connected to the other end of the current path of the second cell block. The first and second lines are made to operate a bit line and a source line, or vise versa, depending on which one of said cell blocks is selected for data retrieval.
    Type: Grant
    Filed: April 11, 1994
    Date of Patent: February 21, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryouhei Kirisawa
  • Patent number: 5163022
    Abstract: The disclosure includes feeding a current I.sub.R to only BIT lines selected, or feeding current I.sub.R transiently to only the BIT lines switched from unselected to selected states; and a sense amplifier for detecting the difference between the currents flowing in selected BIT lines to read out stored information, wherein current I.sub.R and cell current I.sub.cell have a relation of I.sub.R >I.sub.cell. The BiC MOS memory has high speed, low power and high integration density. Diodes are provided between the memory cell and the BIT lines.
    Type: Grant
    Filed: January 30, 1992
    Date of Patent: November 10, 1992
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Noriyuki Homma, Hiroaki Nambu, Kunihiko Yamaguchi, Tohru Nakamura, Youji Idei, Kazuo Kanetani, Kenichi Ohhata, Yoshiaki Sakurai, Hisayuki Higuchi
  • Patent number: 4905199
    Abstract: A circuit (50) is provided in a dynamic RAM (1) for detecting establishment of a substrate bias voltage (V.sub.BB) when the power is first turned on. A NAND gate (5d) in a clock generator circuit (10) immediately applies a high level signal to an inner circuit (11) when the power is turned on. Successively, the NAND gate (5d) applies a RAS signal to the inner circuit (11) in response to the establishment of V.sub.BB. Therefore, the dynamic RAM (1) is brought to a standby state immediately after the power is turned on and thereafter is controlled by the RAS signal. Consequently, flow of excessive current and latch-up immediately after the power is turned on can be prevented.
    Type: Grant
    Filed: August 5, 1988
    Date of Patent: February 27, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takayuki Miyamoto