Abstract: A method of and apparatus for connecting the sense current line in a cross-point memory array greatly reduces the effect of reverse leakage from unaddressed row or column lines. Separate sense line segments are coupled to separate stripes of row or column lines. Each sense line segment is connected to a sense diode, and each sense diode is connected to a sense bus. Each sense diode provides the current path for sensing on a selected row or column line, while allowing the leakage of only one diode per sense line segment for the unaddressed row or column lines. This arrangement results in wider margins for sensing the state of data cells in a cross-point memory array and simpler circuitry design for the memory array.

Abstract: Embodiments of the present invention provide memory modules that mitigate the problems associated with using address pins on memory modules to supply super voltages to memory devices on the memory modules. In one embodiment, the memory module has a memory device that has a test pin. A pin of the memory module is connected to the test pin. The pin of the memory module connects the test pin to one of ground, a power source, or an open circuit when the memory module is inserted in a socket for operation. The pin of the memory module can be used to selectively supply a test voltage to the test pin when the memory module is not connected for operation.

Abstract: A cross point memory array is fabricated on a substrate with a plurality of memory cells, each memory cell including a diode and an anti-fuse in series. First and second conducting materials are disposed in separate strips on the substrate to form a plurality of first and second orthogonal electrodes with cross points. A plurality of semiconductor layers are disposed between the first and second electrodes to form a plurality of diodes between the cross points of the first and second electrodes. A passivation layer is disposed between the first electrodes and the diodes to form a plurality of anti-fuses adjacent to the diodes at the cross points of first and second electrodes. Portions of the diode layers are removed between the electrode cross points to form the plurality of memory cells with rows of trenches between adjacent memory cells to provide a barrier against crosstalk between adjacent memory cells. The trenches extend substantially to the depth of the n-doped layer in each diode.

Abstract: A memory circuit includes a cross-point memory array having first and second sets of transverse electrodes with respective memory elements formed at the crossing-points of the first and second set electrodes. Each of the memory elements is formed to include, in at least one of its binary states, a diode element. The memory circuit also includes an addressing circuit coupled to the memory array. The addressing circuit has a first set of address lines with first diode connections between the first set address lines and the first set memory array electrodes, with the first diode connections coupling each memory array electrode in the first set to a respective unique subset of the first set address lines.

Abstract: A memory circuit includes a cross-point memory array having first and second sets of transverse electrodes with respective memory elements formed at the crossing-points of the first and second set electrodes. Each of the memory elements is formed to include, in at least one of its binary states, a diode element. The memory circuit also includes an addressing circuit coupled to the memory array. The addressing circuit has a first set of address lines with first diode connections between the first set address lines and the first set memory array electrodes, with the first diode connections coupling each memory array electrode in the first set to a respective unique subset of the first set address lines.

Abstract: A memory circuit is provided which is capable of writing data with a simplified configuration and hence being improved in usability. The present invention comprises a fuse 10 having one end to which a bias voltage Vcc is to be applied from an internal power supply to have a disconnect/connect state storing data 0/1, a thyristor 11 having an anode terminal connected to the internal power supply through the fuse 10 and a cathode terminal being ground, an N-channel MOS transistor 12 having a drain terminal connected to a gate terminal of the thyristor 11 and a source terminal being ground, and a read-out circuit 14 for reading out data 0/1 stored on the fuse 10 through the N-channel MOS transistor 13.

Abstract: Diodes are connected between a clamp control line and respective one of data lines. A voltage of the clamp control line in a read operation is set to a value higher, by a forward voltage of the diodes or less, than a lower value among the voltages of the data line to which a selected digit line is connected. The voltages of the data lines to which only non-selected digit lines are connected are clamped to a predetermined value.

Abstract: A casing includes an elongated opening, an alarm device having a buzzer, a battery unit and a circuit unit to connect the battery unit to the buzzer, a time setting wheel and a conductive plate which has a first end connected to a first terminal of the battery unit, a second end abutting with the time setting wheel, a third end connected to a first contact point of the circuit board, and a fourth end above a second contact point of the circuit unit. The alarm device is actuated by a switch button assembly that includes a lever, which is made of a resilient, insulative material, pivotally mounted in the elongated opening and having a first end and a second end transversely passing the elongated opening to extend out of the casing.

Abstract: A self-identifying scheme which permits a variety of integrated circuit semiconductor memory modules to inform a host processor as to each individual memory accessing speed or accessing time. Pre-encoded circuits within each memory module generate a coded signal when that module is selected by the host processor. The coded signal identifies the type of memory accessed, permitting the host processor to transfer information at a rate determined by the memory accessed.

Abstract: A semiconductor memory circuit comprises memory cells, word lines, digit line pairs, load elements, a data bus line pair and a sense amplifier. The load elements are diode type semiconductor elements, and the information of the memory cell is read by using potential difference in forward voltages of the elements.

Abstract: A current bypass for a microelectric memory, such as a static RAM, diverts word line discharge current such that the current does not flow through the memory cells of a selected word line or along an upper word line conductor. In a first embodiment, the bypass comprises a resistor R1 (R2) and a diode D10 (D20) in series and coupled between an upper word line conductor 50 and word line discharge current source V.sub.CC, and a lower word line conductor 51 and word line discharge current sink 42. In another embodiment of the invention, a transistor Q10 (Q20) is used in lieu of the diode. By bypassing current from the upper word line conductor and word line memory cells, metal migration is eliminated and narrower metal lines may be used to form the word lines. By eliminating a flow of steady state discharge current through the memory cells, memory cell current saturation is eliminated.

Abstract: Organizations are disclosed for driving bit lines of a two-line 21/2D coincident current magnetic core memory in which a bit line not used for reading a bit out of a core is placed physically in parallel with the bit line driven by half select current to approximate in the unused line the capacitive and inductive coupling of the driven line with the word drive line. That coupling produces in the unused line the same noise (crosstalk) produced in the driven bit line by the word drive pulse. The crosstalk signal in the unused line is subtracted from the signal in the driven bit line before amplification and detection. The unused line may be a separate dummy line, or simply another bit line not being used for the bit being read out. In the case of paired bit lines used for common mode rejection of the bit drive signal, a second pair of unused bit lines is arranged in parallel for crosstalk cancellation.

Abstract: The complexity of a memory driver system is decreased by minimizing the number of half-select current driver circuits and corresponding terminals and wires connected between the driver lines and the core stack. This is effected by maximizing the number of current paths between memory drivers.