Crossover Patents (Class 365/69)
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Patent number: 12182537Abstract: A circuit for transposing a matrix comprising reversal circuitry configured, for each of one or more diagonals of the matrix, to receive elements of the matrix in a first vector and generate a second vector that includes the elements of the matrix in an order that is a reverse of an order of the elements of the matrix in the first vector, and rotation circuitry configured, for each of the one or more diagonals of the matrix, to determine a number of positions by which to rotate the elements of the matrix in the second vector, receive the second vector of elements of the matrix, and generate a third vector that includes the elements of the matrix in the second vector in an order that is a rotation of the elements of the matrix in the second vector by the determined number of positions.Type: GrantFiled: February 12, 2021Date of Patent: December 31, 2024Assignee: Google LLCInventors: Jonathan Ross, Robert David Nuckolls, Christopher Aaron Clark, Chester Li, Gregory Michael Thorson
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Patent number: 12183424Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.Type: GrantFiled: September 27, 2022Date of Patent: December 31, 2024Assignee: STMicroelectronics International N.V.Inventors: Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj Ayodhyawasi
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Patent number: 11961579Abstract: Bit line noise suppression and related apparatuses, methods, and computing systems are disclosed. An apparatus includes a complementary metal-oxide-semiconductor (CMOS) wafer and a memory cell wafer. The CMOS wafer includes CMOS wafer contact pads and sense amplifier circuitry electrically connected to some of the CMOS wafer contact pads. The memory cell wafer includes memory cell wafer contact pads and bit lines electrically connected to some of the memory cell wafer contact pads. The bit lines include primary bit lines and secondary bit lines. Each of the secondary bit lines extends in parallel proximate to a corresponding one of the primary bit lines. A cross intersection of a first primary bit line with a first secondary bit line located proximate to a parity intersection of a second primary bit line with a second secondary bit line. The first primary bit line is adjacent to the second primary bit line.Type: GrantFiled: May 18, 2022Date of Patent: April 16, 2024Assignee: Micron Technology, Inc.Inventor: Mitsunari Sukekawa
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Patent number: 11810627Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.Type: GrantFiled: August 12, 2022Date of Patent: November 7, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Harish R. Singidi, Renato C. Padilla, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Sampath K. Ratnam
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Patent number: 11568925Abstract: A memory device is disclosed. The memory device includes a memory array including a first memory cell arranged in a first row and a first column and a second memory cell arranged in the first row and a second column next to the first column. The first memory cell is configured to perform a write operation in response to a first write signal transmitted through a first write word line. The second memory cell is configured to perform the write operation in response to a second write signal transmitted through a second write word line. The second write word line is separated from and next to the first write word line. The first write signal and the second write signal have different logic values.Type: GrantFiled: October 30, 2020Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Sanjeev Kumar Jain
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Patent number: 10483281Abstract: A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.Type: GrantFiled: November 13, 2018Date of Patent: November 19, 2019Assignee: SK hynix Inc.Inventors: Yung Jun Kim, Suk Goo Kim
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Patent number: 9047954Abstract: Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells.Type: GrantFiled: April 19, 2014Date of Patent: June 2, 2015Assignee: SANDISK TECHNOLOGIES INC.Inventors: Teruhiko Kamei, Seungpil Lee, Siu Lung Chan, Kwang Ho Kim, Man Lung Mui
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Patent number: 8987909Abstract: According to one embodiment, a lower wiring layer is formed by using a sidewall transfer process for forming a sidewall film having a closed loop along a sidewall of a sacrificed or dummy pattern and, after removing the sacrificed pattern to leave the sidewall film, selectively removing the base material with the sidewall film as a mask. One or more upper wiring layers are formed in an upper layer of the lower wiring layer via another layer using the sidewall transfer process. Etching for cutting each of the lower wiring layer and the upper wiring layers is collectively performed, whereby closed-loop cut is applied to the lower wiring layer and the upper wiring layers.Type: GrantFiled: August 20, 2013Date of Patent: March 24, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Hiroyuki Nansei
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Patent number: 8964453Abstract: Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.Type: GrantFiled: June 27, 2013Date of Patent: February 24, 2015Assignee: Synopsys, Inc.Inventors: Xi-Wei Lin, Victor Moroz
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Patent number: 8891279Abstract: A mechanism is provided in a data processing system for enhancing wiring structure for a cache supporting an auxiliary data output. The mechanism splits the data cache into a first data portion and a second data portion. The first data portion provides a first set of data elements and the second data portion provides a second set of data elements. The mechanism connects a first data path to provide the first set of data elements to a primary output and connects a second data path to provide the second set of data elements to the primary output. The mechanism feeds the first data path back into the second data path and feeds the second data path back into the first data path. The mechanism connects a secondary output to the second data path.Type: GrantFiled: September 17, 2012Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Christian Habermann, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast
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Patent number: 8649217Abstract: According to one embodiment, a memory cell section includes a memory layer in which a non-volatile memory cell is arranged at an intersecting position of a first wiring and a second wiring to be sandwiched by the first wiring and the second wiring. A first drawing section connects the memory cell section and a first contact section with the first wiring, and a second drawing section connects the memory cell section and a second contact section with the second wiring. A dummy pattern is provided in a layer corresponding to the memory layer immediately below the first and second wirings configuring the first and second drawing sections.Type: GrantFiled: March 13, 2012Date of Patent: February 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takuji Kuniya, Katsunori Yahashi
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Publication number: 20130343113Abstract: A semiconductor device in which noise is reduced without an increase in chip area. The device is used as an MRAM in which a memory mat is formed on a silicon substrate surface and the central area of the memory mat is used as a memory array and the area around the memory array is used as a dummy memory array. In the dummy memory array, a capacitor is formed between each bit line, each digit line and a supply voltage line, and a grounding voltage line. Therefore the peak value of a current flowing in each of the bit lines, digit lines and supply voltage line is decreased.Type: ApplicationFiled: June 7, 2013Publication date: December 26, 2013Inventors: Ryoji MATSUDA, Motoi ASHIDA, Yasumitsu MURAI
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Patent number: 8542515Abstract: A multi-plane circuit structure has at least a first circuit plane and a second circuit plane, and each circuit plane has a plurality of row wire segments, a plurality of column wire segments, and a plurality of crosspoint devices formed at intersections of the row wire segments and the column wire segments. The row and column wire segments have a segment length for forming a preselected number of crosspoint devices thereon. Each row wire segment in the second circuit plane is connected to a row wire segment in the first circuit plane with no offset in a row direction and in a column direction, and each column wire segment in the second circuit plane is connected to a column wire segment in the first circuit plane with an offset length in both the row direction and the column direction. The offset length corresponds to half of the preselected number of crosspoint devices.Type: GrantFiled: April 30, 2010Date of Patent: September 24, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventor: Frederick Perner
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Patent number: 8467219Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.Type: GrantFiled: May 29, 2012Date of Patent: June 18, 2013Assignee: Macronix International Co., Ltd.Inventor: Hang-Ting Lue
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Patent number: 8411479Abstract: A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array.Type: GrantFiled: July 13, 2010Date of Patent: April 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng Hung Lee, Jui-Che Tsai, Ching-Wei Wu, Kuang Ting Chen
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Patent number: 8279403Abstract: An exposure apparatus has a first board on which a light-emitting element is mounted and a second board on which is mounted a driving IC for causing the light-emitting element to emit light. A second current path is extended from the driving IC, which is mounted on the second board, to the first board. The second current path is arranged so as to be adjacent to a first current path.Type: GrantFiled: September 9, 2009Date of Patent: October 2, 2012Assignee: Canon Kabushiki KaishaInventor: Ryo Mikami
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Patent number: 8248833Abstract: An anti-fuse memory device includes a plurality of word lines, a plurality of bit lines, and a memory cell provided with respect to an intersecting portion of any of the plurality of word lines and any of the plurality of bit lines. Memory cell includes a PIN diode and an anti-fuse. An anode of the PIN diode is electrically connected to any of the bit lines. A cathode of the PIN diode is electrically connected to a first terminal of the anti-fuse. A second terminal of the anti-fuse is electrically connected to any of the word lines. The anti-fuse includes a silicon layer and an insulating layer which are interposed between electrodes.Type: GrantFiled: September 2, 2009Date of Patent: August 21, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Jun Koyama, Atsushi Miyaguchi
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Patent number: 8023307Abstract: A method for handling peripheral signals in an extensible three dimensional circuit includes forming an extensible three dimensional circuit with a plurality of stacked crossbar arrays and at least one class of traveling lines which travel vertically and laterally through the circuit. The method also includes alternating the traveling direction of bundles of traveling lines such that there are a substantially equal number of undriven lines and underutilized lines which exit out of a given side of the circuit and creating loopback traces which connect the undriven traveling lines and the underutilized traveling lines to form driven traveling lines with a full complement of memory elements and eliminate addressing gaps within the circuit.Type: GrantFiled: April 30, 2010Date of Patent: September 20, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Richard J. Carter, Frederic Amerson
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Patent number: 7923812Abstract: A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the at least three resistivity switching storage elements.Type: GrantFiled: December 19, 2008Date of Patent: April 12, 2011Assignee: SanDisk 3D LLCInventor: Roy E. Scheuerlein
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Patent number: 7835208Abstract: A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that are cross-coupled between the main bit pair and the sub-bit pair, respectively; and first and second correction capacitors that are connected in parallel to the first and second coupling capacitors, respectively, and whose capacitance is adjusted by a control voltage signal.Type: GrantFiled: February 2, 2009Date of Patent: November 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Ki-whan Song
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Patent number: 7804700Abstract: A semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at the intersections of the plurality of word lines and the plurality of bit lines and each of that includes a MIS transistor and a memory element, a decoder circuit for selecting a plurality of word lines, and a sense-amplifier circuit for determining information that is read from any of the plurality of memory cells to any of the plurality of bit lines, wherein a twist connector for switching the wiring order of the plurality of word lines is provided and level-stabilizing circuits, for supplying the potential level of a non-selected state to the plurality of word lines in the non-selected state are arranged in the area below the twist connector.Type: GrantFiled: December 23, 2008Date of Patent: September 28, 2010Assignee: Elpida Memory, Inc.Inventors: Yasutoshi Yamada, Tomonori Sekiguchi, Riichiro Takemura, Kazuhiko Kajigaya
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Patent number: 7761753Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.Type: GrantFiled: June 9, 2008Date of Patent: July 20, 2010Assignee: Intel CorporationInventors: Pete D. Vogt, Dennis W. Brzezinski, Warren R. Morrow
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Patent number: 7613025Abstract: The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6 F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines on a 3 F-pitch arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.Type: GrantFiled: January 30, 2008Date of Patent: November 3, 2009Assignee: Micron Technology, Inc.Inventors: Fei Wang, Anton P. Eppich
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Patent number: 7505302Abstract: A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that are cross-coupled between the main bit pair and the sub-bit pair, respectively; and first and second correction capacitors that are connected in parallel to the first and second coupling capacitors, respectively, and whose capacitance is adjusted by a control voltage signal.Type: GrantFiled: December 13, 2006Date of Patent: March 17, 2009Assignee: Samsung Electric Co., LtdInventor: Ki-whan Song
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Patent number: 7414913Abstract: A multiport memory in one embodiment of the invention includes a memory cell array, where each column in the array has two exterior complementary bitline pairs and zero, one, or more interior complementary bitline pairs. Across each pair of adjacent columns in the array, the adjacent exterior bitline pairs are associated with the same port in the multiport memory. In addition, within each column, the two exterior bitline pairs have the same, non-zero number of crossovers, and, across each pair of adjacent columns, the exterior bitline pairs have different numbers of crossovers. Furthermore, each column has at least one reference signal line located between the two exterior bitline pairs.Type: GrantFiled: August 1, 2005Date of Patent: August 19, 2008Assignee: Lattice Semiconductor CorporationInventors: Larry Fenstermaker, Harold N. Scholz, Gregory Cartney, Allen White, Margaret Tait, Hemanshu T. Vernenker
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Patent number: 7349232Abstract: The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines on a 3F-pitch arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.Type: GrantFiled: March 15, 2006Date of Patent: March 25, 2008Assignee: Micron Technology, Inc.Inventors: Fei Wang, Anton P. Eppich
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Patent number: 7310256Abstract: A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.Type: GrantFiled: May 23, 2005Date of Patent: December 18, 2007Assignees: Hitachi, Ltd., Elpida Memory, Inc.Inventors: Riichiro Takemura, Satoru Akiyama, Satoru Hanzawa, Tomonori Sekiguchi, Kazuhiko Kajigaya
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Patent number: 7277309Abstract: A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell (102, 104) can include a pair of memory areas to store data (106-0/106-1, 106-2/106-3), and a logic portion (108-0, 108-1) that receives the data stored therein. Memory areas and the logic portions of each memory/logic cell can be arranged on the substrate in a shape of an L, U, S, T, or Z to form a pair of interlocking memory/logic cells.Type: GrantFiled: October 23, 2006Date of Patent: October 2, 2007Assignee: NetLogic Microsystems, Inc.Inventors: Bartosz Banachowicz, Andrew Wright
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Patent number: 7257011Abstract: A semiconductor memory according to an example of the present invention comprises first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns, a first cell block which is disposed in the first column, a first block select transistor which is connected between the first or second bit line and one end of the first cell block, a second cell block which is disposed in the second column, and a second block select transistor which is connected between the second or first bit line and one end of the second cell block.Type: GrantFiled: October 27, 2005Date of Patent: August 14, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi Miyakawa, Daisaburo Takashima
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Patent number: 7242602Abstract: A semiconductor memory device includes spaced apart twisted bit line pairs, a respective one of which includes a spaced apart twisted area. A conductive line overlaps the respective twisted areas of the spaced apart twisted line pairs. The conductive line can extend parallel to the memory device word lines, and can provide a power supply ground and/or signal line.Type: GrantFiled: December 2, 2004Date of Patent: July 10, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Ho Lee, Jong-Hyun Choi
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Patent number: 7221577Abstract: The present invention relates to a system and method for equalizing the capacitance between/among n lines of a bus running in parallel for a portion of their length. The system and method include determining a twisting pattern for the n lines using an algorithm for example. After determining the twisting pattern forming at least n?1 twisted sections, the n lines are twisted according to the pattern so that each of the n lines runs along every other line for a same distance across the length of a bus.Type: GrantFiled: May 24, 2004Date of Patent: May 22, 2007Assignee: Broadcom CorporationInventors: Gil I. Winograd, Bibhudatta Sahoo, Esin Terzioglu
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Patent number: 7200059Abstract: A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.Type: GrantFiled: October 28, 2005Date of Patent: April 3, 2007Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Yoshiaki Okuyama, Yasuhiro Takada, Tatsuhiro Watanabe, Nobumi Kodama
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Patent number: 7154793Abstract: An integrated memory includes memory cells arranged in a memory cell array along word lines and bit lines. One of the bit lines can be connected to a data line by a respective one of a plurality of switches. The memory contains column select lines. One of the column select lines in each case connected to a plurality of the switches for driving, in an activated state, in order to connect a number of bit lines to a same number of data lines. An access controller is connected to the column select lines and can be operated in a test operating mode such that a plurality of the column select lines are activated in the event of a memory cell access. The writing of test data to the memory cell array in a test operating mode can thus be optimized in accordance with the invention.Type: GrantFiled: September 24, 2004Date of Patent: December 26, 2006Assignee: Infineon Technologies AGInventors: Michael Bernhard Sommer, Fabien Funfrock
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Patent number: 7139993Abstract: One embodiment of the present invention provides an arrangement of differential pairs of wires that carry differential signals across a semiconductor chip. In this arrangement, differential pairs of wires are organized within a set of parallel tracks on the semiconductor chip. Furthermore, differential pairs of wires are organized to be non-adjacent within the tracks. This means that each true wire is separated from its corresponding complement wire by at least one intervening wire in the set of parallel tracks, thereby reducing coupling capacitance between corresponding true and complement wires. Moreover, this arrangement may include one or more twisting structures, wherein a twisting structure twists a differential pair of wires so that the corresponding true and complement wires are interchanged within the set of parallel tracks.Type: GrantFiled: March 26, 2004Date of Patent: November 21, 2006Assignee: Sun Microsystems, Inc.Inventors: Robert J. Proebsting, Ronald Ho, Robert J. Drost
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Patent number: 7106639Abstract: A defect management enabled PIRM including a data storage medium providing a plurality of cross point data storage arrays. Each array provides a plurality of memory cells. The arrays are allocated into separate super arrays, the separate super arrays virtually aligned as sets. A controller is also provided, capable of establishing the selection of a virtually aligned set of arrays and a virtually aligned set of memory cells. The controller is operable during a write operation to receive a word of data bits and detect a defective array in the selected virtually aligned set of memory arrays. The controller is further capable of directing the allocation of at least one data bit from the defective memory array to a spare memory array.Type: GrantFiled: September 1, 2004Date of Patent: September 12, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Carl P. Taussig, Richard E. Elder
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Patent number: 7079410Abstract: A ferroelectric memory cell array and a device for driving the same are disclosed, in which the ferroelectric memory cell array is defined as first and second cell regions each using at least one group of four split wordlines to reduce a layout area of the memory cell array and/or a RC load when a split wordline is used as a plate line. In the first cell region, the first and third split wordlines are used as wordlines, and the second and fourth split wordlines are used as plate lines. In the second cell region, the second and fourth split wordlines are used as wordlines and the first and third split wordlines are used as plate lines.Type: GrantFiled: January 25, 2005Date of Patent: July 18, 2006Assignee: Hynix Semiconductor Inc.Inventor: Hee-Bok Kang
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Patent number: 7075807Abstract: A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.Type: GrantFiled: August 18, 2004Date of Patent: July 11, 2006Assignees: Infineon Technologies AG, Altis SemiconductorInventors: Rainer Leuschner, Daniel Braun, Gill Yong Lee, Ulrich Klostermann
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Patent number: 7020012Abstract: Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines being uniquely defined. Additionally, an unselect voltage is applied to the unselected conductive array lines. The unselect voltage can be applied before, after or during the selection process. The unselect voltage can be approximately equal to the average of the first select voltage and the second select voltage.Type: GrantFiled: December 13, 2004Date of Patent: March 28, 2006Inventors: Darrell Rinerson, Steven W. Longcor, Christophe J. Chevallier, Edmond R. Ward
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Patent number: 6999336Abstract: A memory cell array includes ferroelectric memory cells arranged in m rows and n columns, bit lines provided along a row direction, and word lines and plate line provided along a column direction. The word lines are provided side by side so as to intersect each other at the border between the fourth row and fifth row. The arrangement allows the connecting of four ferroelectric memory cells to the same plate line and the same word line. Since the number of ferroelectric memory cells to be accessed simultaneously will be one-half the number of memory cells provided in one row, unnecessary access to the ferroelectric memory cells is reduced, to suppress deterioration of the ferroelectric memory cells. The word lines may instead intersect each other between the second and third lines, so that two ferroelectric memory cells are connected to the same plate and word lines.Type: GrantFiled: October 27, 2004Date of Patent: February 14, 2006Assignee: Oki Electric Industry Co., Ltd.Inventor: Shinzo Sakuma
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Patent number: 6909663Abstract: Memory cell arrays are defined by rows and columns of memory cells that are addressed by sets of bitlines associated with a first memory port and a second memory port. The bitlines associated with the first memory port have bitline exchanges associated with a first set of memory cell rows and the bitlines associated with the second memory port have bitline exchanges associated with a second set of memory cell rows. The memory cells can have the same design, and all memory cell columns can have the same design. Read/write logic for the arrays can be based on memory cell row addresses.Type: GrantFiled: September 26, 2003Date of Patent: June 21, 2005Assignee: Lattice Semiconductor CorporationInventors: Hemanshu T. Vernenker, Allen White, Marge Tait
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Patent number: 6894231Abstract: The present invention relates to a system and method for equalizing the capacitance between at least two lines of a bus running in parallel for a portion of their length. The system and method include determining a twisting pattern for the lines using an algorithm. After determining the twisting pattern, the lines are twisted according to the pattern so that each of the lines runs along every other line for a same distance across the length of the bus.Type: GrantFiled: March 19, 2002Date of Patent: May 17, 2005Assignee: Broadcom CorporationInventors: Gil I. Winograd, Bibhudatta Sahoo, Esin Terzioglu
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Patent number: 6873537Abstract: A ferroelectric memory cell array and a device for driving the same are disclosed, in which the ferroelectric memory cell array is defined as first and second cell regions each using at least one group of four split wordlines to reduce a layout area of the memory cell array and/or a RC load when a split wordline is used as a plate line. In the first cell region, the first and third split wordlines are used as wordlines, and the second and fourth split wordlines are used as plate lines. In the second cell region, the second and fourth split wordlines are used as wordlines and the first and third split wordlines are used as plate lines.Type: GrantFiled: November 5, 2002Date of Patent: March 29, 2005Assignee: Hynix Semiconductor Inc.Inventor: Hee-Bok Kang
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Patent number: 6870754Abstract: A memory cell array includes ferroelectric memory cells arranged in the form of m rows and n columns, bit lines provided along a row direction, and word lines and plate lines provided along a column direction. The word lines are provided side by side so as to intersect each other at the border between the fourth row and the fifth row. The arrangement allows the connecting of four ferroelectric memory cells to the same plate line and the same word line. Since the number of ferroelectric memory cells to be accessed simultaneously will be one-half of the number of memory cells provided in one row, unnecessary access to the ferroelectric memory cells can be reduced, thereby deterioration of the ferroelectric memory cells can be suppressed.Type: GrantFiled: April 3, 2003Date of Patent: March 22, 2005Assignee: Oki Electric Industry Co., Ltd.Inventor: Shinzo Sakuma
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Patent number: 6862204Abstract: A plurality of memory cell arrays includes bit lines and memory cells each constituted by a variable capacitor, and operates at mutually different timings. The bit lines of each memory cell array are connected to bit lines of the other memory cell arrays via connecting wires. Accordingly, the actual capacitances of the bit lines are the capacitances of bit lines of that memory cell array itself plus that of the other memory cell arrays plus the capacitances of the connecting wires. Therefore, when data is read from the memory cells, the variations in voltage of the bit lines caused by the capacitive division can be enlarged. Consequently, the read margin can be prevented from being degraded, and the manufacturing yield of semiconductor memories can be prevented from being degraded. Additionally, since the variations in voltage of the bit lines are enlarged, the data reading time can be shortened.Type: GrantFiled: October 22, 2002Date of Patent: March 1, 2005Assignee: Fujitsu LimitedInventor: Noro Kouichi
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Patent number: 6862234Abstract: Method and system for testing a sense amplifier in a dynamic memory circuit. In one embodiment, the sense amplifier is connected to a first bit line pair via a first switching device and to a second bit line pair via a second switching device. First memory cells are arranged at crossover points between first word lines and one of the bit lines of the first bit line pair, and second memory cells are arranged at crossover points between second word lines and one of the bit lines of the second bit line pair. Data are written to the first and the second memory cells and subsequently read out. During the read-out of one of the first memory cells, the relevant first word line is activated and the first switching device is activated while the second switching device is closed, and during the read-out of one of the second memory cells, the relevant second word line is activated and the second switching device is activated while the first switching device being closed.Type: GrantFiled: March 11, 2004Date of Patent: March 1, 2005Assignee: Infineon Technologies AGInventors: Martin Versen, Peter Beer, Lee Nino
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Patent number: 6845028Abstract: When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ).Type: GrantFiled: October 2, 2003Date of Patent: January 18, 2005Assignee: Hitachi, Ltd.Inventor: Riichiro Takemura
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Patent number: 6839266Abstract: A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.Type: GrantFiled: March 20, 2002Date of Patent: January 4, 2005Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Frederick Abbott Ware, Craig E. Hampel, Richard M. Barth, Don Stark, Abhijit Mukund Abhyankar, Catherine Yuhjung Chen, Thomas J. Sheffler, Ely K. Tsern, Steven Cameron Woo
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Patent number: 6831854Abstract: Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines uniquely defining a single memory plug. The magnitude of the select voltages depends upon whether a read operation or a write operation is occurring. Additionally, an unselect voltage is applied to the unselected conductive array lines. The unselect voltage can be applied before, after or during the selection process. The unselect voltage is approximately equal to the average of the first select voltage and the second select voltage.Type: GrantFiled: December 26, 2002Date of Patent: December 14, 2004Assignee: Unity Semiconductor CorporationInventors: Darrell Rinerson, Steven W. Longcor, Christophe J. Chevallier, Edmond R. Ward, Wayne Kinney, Steve Kuo-Ren Hsia
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Patent number: 6826075Abstract: A memory matrix has at least one cell array including column lines and row lines. Memory elements are situated at points where the row lines and column lines intersect one another. In each case two adjacent lines are guided such that they cross one another in such a way that the two lines change their spatial configurations in sections along the direction in which they run. Thus an overcoupling of signals between the lines is minimized.Type: GrantFiled: July 13, 2001Date of Patent: November 30, 2004Assignee: Infineon Technologies AGInventors: Dietmar Gogl, Thomas Röhr, Heinz Hönigschmid
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Publication number: 20040125636Abstract: A high-density folded bitline memory array architecture is disclosed. High memory cell packing density is achieved by dividing polysilicon wordlines into short individual segments in the folded bitline scheme. Each wordline segment forms the gate of one or two DRAM memory cell transistors, and each segment is connected to a metal wordline, or conductor having low resistivity. By eliminating spaces between the memory cells due to passing wordlines, a cell arrangement and density similar to open bitline schemes is achieved. Further packing is obtained by arranging two columns of memory cells parallel to each bitline, each column offset with the other by a predetermined pitch. Therefore, by increasing the number of memory cells connected to each complementary bitline pair, each bitline pair can be cut in half and connected to its own bitline sense amplifier to reduce the bitline capacitance.Type: ApplicationFiled: December 18, 2003Publication date: July 1, 2004Inventors: Wlodek Kurjanowicz, David Chi Wing Kwok