Abstract: A novel semiconductor memory having a plurality of storage devices arranged in and X-Y array wherein the Input and Output data lines of the array are routed over a portion of the memory array. The Input and Output data lines are routed symmetrically between and in parallel with the small-signal bit-line pairs of the array which access the individual storage devices. The individual bit-lines of a bit-line pair cross-over one another at the midpoint of the portion of the array over which the Input and Output lines am routed. Buffers are included on the Input and Output lines at the periphery of the array in order to prevent noise external to the array from being transmitted into the array on the I/O data lines above the array. Output buffers are also provided to drive output data out across the array. Additionally, circuitry is provided for preventing the Input and Output lines from transitioning while small-signals are being developed on the bit-line pairs.

Abstract: An integrated circuit bus for the transmission of a serial data signal, to be used in integrated circuits, wherein the data is clocked only to one addressed register, and thus cross-talk is reduced. In the bus all information signals are contained in one signal. The data transmission is based on pulses of different lengths corresponding to different states.

Abstract: A system is described for arraying multi-device processing nodes in a 3-dimensional computing architecture and for flexibly connecting their ports. The topology of each processing node is of a fixed and constant physical geometry. The nodes may comprise a digital signal processor chip, a static RAM, and a communications and network controller. The nodes are mounted on boards. Selective connection of ports of each board to ports of another adjacent board is effected by a routing and spacer element having internal routing paths.

Abstract: A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

Abstract: A dual-port memory device provides bit lines having a crossover pattern to reduce stray end coupling capacitances. Such crossover occurs approximately in the middle of the memory array for the device. Data in one-half of the array is stored in an inverted manner from data in the other half of the array. A preferred technique for clearing a memory provides for resetting only a portion of the bits of the array for each entry, with the bits of all memory entries being reset simultaneously. In order to provide such a reset function with the preferred bit line crossover scheme, a voltage node used for reset must also provide signal lines which are crossed over in the middle of the array.

Abstract: A dynamic-type semiconductor memory device comprises bit lines, every two bit lines forming a folded bit line pair, every two pairs forming a bit-line unit such that one of the bit lines of the first pair extends between the bit lines of the second pair, and the bit lines of the second pair are twisted at middle portion, word lines intersecting with the bit lines, dummy word lines, extending parallel to the word lines, two of the dummy word lines being arranged on one side of the crossing portions of the bit lines of the second pair, and the other two of the dummy word lines being arranged on the other side of the crossing portions of the bit lines of the second pair, memory cells connected to selected ones of the intersections of the bit lines and the word lines, such that any adjacent memory cells connected to the same word line form a group which is arranged every two bit lines, and any adjacent two memory cells connected to the same bit line are shifted by half-pitch distance with respect to the correspon

Abstract: A semiconductor device such as a memory device has many sets of complementary data lines disposed parallel to one another. Mutually complementary lines are crossed with respect to each other nearly at the center such that their inter-line capacitances with a neighboring line are nearly equal. Crosstalks between either of the complementary word lines and such a neighboring line can be thereby reduced.

Abstract: A criss-crossed complementary bit line and cross-coupled pull-up means is disclosed. One bit line (26) is crossed with respect to another bit line (28) of a complementary bit line pair to reduce the effect of noise interference induced therein. P-channel cross-coupled pull-up transistors (154, 156) are connected between the bit lines (26, 28) at an intersection (148) to assure that when one bit line is pulled low by the readout of a memory cell (158), the other bit line is pulled to the supply voltage.

Abstract: A device for the determination of the dynamic characteristics of a magnetic recording and reproducing head utilizes a support for the head to be analyzed and a standard head which are juxtaposed with common carrier and are controlled by a microcomputer through interface and shift register circuitry to automatically print out the saturation and response characteristics of the analyzed head. If a defect is determined, the standard head is activated so that the system can automatically detect whether the defect is an artifact of the recording medium or is a defect in the analyzed head.

Abstract: An impedance is connected by a switching circuit, to sense/inhibit windings of a core memory at the end of each memory cycle. The result is an effectively decreased time constant for the core windings which permits faster memory operation. The circuit further reverse biases diodes connected to the input terminals of a sense amplifier during a read cycle thereby increasing the isolation of this amplifier from the effects of inhibit current pulses occurring during a memory read cycle.

Abstract: A large, 2 wire, 2-1/2D core memory includes four, 1K (1024) by 1280, core frames with 1280 Y conductors each stringing and inductively coupling a column of 1024 cores in each of the four frames and 4K orthogonal X conductors each stringing and inductively coupling one row of 1280 cores. A word position within the memory is defined by 5 pairs of Y conductors, a corresponding X conductor from each frame, and selection of relative current directions in the Y conductors. Reading of a 20 bit word is accomplished with 5 sense amplifiers in four rapid succession read sub-operations. Digit sense conductor noise recovery time is minimized by arranging for balanced, predictable delta noise on each digit sense conductor of a pair and by providing a multiple digit sense conductor pair crossover arrangement which results in a balancing of image current coupling into adjacent digit sense conductor pairs.

Abstract: A large bit size core memory which maximizes usable flux includes at least one array of low drive toroidal magnetic memory cores, a sense-inhibit conductor pair passing through the array in a given direction to inductively couple all cores in the array, a plurality of perpendicular drive conductors, each passing through the array perpendicular to the sense-inhibit conductor pair and inductively coupling a portion of the cores in the array, a plurality of parallel drive conductors, each passing through the array parallel to the sense-inhibit conductor pair and inductively coupling a portion of the cores in the array, and driving and switching circuitry coupled to drive selected a core during a read portion of a memory cycle with a current which rapidly increases to approximately provide the coercive force MMF to the core and then increases relatively slowly toward the full drive current.