Abstract: Word-line drivers, memories, and methods of operating word-line drivers are provided. A word-line driver coupled to an array of memory cells includes a decoder powered by a first power supply. The decoder is configured to decode an address to provide a plurality of word-line signals. The word-line driver also includes a plurality of output stages powered by a second power supply that is different than the first power supply. Each of the output stages includes a first transistor having a gate controlled by a first control signal and an inverter. The inverter is coupled between the first transistor and a ground and has an input coupled to the decoder to receive one of the word-line signals. The word-line driver also includes pull-down circuitry coupled between the gates of the first transistors and the ground and activated by a second control signal.

Abstract: A non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A MOS (“metal-oxide-semiconductor”) transistor in addition to a capacitor or transistor acting as a capacitor can also be included. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. A floating gate of an NMOS transistor can be connected to the other side of the selector device, and a second NMOS transistor can be connected in series with the first NMOS transistor.

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a plurality of sensing components coupled to a controller. The controller is configured to selectively activate a first control line and a second control line to invert signals stored on a latch.

Abstract: The present disclosure relates to a thin film transistor, a method for fabricating the same, an array substrate, a method for fabricating the same, and a display device. The thin film transistor includes an active layer disposed on a base substrate and a gate stack disposed on the active layer. The gate stack includes: a gate insulating layer disposed on the active layer; a gate electrode disposed on the gate insulating layer; a capping layer disposed on the gate electrode, wherein the capping layer capturing oxygen atoms more easily than the gate electrode.

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j-1th sub memory cell.

Abstract: A circuit includes a current mirror circuit (CM circuit) including first and second transistors, a third transistor whose drain is electrically connected to a drain of the second transistor, a switch controlling the current output from the circuit, and first and second memory circuits. A reference current of the CM circuit is input to a drain of the first transistor; a current that is a copy of the reference current is output from the drain of the second transistor. When a current is output from the circuit, the reference current is not input to the CM circuit. A drain current corresponding to a voltage stored in the first memory circuit flows through the second transistor; a drain current corresponding to a voltage stored in the second memory circuit flows through the third transistor. The difference between the two drain currents corresponds to the output current of the circuit.

Abstract: A memory device includes a page buffer unit including a plurality of latches latching each of a plurality of pieces of dummy data of selected memory cells according to a plurality of dummy signals provided by a word line of the selected memory cells, and a control logic comparing a count value of a first count latch among the plurality of latches with a reference count value, determining whether to count a second count latch other than the first count latch according to a result of the comparison, and correcting a level of a read signal provided by the word line of the selected memory cells in a read operation.

Abstract: A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.

Abstract: Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.

Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

Abstract: A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.

Abstract: Piezoelectric transistors with Schottky contacts and power conversion applications utilizing such piezoelectric transistors are disclosed. A piezoelectric transistor configured in accordance with the inventive concepts disclosed herein may be fabricated to behave as a controllable/switchable active device with an intrinsic anti-parallel diode. Piezoelectric transistors configured in this manner may be utilized in power amplifiers, power converters, as well as in a variety of electronic systems/applications.

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a plurality of sensing components coupled to a controller. The controller is configured to selectively activate a first control line and a second control line to invert signals stored on a latch.

Abstract: A metal oxide film includes indium, M, (M is Al, Ga, Y, or Sn), and zinc and includes a region where a peak having a diffraction intensity derived from a crystal structure is observed by X-ray diffraction in the direction perpendicular to the film surface. Moreover, a plurality of crystal parts is observed in a transmission electron microscope image in the direction perpendicular to the film surface. The proportion of a region other than the crystal parts is higher than or equal to 20% and lower than or equal to 60%.

Abstract: A semiconductor device including a memory which can perform a pipeline operation is provided. The semiconductor device includes a processor core, a bus, and a memory section. The memory section includes a first memory. The first memory includes a plurality of local arrays. The local array includes a sense amplifier array and a local cell array stacked thereover. The local cell array is provided a memory cell including one transistor and one capacitor. The transistor is preferably an oxide semiconductor transistor. The first memory is configured to generate a wait signal. The wait signal is generated when a request for writing data to the same local array is received over two successive clock cycles from the processor core. The wait signal is sent to the processor core via the bus. The processor core stands by for a request for the memory section on the basis of the wait signal.

Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of memory cells arranged in columns. The integrated circuit may include write assist circuitry having a column selector that accesses the memory cells via a bitline coupled to each of the columns. The write assist circuitry may include a first node that couples the column selector to a discharge circuit and a feedback circuit. The write assist circuitry may include a second node that couples a trigger circuit to the discharge circuit and the feedback circuit. The trigger circuit enables the discharge circuit, discharges the second node, and is disabled after discharging the second node. The discharge circuit discharges the first node, and the feedback circuit tracks the first node and disables the discharge circuit.

Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the

Abstract: A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal coupled to a boost capacitor. A ground for the first write driver inverter floats during a write assist period to choke off leakage of boost charge from the boost capacitor through the write driver transistor.

Abstract: To provide a small, highly reliable memory device with a large storage capacity. A semiconductor device includes a circuit for retaining data and a circuit for reading data. The circuit for retaining data includes a transistor and a capacitor. The circuit for reading data is configured to supply a potential to the circuit for retaining data and read a potential from the circuit for retaining data. The circuit for retaining data and the circuit for reading data are provided in different layers, so that the semiconductor device with a large storage capacity is manufactured.

Abstract: A transistor includes: a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.

Abstract: A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.

Abstract: Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.

Abstract: A semiconductor device excellent in writing operation is provided. In a structure where a data voltage supplied to a source line is supplied to a node of a memory cell via a bit line, a switch is provided between memory cells connected to the bit line. During a period in which the data voltage is supplied to the node of the memory cell, the switch on the bit line, which is provided between the memory cells, is off. With such a structure, parasitic capacitance of the bit line during a period in which the data voltage is supplied to the node of the memory cell can be reduced. As a result, writing of the data voltage into the memory cell can be performed fast.

Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells comprises: a gate structure on the substrate; a first interlayer dielectric (ILD) layer around the gate structure; a first contact plug in the first ILD layer; a second ILD layer on the first ILD layer; and a second contact plug in the second ILD layer and electrically connected to the first contact plug.

Abstract: A semiconductor device excellent in writing operation is provided. In a structure where a data voltage supplied to a source line is supplied to a node of a memory cell via a bit line, a switch is provided between memory cells connected to the bit line. During a period in which the data voltage is supplied to the node of the memory cell, the switch on the bit line, which is provided between the memory cells, is off. With such a structure, parasitic capacitance of the bit line during a period in which the data voltage is supplied to the node of the memory cell can be reduced. As a result, writing of the data voltage into the memory cell can be performed fast.

Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor substrate; and a memory cell array which is arranged above the semiconductor substrate in a first direction. The memory cell array includes: a semiconductor layer which extends in the first direction; a first conductive line which extends in a second direction crossing the first direction; a variable resistance film which is arranged at an intersection between the semiconductor layer and the first conductive line; a plurality of second conductive lines which are arranged in the second direction sandwiching the semiconductor layer and extend in the first direction; and a plurality of third conductive lines which are electrically connected to the second conductive lines. Two of the second conductive lines neighboring to each other in the second direction with the semiconductor layer interposed therebetween are electrically connected to different third conductive lines.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate and arranged to intersect the word lines, thereby delimiting a plurality of crossing regions and a plurality of unit memory cells; a plurality of gate electrodes formed to control respective pairs of unit memory cells adjacent to each other with the word lines interposed therebetween and to contact corresponding word lines on one sides of the crossing regions; storage node contacts respectively formed in spaces of the unit memory cells; and a plurality of bit line contacts formed to contact the respective bit lines on one sides of the crossing regions.

Abstract: A semiconductor device with a small cell area and excellent data read/write capability is achieved. In the semiconductor device, a wiring for writing data is provided, and a first transistor with a low off-state current is turned on to supply data to a gate of a second transistor and is turned off so that electric charge corresponding to data is retained. Moreover, a wiring for reading data is provided, and a third transistor is turned on so that data is read out in accordance with the on/off state of the second transistor retaining the electric charge. With this configuration, data write and data read are achieved in the same cycle.

Abstract: A plurality of word lines extend in a first direction and are disposed in a second direction and a third direction. A plurality of bit lines extend in the third direction and are disposed in the first direction and the second direction. A global bit line is coupled in common to the plurality of bit lines. A selection elements is disposed between the bit line and the global bit line. A control circuit is able to perform respective operations of reading, writing, and deletion on the storage element. A resistive element is disposed on the global bit line side with respect to the selection element. The resistive element adjusts a magnitude of a voltage to be applied to the selection element according to a magnitude of a current flowing through the selection element.

Abstract: A memory cell (1) includes a first storage circuit (2) with a write time t1 and a data retention time ?1 and a second storage circuit (3) with a write time t2 and a data retention time ?2 (t1<t2 and ?1<?2). A row decoder supplies write data to the memory cell (1) via a word line (WL) to write the data on the first storage circuit (2) over a write time tW that is longer than the write time t1 and that is shorter than the write time t2. A PL control circuit (4) supplies power to the memory cell (1) for a time that is longer than the write time t2 when the write data is supplied to the memory cell (1), writes, on the second storage circuit (3), the data written on the first storage circuit (2) once the supply of the write data is stopped, and stops the supply of the power to the memory cell (1) after a lapse of the write time t2 following start of the supply of the write data.

Abstract: A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.

Abstract: An integrated circuit including data and code non-volatile memory configuration is provided. The integrated circuit comprises a first non-volatile memory array for storing code and a second non-volatile memory array for storing data. The first non-volatile memory array comprises a plurality of first non-volatile memory cells, the first non-volatile memory cells each having a first channel width. The second non-volatile memory array comprises a plurality of second non-volatile memory cells, the second non-volatile memory cells each having a second channel width. The second channel width of the second non-volatile memory cells is larger than the first channel width of the first non-volatile memory cells. This allows the data non-volatile memory cells to have a higher transconductance than the code non-volatile memory cells.

Abstract: A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.

Abstract: Some embodiments relate to a system that pre-colors word lines and control lines within a memory cell to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The system has a memory element that stores a graphical IC layout with a memory circuit having layout features including a plurality of word lines and a plurality of Y-control lines. A pre-coloring element pre-colors one or more of the plurality of word lines and Y-control lines, to indicate that pre-colored word lines and Y-control lines are to be formed on a same mask of a multiple mask set used for a multiple patterning lithography process. A decomposition element assigns different colors to uncolored layout features of the memory circuit, to indicate that different colored memory features are to be formed on different masks of the multiple mask set.

Abstract: Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and second set of data lines. Other embodiments including additional apparatuses and methods are described.

Abstract: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.

Abstract: A memory cell includes a first transistor controlling writing of the first date by being in an on state, and holding of the first data by being in an off state, a second transistor in which a potential of one of a source and a drain is a potential of the second data and a potential of a gate is a potential of the first data, and a third transistor which has a conductivity type opposite to that of the second transistor, which has one of a source and a drain electrically connected to the other of the source and the drain of the second transistor, and in which a potential of a gate is a potential of the first data.

Abstract: A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.

Abstract: A circuit comprises a first memory cell, a second memory cell, and a disturb control circuit. The first memory cell has a first port and a second port. The first port is associated with a first write assist circuit. The second port is associated with a second write assist circuit. The second memory cell has a third port and a fourth port. The third port is associated with a third write assist circuit. The fourth port is associated with a fourth write assist circuit. The disturb control circuit is configured to selectively turn on at least one of the first write assist circuit, the second write assist circuit, the third write assist circuit, or the fourth write assist circuit according to whether the first port, the second port, the third port, or the fourth port is determined to be write disturbed.

Abstract: An SRAM device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a second segment of the memory cells and a write assist line interleaved with the first and second metallization layers to provide a substantially constant coupling capacitance with each of the first and second pairs of bitlines.

Abstract: A semiconductor memory device in which capacitance of a capacitor is lower and integration degree is higher. A plurality of memory blocks is connected to one bit line BL_m. A memory block MB_n_m includes a sub bit line SBL_n_m, a write switch, and a plurality of memory cells. A sub bit line SBL_n+1_m adjacent to the sub bit line SBL_n_m is connected to an amplifier circuit AMP_n/n+1_m including two inverters and two selection switches. A circuit configuration of the amplifier circuit can be changed with the selection switches. The amplifier circuit is connected to the bit line BL_m through a read switch. Because of a sufficiently low capacitance of the sub bit line SBL_n_m, potential change due to electric charges of the capacitor in each memory cell can be amplified by the amplifier circuit AMP_n/n+1_m without an error, and the amplified data can be output to the bit line BL_m.

Abstract: Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization layer includes first and second global bitlines. The first metallization layer includes local bitlines. In each of the first segments, local bitlines are connected to one of the first global bitlines. In each of the second segments, local bitlines are connected to one of the second global bitlines.

Abstract: An array includes a plurality of vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include an inner data/sense line elevationally inward of the access lines and which interconnect transistors in that column. An outer data/sense line is elevationally outward of the access lines and electrically couples to the inner data/sense line. Other embodiments are disclosed, including memory arrays and memory cells.

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Abstract: A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of said interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold.

Abstract: This semiconductor device is provided with: a variable resistance first switch (103), which has a first terminal and a second terminal, and which has the resistance value thereof varied when an applied voltage exceeds a reference value; a variable resistance second switch (104), which has a third terminal and a fourth terminal, and which forms an intermediate node (105) by having the third terminal connected to the second terminal, and has the resistance state thereof varied when an applied voltage exceeds a reference value; first wiring (101) connected to the first terminal; second wiring (102), which is connected to the fourth terminal, and which extends in the direction intersecting the first wiring (101) in a planar view; a first selection switch element (106) connected to the first wiring (101); and a second selection switch element (107) connected to the second wiring (102).

Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: The semiconductor memory device includes a cell transistor having a gate insulating film deposited on an inner surface of a groove formed in an upper surface of the semiconductor substrate, a gate electrode buried in the groove with the gate insulating film formed on the inner surface thereof, and a source region and a drain region formed on an upper surface of the active area of the semiconductor substrate on opposite sides of the gate electrode. The semiconductor memory device includes an MTJ element having a variable resistance that varies with a direction of magnetization that is provided on the source region and electrically connected to the source region at a first end thereof.

Abstract: A semiconductor memory device, including a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells coupled to the plurality of word lines and the plurality of pairs of bit lines, a plurality of sense amplifiers each coupled between a corresponding pair of bit lines, a plurality of first driver transistors coupled between the plurality of sense amplifiers and a first power supply line, a plurality of second driver transistors coupled between the plurality of sense amplifiers and a second power supply line, a pair of common data lines, and a plurality of column selection gates each coupled between the corresponding pair of bit lines and the pair of common data lines, wherein the number of the first driver transistors is more than the number of the second driver transistor.

Abstract: A high-voltage word-line driver circuit for a memory device uses cascode devices to prevent any single transistor of the driver circuit from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.