Abstract: Upon reception of data via a first communication device, a unit connects the first communication device with a storage unit to store the data to be transferred and, after completion of data reception, the unit switches connections of the storage unit to a second communication device and transmits the stored data to the second communication device.

Abstract: A system, apparatus, method and article for high definition audio modems are described. The apparatus may include a communications path comprising a communications bus and buffers, a codec to couple to the communications bus, and a processor to couple to the communications bus. The processor may be arranged to execute instructions for a software modem to determine a round trip delay value for a communications path, and adjust the round trip delay value by varying input to one of the buffers. Other embodiments are described and claimed.

Abstract: A serial bus communication system for communication across the backplane of a node includes a control unit having a serial bus controller operable to convert between parallel signals and serialized signals. A plurality of service units each include a serial bus terminator. A serial bus includes a discrete serial channel for each service unit. The serial channel connects the serial bus terminator to the serial bus controller. The serial bus controller is operable to direct a message for a service unit on the serial bus to only the serial channel of the service unit.

Abstract: In network setting, when setting inputted from a management terminal is inputted into management agent of a CPU blade, the management agent performs network setting to a device driver of the CPU blade, performs setting of NIC to the device driver of the CPU blade and creates network setting information required for a port of an Ethernet switch module unit connected to the NIC to notify the same to a management module unit. The management module unit recognizes a port of Ethernet switch module units which corresponds to the NIC and performs network setting to the port of the Ethernet switch module based on the acquired network configuration information. Accordingly, a technology capable of easily performing the setting of network in a composite computer apparatus in a short time is provided.

Abstract: The invention discloses an information switch, which comprises a management system, a core switching system and an information routing system. The core switching system at least comprises an information bus, a switching module and a switching management module. The information bus comprises an access bus (D-Bus) for connecting with device access gateways, a service bus (S-Bus) for connecting with service gateways, a management bus (M-bus) for connecting with the management system, and a routing bus (R-Bus) for connecting with the information routing system. The management system and the information routing system are connected with core switching via the information bus to perform, respectively, system management and routing management.

Abstract: A distributed system comprises a master node, at least one slave node, and two or more communication channels linking the master node to the at least one slave node. The master node is configured for transmitting the same message to the at least one slave node over each of the two or more communication channels, with a pre-determined delay between each channel transmission. In some embodiments, the system may also include a clock synchronization means configured such that the operation of each slave node is synchronized with the master node and/or a different slave node, irrespective of which channel transmission the slave node receives.

Abstract: A system for path finding and terrain analysis. The system includes at least one processing unit, a graph processing unit and an artificial intelligence logic unit. A local bus is coupled to the at least one processing unit, the graph processing unit, the artificial intelligence unit and a bus interface unit. A memory bus is coupled to said bus interface unit, the at least one processing unit, a data memory, and a program memory. The graph processing unit further includes a network of interconnected nodes. Each of said nodes have at least one digitally programmable delay unit.

Abstract: An Ethernet switch has a header device with a crossbar device and a number of downstream interface modules with a first number of a series of ports and a second number of a series of ports, respectively, such that in each case the same one in the series of the first number of ports is connected to a switching control unit coupled to an interface device, and the further ports in the series of the first number of ports are connected to a port in the second number of the series of ports via respective data lines routed in cascade form.

Abstract: A method may involve: receiving an even number of odd-sized packets for transmission over a double data rate link; re-packetizing the even number of odd-sized packets into several even-sized packets; transmitting the even-sized packets over the double data rate link; and de-packetizing the even-sized packets to reform the even number of odd-sized packets. Re-packetizing may involve dividing each of the even number of odd-sized packets into an even-sized portion and a remaining portion. Each even-sized portion may be transferred as one of the even-sized packets. The remaining portions of each of the even number of odd-sized packets may be combined to form another one of even-sized packets. De-packetizing may involve associating each of several portions of one of the even-sized packets with a respective other one of the even-sized packets.

Abstract: Channel access techniques are provided for use in a high throughput wireless network that utilizes multiple wireless channels within a single service set.

Abstract: A planar backplane is arranged in a horizontal orientation in a server configured for rack mounting. The planar backplane is configured to accept and mount a plurality of disk drives in a vertical orientation in a dense server arrangement.

Abstract: A DMA module includes an address generator to perform a write or read access to a location of an addressable memory, and an address counter to advance a stored address to an adjacent memory location. The address counter does not act on an internal register of the DMA module but instead is configured so that between reading an address value from the memory and writing the address value to the memory, the address counter is advanced once. The memory location at which the address value is read or written takes on the function of a register conventionally integrated in the DMA module. This approach reduces the space requirement of the DMA module, and the DMA module may be employed to control a large number of DMA processes that may mutually interrupt each other by providing a plurality of memory locations to store specifications of the DMA blocks.

Abstract: A system for selectively forming high-speed serial connections between various components of a network device that includes a multiplexing switch coupled a GE slot and to the high speed serial interfaces of a PHY and at least two network devices. The switch can be programmed to connect the serial interfaces of the two network modules to provide a high-speed, low-latency serial link between the two network modules. Alternatively, the serial interface of a network module can be connected to the GE slot to provide a high-speed, low-latency serial link between the network module and the GE slot.

Abstract: A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and a switch adapter for configuring an inner network by interconnecting the channel adapter, memory adapter and processor adapter, wherein the channel adapter, memory adapter, processor adapter and switch adapter each include a DMA controller for performing a communication protocol control of the inner network; and packet multiplex communication is performed among the DMA controllers provided in the adapters. The disk controller can realize a high transfer efficiency and a low cost while retaining a high reliability.

Abstract: In a synchronized data communication on a one-wired bus, it transmits and receives a synchronizing signal that segments part of or all proportions of the data signal by use of three electrically distinguishable statuses for the identifier of the synchronizing signal and the logic states of the data signal to increase the endurance of frequency displacement and resist influences of the interference of external conditions, low quality of transmission medium, and limitation of transmission distance and make the reliability and correctness of the signal transmission improve substantially. It is also clearly illustrated the feasibility and simplicity for implementing the one-wired synchronized communication by a plurality of exemplary signal types and a transceiver circuitry.

Abstract: To display a horizontally oblong movie on a vertically oblong display portion, the movie may be displayed with being rotated 90 degrees by a CPU while the display portion is held in an orientation where the display portion is wider than tall. Since this arrangement puts a heavy load on the CPU, the mobile terminal according to the invention is adapted to implement the movie rotation by processings in the display portion. More specifically, an image memory in the display portion has a foursquare figure each side of which has a length the same as a longer side of a display panel of the display portion. A picture data is written on the memory in the same direction as a direction in which the picture data is read out to be transferred to the panel by the driver portion, and the driver portion rotates the picture data when transferring it.

Abstract: A multiprocessor system having a plurality of processor elements each of which obtains right to use bus of a first or second shared bus in response to a transfer request for control system data or input/output data and as a master, conducts multiplex-transfer or burst-transfer, in which the processor element outputs a bus request signal for the first shared bus in response to a transfer request for the control system data and as a master, transfers and outputs a selection signal, a control signal and an address signal of a transfer destination and the control system data in one cycle in response to application of a bus grant signal, and is selected as a slave based on the selection signal through the first shared bus to receive input of the control system data and process the data based on the control signal and the address signal.

Abstract: Disclosed are improved methods, devices and systems for storage management in digital networks.

Abstract: A switch fabric includes a first plurality of data switches each having a plurality of input ports and a plurality of output ports the plurality of switches capable of switching any of its input ports to any of its output ports with the plurality of data switches having inputs coupled to a plurality of input buses so that a first byte of a first one of the input buses is coupled to a first one of the plurality of switches, and a succeeding byte of the first input bus is coupled to a succeeding one of the plurality of switches.

Abstract: A PBX system using an unmodified personal computer as the host server and using expansion slots to couple one or more switch cards to the system bus, and, optionally including a network interface card to couple the PBX system to other client computers running telephony enabled applications to control the PBX via a local area network. The switch card(s) are each coupled to a chain of one or more port expansion units that do not consume expansion slots. Each PEU contains a DSP and a microcontroller, an FPGA and port interface circuitry to interface to POTS CO lines, extension telephone lines, T1 lines or PRI lines. The personal computer is programmed with a PBX process that controls operations of the overall system and may also be programmed with conventional voice mail applications or integrated voice response and other applications to implement various telephony functions such as recording voice mail or prompt callers to input DTMF tones indicating what they want to do.

Abstract: A network with memory device address decoding that enables communication among integrated processing elements, including a network, a processing element and a bus gasket. The network transfers packets between multiple ports, where each port conforms to a consistent port interface protocol. The processing element includes a bus and a memory device programmed with the address of each port, so that a transaction on the bus indicating another port is decoded by the memory device. The bus gasket includes a bus interface that generates packets and a port interface that sends and receives the packets according to the consistent port interface protocol and that uses the decoded address as a destination port address. The memory device may be implemented in any desired manner, such as a memory management unit (MMU) or a direct memory access (DMA) device.

Abstract: The present invention creates dedicated point-to-point or point-to-multipoint links between different devices along plural busses. Synchronized clocks to each device enable proper timing of read and write operations to/from the bus. The bus connection between the devices are selectively switchable so that dedicated bus connections between devices can be switched on and off as needed. Since the links are point-to-point between sending and receiving devices, the throughput of star-like topology (e.g., Ethernet) can be achieved with very low latency. An arbiter creates the link. The link is established indefinitely, for as long as the arbiter configures it to exist. Additional transactions through the link require only a frame signal to be asserted by the sender and the frame signal to be interpreted as a“data ready” signal by the target.

Abstract: A system for providing a feedback signal in a telecommunications network is provided that includes a plurality of bus control modules, a lower level distribution module, and a timing generator. The bus control modules are operable to generate a feedback signal. The lower level distribution module is coupled to the bus control modules. The lower level distribution module is operable to receive the feedback signal and to insert feedback information for the lower level distribution module into the feedback signal. The timing generator is coupled to the lower level distribution module. The timing generator is operable to receive the feedback signal and to provide the feedback signal to a controller for response.

Abstract: In an NXN switch a plurality of buses interconnect the individual input modules to all of the output modules in a predetermined sequence. The input modules store the received cells and a unique ID. When selected the input module places a cell and its ID on selected ones of the buses along with a multicast vector which identities which of the output modules is to process the cell on a bus. The output modules examine the multicast vector and process the cell (table lookup) if selected In the multicast vector. If an output module is unable to process a required cell (successful table lockup) it sets a retry vector resident on the bus and the input module modifies the multicast vector to indicate only those output module(s) which failed to process a required cell. The cell, the ID and the modified multicast vector are placed on a bus in a subsequent selection of that input module.

Abstract: The Fibre. Channel standard was created by the American National Standard for Information Systems (ANSI) X3T11 task group to define a serial I/O channel for interconnecting a number of heterogeneous peripheral devices to computer systems as well as interconnecting the computer systems themselves through optical fiber and copper media at gigabit speeds (i.e., one billion bits per second). Multiple protocols such as SCSI (Small Computer Serial Interface), IP (Internet Protocol), HIPPI, ATM (Asynchronous Transfer Mode) among others can concurrently utilize the same media when mapped over Fibre Channel. A Fibre Channel Fabric is an entity which transmits Fibre Channel frames between connected Node Ports. The Fibre Channel fabric routes the frames based on the destination address as well as other information embedded in the Fibre Channel frame header. Node Ports are attached to the Fibre Channel Fabric through links.

Abstract: The present invention discloses a method and apparatus for cross-connecting high-speed telecommunications signals at a cross-connect apparatus. The cross-connect apparatus can transmit the telecommunications signals from an input interface card to a cross-connect card, and from the cross-connect card to an output interface card without any synchronization information. Synchronization of the signals is accomplished with circuitry contained on the interface cards and the cross-connect card. The cross-connect apparatus also includes a control unit for managing the control and timing of the apparatus.

Abstract: One embodiment of the present invention provides a system for enhancing the effective timing margins and the reliability of a digital system bus. The system monitors the digital system bus to determine the data flow between devices on the digital system bus. If an absence of data flow is detected, the system generates a pseudo-data signal to replace the normal data signal on the digital system bus. This pseudo-data signal is broadcast on the digital system bus, in order to keep the digital system bus active, thereby preventing subsequent transmissions from suffering from effects caused by an inactive digital system bus.

Abstract: Systems and methods insert broadcast transactions into a fast data stream of transactions. Header packets of transactions of one or more fast data streams are processed into a single fast data stream. Header packets of one of the transactions are generated if the one transaction is a broadcast transaction. Data packets of the transactions of the fast data streams are processed into the single fast data stream such that data packets associated with the one transaction are generated in accordance with a header packet of the one transaction.

Abstract: Implementations of bridges are described and claimed herein, e.g., for use in building automation systems. An exemplary implementation of a bridge for a building automation system comprises a system controller. A first network controller is operatively associated with the system controller to connect the bridge to a local area network. A second network controller is operatively associated with the system controller to connect the bridge to a subnetwork. Computer-readable program code is provided in computer-readable storage operatively associated with the system controller. The computer-readable program code includes: program code for receiving configuration information via the local area network; and program code for configuring an automation device connected to the subnetwork based on the configuration information.

Abstract: Two transfer modes of a band-guaranteed cycle and an event-driven type asynchronous cycle are defined for a multimedia bus. In the band-guaranteed cycle, stream data is transferred between nodes, to which the same channel number is assigned, in peer-to-peer mode using a reserved band for each cycle time. If the same channel number is assigned to a plurality of receiver nodes, a multi-cast transfer can be achieved by the band-guaranteed cycle. The multi-cast transfer using the band-guaranteed cycle can be stopped even in response to an instruction from any receiver node, and a buffer of each receiver node can be prevented from overflowing.

Abstract: In another embodiment, an ASIC device includes a first RAM that stores a code for each of multiple first time slots. Each code is combined with corresponding data from a first bus to specify a previously stored operation. A second RAM receives the combined data and code for each first time slot and applies the specified operation for each first time slot to generate modified data for each first time slot. A third RAM stores information specifying a second time slot to correspond to each first time slot and communicates the information for each second time slot as an address. A fourth RAM stores the modified data for a previous frame and the modified data for a current frame, locates the modified data for each first time slot of the previous frame according to the address, and communicates the modified data for each time slot of the previous frame to a second bus in the corresponding second time slot while the modified data for the current frame is being stored.

Abstract: A rate adjustable backplane includes a set of switch slots configured to receive one or more switch cards forming a switch core and a plurality of line slots each configured to receive a line card. A low speed bus couples the line slots to the set of switch slots. A high speed bus also couples the line slots to the set of switch slots. Each line slot includes a low speed connector coupled to the low speed bus and a high speed connector coupled to the high speed bus. The low speed connector is adapted to receive a mating connector of a line card to establish a low speed communication connection between the line card and the switch core. The high speed connector is adapted to receive a mating connector of the line card to establish a high speed link between the line card and the switch core.

Abstract: A hardware configuration, a general packet radio services support node (GSN) and method for implementing general packet radio services over a global system for mobile communications network is provided. The hardware configuration comprises a plurality of electronic boards which provide the GPRS functionality. An internal bus, preferably CPCI, provides intra-configuration communications while a ATM bus provides communications to an external circuit. The GSN comprises a single board computer for providing general packet radio services functionality which is required for each call being serviced and a line card processor for providing general packet radio services functionality which is required for each packet being serviced. The GSN may function as a SGSN, GGSN or both.

Abstract: A method and apparatus for maintaining packet order integrity in a switching engine wherein inbound packets are forwarded to different ones of parallel processing elements for switching. Order preservation for packets relating to the same conversation is guaranteed by checking for each inbound packet whether a previous packet from the same source is pending at a processing element and, if the check reveals that such a packet is pending, forwarding the inbound packet to the same processing element as the previous packet.

Abstract: A peripheral bus jumper block that establishes an external peripheral bridge for linking independent peripheral bus signal paths (i.e., sets of electrical traces formed on a peripheral bus panel) of a peripheral bus interconnect system so that the signal paths have the functional equivalent of a single, continuous peripheral bus path. Accordingly, arrays of computer peripherals (e.g. disk drives) that are coupled to the peripheral bus signal paths within a peripheral device enclosure are chained together so as to be capable of being operated by the same computer controller, whereby the peripheral bus interconnect system can be selectively reconfigured to improve system flexibility. The peripheral bus jumper block has a pair of peripheral bus connectors that are detachably connected to respective peripheral bus connectors from a pair of the peripheral bus signal paths that are to be linked together.

Abstract: An electronic system for networking, switching or computing includes a backplane-based interconnection system (100). The system includes a backplane (102) with a plurality of traces coupled to slots for receiving circuit packs (104a-d). The backplane traces are configured to form point-to-point connections (106a-f) from one slot of the backplane to every other slot of the backplane. A hub circuit (110) is provided on each circuit pack for coupling the circuit pack to the point-to-point connections in the backplane. Circuit packs communicate via direct connections over the point-to-point connections or indirectly by sending traffic through point-to-point connections and hub circuits.

Abstract: A computer system, for example for use as a server, comprises a host processor, a service processor for providing system management functions within the computer system, and a user interface for receiving external commands and data for the service processor and/or the host processor, and for sending data from the service processor and/or the host processor. A device is provided for routing the commands and data to and from the user interface via the service processor only when the device receives a signal from the service processor. In the absence of the signal, the commands and data are sent between the user interface and the console interface bypassing the service processor. By this means, the host processor may be addressed even if the service processor malfunctions.

Abstract: A method for communicating from a source port (i) to a destination port (j) is employed within a switching system that has m ports, each of the ports being coupled to a local area network via a Hub. The connectivity between the inputs and outputs of the m ports forms a matrix of cross points having m rows and m columns. Each port has a transmit line coupled to a row of the matrix and a receive line coupled to a column of the matrix. A transmission operation from the source port (i) to the destination port (j) involves a first control circuit for unilaterally connecting the port (i) to the port (j), a second control circuit for unilaterally connecting the port (j) to the port (i). The method includes the use of a third control circuit, and a column control bus that couples the third control circuit to a plurality of control circuits including the second control circuit.

Abstract: In-band flow control data may be received from a switch fabric at a first network processor. The received in-band flow control data may be transmitted to a second network processor using a flow control bus. The second network processor may determine which receive queues in the switch fabric exceed a predetermined overflow threshold based on the in-band flow control data. The second processor may transmit data to the receive queues in the switch fabric determined not to exceed the predetermined overflow threshold.

Abstract: A system and method of operation for connecting at least one USB function to at least two USB hosts is presented. The system of provides a USB tree between each USB host and the at least one USB function. The system further contains provisions for isolating a given USB host from the at least one USB function.

Abstract: A serial bus communication system for communication across the backplane of a node includes a control unit having a serial bus controller. A plurality of service units each include a serial bus terminator. A serial bus includes a discrete serial channel for each service unit. The serial channel connects the serial bus terminator to the serial bus controller. The serial bus controller is operable to direct a message for a service unit on the serial bus to only the serial channel of the service unit.

Abstract: Ad-hoc timing signals are transferred from a first circuit to a second circuit by determining a system transit delay, detecting an edge of an ad-hoc signal and the frame and timeslot that correspond with the edge, and regenerating the ad-hoc timing signal based on the system transit delay and the frame and timeslot that correspond with the edge.

Abstract: In a synchronized data communication on a one-wired bus, it transmits and receives a synchronizing signal that segments part of or all proportions of the data signal by use of three electrically distinguishable statuses for the identifier of the synchronizing signal and the logic states of the data signal to increase the endurance of frequency displacement and resist influences of the interference of external conditions, low quality of transmission medium, and limitation of transmission distance and make the reliability and correctness of the signal transmission improve substantially. It is also clearly illustrated the feasibility and simplicity for implementing the one-wired synchronized communication by a plurality of exemplary signal types and a transceiver circuitry.

Abstract: An integrated circuit device having multiple communication modes is provided. The integrated circuit device includes a transceiver coupled to first and second data lines. The integrated circuit device further includes a voltage control circuit. The voltage control circuit determines whether or not an external device is connected to the integrated circuit device. In the case where the external device is connected to the integrated circuit device, the voltage control circuit controls the voltage of the first data line so as to cause the external device to not recognize the integrated circuit device for a predetermined time.

Abstract: A circuit and special cable which allow a single DB9 connector to provide a standard RS-232 interface to a RAID controller in single RAID controller systems or to provide a controller-to-controller communication link for messaging, control and status signals when the special cable is used to interconnect two RAID controllers in a dual-active system.

Abstract: A method for testing and safeguarding the availability of a networked system which is assigned to a system carrier, wherein a multiplicity of subscribers exchange data via a bus-type network which is comprised of one or more bus lines. Specific voltage levels are applied to the bus line or the lines by the appropriate subscribers. By virtue of this, as a minimum, at least individual subscribers transmit data. The bus line or the lines is/are monitored by the at least one receiving subscriber for an overshoot or undershoot of voltage levels. Due to this, the data is evaluated in at least one receiving subscriber with the aid of voltage levels. During operation of the system, signals present on the bus-type network are discriminated, tested or measured with respect to at least one signal criterion by individual subscribers under conditions defined in a network-wide manner for all subscribers.

Abstract: The invention relates to an electrical device (LNK) which has means (DP-S, K′) for forming a communication connection to a field bus (DP) and additional means (PA-M, FF-M, K) for forming a communication connection to an additional field bus (PAFF). Said device is thus presented as a combination of three communication stations (DP-S, PA-M, FF-M) for the respective connection to a field bus (DP, PA, FF).

Abstract: A distributed method and apparatus for assigning a unique identifier number to devices connected in a sequential fashion and determining a total device count is presented. Additionally, a method and apparatus for enabling the support of a variable number and type of time slots within a time division multiplexed serial protocol is presented.

Abstract: A network of switches having a first switch having a first memory interface and a first expansion port. The network also has an expansion bus having a first expansion bus interface and a second expansion bus interface. The first expansion bus interface is connected to the first expansion port. A second switch has a second memory interface and a second expansion port. The second expansion port is connected to the second expansion bus interface, thereby connecting the first switch to the second switch, wherein the expansion bus allows the first switch to directly access the second memory interface through the second switch and the second switch to directly access the first memory interface through the first switch.

Abstract: In one embodiment of the present invention, a bus controller is used in a multi-master system having first and second processors. The bus controller includes a bus arbiter and a first multiplexer. The bus arbiter is coupled to the first and second processors via first and second master buses, respectively, to generate an arbitration select signal based on result of arbitrating bus access information from the first and second processors. The first multiplexer is coupled to the first and second master buses and a first slave bus in a plurality of slave buses to provide device access information selected from the bus access information using the arbitration select signal. The device access information is transferred to a first slave device connected to the first slave bus.